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2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab5-682/+964
ARMv8.2 adds 16-bit floating point operations as an optional extension to the ARMv8 FP support. This patch adds the new FP16 instructions, making them available when the architecture extension +fp+fp16 is specified. The instructions added are: - Comparisons and conditionals: FCMP, FCCMPE, FCMP, FCMPE and FCSEL. - Arithmetic: FABS, FNEG, FSQRT, FMUL, FDIV, FADD, FSUB, FMADD, FMSUB, FNMADD and FNMSUB. - Rounding: FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX and FRINTI. - Conversions: SCVTF (fixed-point), SCVTF (integer), UCVTF (fixed-point) UCVTF (integer), FCVTZS (fixed-point), FCVTZS (integer), FCVTZU (fixed-point), FCVTZU (integer), FCVTNS, FCVTNU, FCVTAS, FCVTAU, FCVTPS, FCVTPU, FCVTMS and FCVTMU. - Scalar FMOV: immediate, general and register gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/float-fp16.d: New. * gas/aarch64/float-fp16.s: New. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. (QL_INT2FP_H, QL_FP2INT_H): New. (QL_FP2_H, QL_FP3_H, QL_FP4_H): New (QL_DST_H): New. (QL_FCCMP_H): New. (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and fcsel. Change-Id: Ie6d40bd1b215a9bc024e12ba75e52afbe1675eb7
2015-11-27[AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab2-7/+37
ARMv8.2 adds 16-bit floating point operations as an optional extension. This patch adjusts the utility function expand_fp_imm to support 16-bit values. The function is intended to convert an 8-bit immediate representing a floating point value to a representation that can be passed to fprintf. Because of the limited use of the results, the only change made to the function is to treat a request for a 16-bit float as a request for a 32-bit float. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (half_conv_t): New. (expand_fp_imm): Replace is_dp flag with the parameter size to specify the number of bytes for the required expansion. Treat a 16-bit expansion like a 32-bit expansion. Add check for an unsupported size request. Update comment. (aarch64_print_operand): Update to support 16-bit floating point values. Update for changes to expand_fp_imm. Change-Id: I1ae3df3864be375d71925197ab03397ed1ad2d15
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab2-0/+8
ARMv8.2 adds 16-bit floating point operations as an optional extension to the ARMv8 FP support. This patch set adds support for the 16-bit FP instructions to binutils, enabling the instructions when both +fp and +fp16 architecture extensions are enabled. The patches in this series: - Add a feature macro for use by the encoding/decoding mechanism. - Adjust a utility function, used when disassembling, to support 16-bit floating point values. - Add the new scalar floating-point instructions. This patch adds the feature macro FP_F16 to the AArch64 encoding/decoding mechanism, enabling it when both +fp and +fp16 are selected. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-tbl.h (aarch64_feature_fp_f16): New. (FP_F16): New. Change-Id: Ie370e43e3d77a7d54b4416b4be901b363a37f3d5
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab5-768/+785
This patch adds the alias REV64 <Rd>, <Rs> as an alias for REV <Rd>, <Rs>. However, REV is still the preferred form for the instruction. gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/alias-2.d: Add tests for REV. * gas/aarch64/alias-2.s: Likewise. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add "rev64". Change-Id: I331567c8d3618ba9fec1673c6e0b5977222dde61
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab8-861/+967
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as an alias for REV. This patch set adds support for these to binutils, enabled when the -march=armv8.2-a is given. It depends on the support for an instruction being its preferred form which was added in an earlier patch. This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred form for BFM when the source is a zero register and the conditions for using the BFI form are met (in other words, BFC is the preferred form for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register). gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/alias-2.d: New. * gas/aarch64/alias-2.s: New. include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_op): Add OP_BFC. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-asm.c (convert_bfc_to_bfm): New. (convert_to_real): Add case for OP_BFC. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c: (convert_bfm_to_bfc): New. (convert_to_alias): Add case for OP_BFC. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert to allow width operand in three-operand instructions. * aarch64-tbl.h (QL_BF1): New. (aarch64_feature_v8_2): New. (ARMV8_2): New. (aarch64_opcode_table): Add "bfc". Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab5-2/+202
Although the AArch64 backend supports aliased instructions, the aliasing forms are always preferred over the real instruction. This makes it awkward to handle instructions which have aliases but which are their own preferred form. This patch includes the instruction being aliased in the list of alternatives which is searched when considering which form to use. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c: Weaken assert. * aarch64-gen.c: Include the instruction in the list of its possible aliases. Change-Id: I1f23eb25fccef76a64d3d732d58761bd25fad94e
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab2-0/+11
ARMv8.2 adds a new system register id_aa64mmfr2_el1. This patch adds support for the register to binutils, making it available when -march=armv8.2-a is selected. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1". (aarch64_sys_reg_supported_p): Add ARMv8.2 system register feature test. gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: New. * gas/aarch64/sysreg-2.s: New. Change-Id: I767f18a60e2bd70ce74c89f6abfe07afdc9e601f
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold2-0/+12
opcodes/ * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2-0/+78
The ARMv8.1 architecture includes the Virtualization Host Extensions which add a number of system registers. This patch adds support for these system registers, making them available when -march=armv8.1-a is selected. include/opcode/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_1): New. (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. opcodes/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, amair_el12, vbar_el12, contextidr_el2, contextidr_el12, cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, cnthv_ctl_el2, cnthv_cval_el2. (aarch64_sys_reg_supported_p): Update for the new system registers. gas/testsuite/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/virthostext-directive.d: New. * gas/aarch64/virthostext.d: New. * gas/aarch64/virthostext.s: New. Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
2015-11-20Remove a if-clause that is redundant because the same test has been ↵Nick Clifton2-4/+5
performed earlier on. PR binutils/19224 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
2015-11-20Update translations.Nick Clifton2-317/+1153
binutils * po/ca.po: New Catalan translation. * configure.ac (ALL_LINGUAS): Add ca. * configure: Regenerate. gas * po/fr.po: Updated French translation. * po/uk.po: Updated Ukraninan translation. * po/zh_CN.po: New simplified Chinese translation. * configure.ac (ALL_LINGUAS): Add zh_CN. * configure: Regenerate. opcodes * po/zh_CN.po: Updated simplified Chinese translation.
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab2-0/+13
The support for accessing the ARMv8.1 PSTATE field PAN allows instructions of the form MSR PAN, #<imm> with <imm> any unsigned 4-bit integer. However, the architecture specification requires that the immediate is either 0 or 1. This patch implements the constraint on the immediate, generating an error if the immediate operand is invalid, and adds tests for the illegal forms. opcodes/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Check validity of MSR PAN immediate operand. gas/testsuite/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/pan-illegal.d: New. * gas/aarch64/pan-illegal.l: New. * gas/aarch64/pan.s: Add tests for invalid immediates. Change-Id: Ibb3056c975eb792104da138d94594224f56a993e
2015-11-17Fix the disassembly of conditional instructions will illegal condition ↵Nick Clifton2-1/+6
selections. * rx-dis.c (condition_names): Replace always and never with invalid, since the always/never conditions can never be legal.
2015-11-14Bump version to 2.26.51Tristan Gingold2-10/+14
bfd/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.26.51 * configure: Regenerate. binutils/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2015-11-13 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner3-107/+686
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-11-09Move copy_u.w to MSA64 ASE, remove copy_u.d.Robert Suchanek1-2/+1
opcodes/ChangeLog: * mips-opc.c (mips_builtin_opcodes): Change "copy_u.w" to MSA64 ASE, remove "copy_u.d". gas/testsuite/ChangeLog: * gas/mips/micromips@msa.d: Remove "copy_u.w". * gas/mips/msa.d: Likewise. * gas/mips/msa.s: Likweise. * gas/mips/mipsr6@msa.d: Likewise. Replace addresses with regex. * gas/mips/msa64.d: Add "copy_u.w". Remove "copy_u.d". * gas/mips/msa64.s: Likewise. * gas/mips/micromips@msa64.d: Likewise.
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton3-18/+98
opcode * rx.h (enum RX_Opcode_ID): Add more NOP opcodes. opcodes * rx-decode.opc (rx_decode_opcode): Decode extra NOP instructions. * rx-decode.c: Regenerate. tests * gas/rx/max.d: Update expecetd disassembly. * gas/rx/nod.d: Likewise. * gas/rx/nop.sm: Add tests of more NOP instructions.
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton4-7/+14
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the type to RX_Operand_Zero_Indirect. * rx-decode.c: Regenerate. * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. gas * config/rx-parse.y: Allow zero value for 5-bit displacements. tests * gas/rx/mov.sm: Add tests for zero offset indirect moves. * gas/rx/mov.d: Update expected output.
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi2-5/+15
Nowadays aarch64_decode_insn is a public interface used by both opcodes and gdb. However, its behaviour relies on a global variable no_aliases, which isn't a good practise. On the other hand, In default, no_aliases is zero, but in GDB, we do want no alias when decoding instructions for prologue analysis (patches to be posted), so that we can handle both instructions "add" and "mov" (an alias of "add") as "add". The code in GDB can be simplified. This patch adds a new argument in aarch64_decode_insn, and pass no_aliases to it. In GDB side, always pass 1 to it. include/opcode: 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64.h (aarch64_decode_insn): Update declaration. opcodes: 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (aarch64_decode_insn): Add one argument noaliases_p. Update comments. Pass noaliases_p rather than no_aliases to aarch64_opcode_decode. (print_insn_aarch64_word): Pass no_aliases to aarch64_decode_insn. gdb: 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_software_single_step): Pass 1 to aarch64_decode_insn.
2015-10-27Fix RL78 disassembly of DE+offset addressing to always show the offset, even ↵Vinay Kumar3-24/+31
when zero. PR binutils/19159 opcodes * rl78-decode.opc (MOV): Added offset to DE register in index addressing mode. * rl78-decode.c: Regenerate. test * gas/rl78/pr19159.s: New test source file. * gas/rl78/pr19159.d: New test case. * gas/rl78/rl78.exp: Run the new test.
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar4-13/+34
PR binutils/19158 opcodes * rl78-decode.opc: Add 's' print operator to instructions that access system registers. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78_common): Decode all system registers. tests * gas/rl78/pr19158.s: New test source file. * gas/rl78/pr19158.d: New test case. * gas/rl78/rl78.exp: Run the new test.
2015-10-27Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ↵Vinay Kumar3-20/+27
even when zero. PR binutils/19157 opcodes * rl78-decode.opc: Add 'a' print operator to mov instructions using stack pointer plus index addressing. * rl78-decode.c: Regenerate. tests * gas/rl78: New directory. * gas/rl78/rl78.exp: New test driver. * gas/rl78/pr19157.s: New test source file. * gas/rl78/pr19157.d: New test case.
2015-10-14Add missing changelog entriesAndreas Krebbel1-0/+7
2015-10-14S/390: Fix instruction type of troo, trot, trto, and trtt.Andreas Krebbel2-5/+5
opcodes/ChangeLog: 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Fix comment. * s390-opc.txt: Change instruction type for troo, trot, trto, and trtt to RRF_U0RER since the second parameter does not need to be a register pair. gas/testsuite/ChangeLog: 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/s390/esa-g5.d: Use odd GPR for the second operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise.
2015-10-08Fix compile time warning compiling ARC port.Nick Clifton2-1/+6
2015-10-07Avoid using 'template' C++ keywordYao Qi3-3/+9
'template' is used in include/opcode/aarch64.h as below, typedef struct { const char *template; uint32_t value; int has_xt; } aarch64_sys_ins_reg; and it triggers compilation errors when GDB is built in C++ mode. In file included from git/gdb/aarch64-tdep.c:62:0: git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template' const char *template; This patch is to rename field template to name. gas/ * config/tc-aarch64.c (md_begin): Access field 'name' rather than 'template'. include/opcode/ * aarch64.h (aarch64_sys_ins_reg) <template>: Removed. <name>: New field. opcodes/ * aarch64-dis.c (aarch64_ext_sysins_op): Access field 'name' rather than 'template'. * aarch64-opc.c (aarch64_print_operand): Likewise.
2015-10-07New ARC implementation.Nick Clifton9-2824/+21958
bfd * archures.c: Remove support for older ARC. Added support for new ARC cpus (ARC600, ARC601, ARC700, ARCV2). * bfd-in2.h: Likewise. * config.bfd: Likewise. * cpu-arc.c: Likewise. * elf32-arc.c: Totally changed file with a refactored inplementation of the ARC port. * libbfd.h: Added ARC specific relocation types. * reloc.c: Likewise. gas * config/tc-arc.c: Revamped file for ARC support. * config/tc-arc.h: Likewise. * doc/as.texinfo: Add new ARC options. * doc/c-arc.texi: Likewise. ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*. * emulparams/arcebelf_prof.sh: New file * emulparams/arcebelf.sh: Likewise. * emulparams/arceblinux_prof.sh: Likewise. * emulparams/arceblinux.sh: Likewise. * emulparams/arcelf_prof.sh: Likewise. * emulparams/arcelf.sh: Likewise. * emulparams/arclinux_prof.sh: Likewise. * emulparams/arclinux.sh: Likewise. * emulparams/arcv2elfx.sh: Likewise. * emulparams/arcv2elf.sh: Likewise. * emultempl/arclinux.em: Likewise. * scripttempl/arclinux.sc: Likewise. * scripttempl/elfarc.sc: Likewise. * scripttempl/elfarcv2.sc: Likewise * Makefile.am: Add new ARC emulations. * Makefile.in: Regenerate. * NEWS: Mention the new feature. opcodes * arc-dis.c: Revamped file for ARC support * arc-dis.h: Likewise. * arc-ext.c: Likewise. * arc-ext.h: Likewise. * arc-opc.c: Likewise. * arc-fxi.h: New file. * arc-regs.h: Likewise. * arc-tbl.h: Likewise. binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact and ARCv2. (get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Likewise. * NEWS: Mention the new feature. include * dis-asm.h (arc_get_disassembler): Correct declaration. * arc-reloc.def: Macro file with definition of all relocation types. * arc.h: Changed macros for the newly supported ARC cpus. Altered enum defining the supported relocations. * common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added macro for EM_ARC_COMPACT2. * arc-func.h: New file. * arc.h: Likewise.
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi2-4/+12
We want to use disas_aarch64_insn inside GDB to decode instructions, so this patch exposes it and rename it to aarch64_decode_insn to follow the conventions of other interfaces. include/opcode: 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64.h (aarch64_decode_insn): Declare it. opcodes: 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (disas_aarch64_insn): Remove static. Change argument insn type to aarch64_insn. Rename to ... (aarch64_decode_insn): ... it. (print_insn_aarch64_word): Caller updated.
2015-10-02[aarch64] Remove argument pc from disas_aarch64_insnYao Qi2-3/+7
I happen to see that argument pc is not used inside disas_aarch64_insn at all. This patch is to remove it. OK to apply? opcodes: 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (disas_aarch64_insn): Remove argument PC. (print_insn_aarch64_word): Caller updated.
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ↵Dominik Vogt3-508/+522
zEC12+nohtm+vx" gas * doc/c-s390.texi: Add documentation. Add missing code markup. * config/tc-s390.c (current_flags): New static variable. (s390_parse_cpu): Parse cpu flags a la "+nohtm" etc. (s390_setup_opcodes): Use cpu flags to determine the set of opcodes. Fix indentation. (md_parse_option): Call s390_parse_cpu with the new signature. (s390_machine): Likewise. Keep track of current_flags. Simplify code a bit. undefine MAX_HISTORY at end of function. (s390_machinemode): undefine MAX_HISTORY at end of function. Update an error message. tests * gas/s390/s390.exp: Add new tests. * gas/s390/machine-parsing-1.s: New test file. * gas/s390/machine-parsing-1.l: Likewise. * gas/s390/machine-parsing-2.s: Likewise. * gas/s390/machine-parsing-2.l: Likewise. * gas/s390/machine-parsing-3.s: Likewise. * gas/s390/machine-parsing-3.l: Likewise. * gas/s390/machine-parsing-4.s: Likewise. * gas/s390/machine-parsing-4.l: Likewise. * gas/s390/machine-parsing-5.s: Likewise. * gas/s390/machine-parsing-5.l: Likewise. * gas/s390/machine-parsing-6.s: Likewise. * gas/s390/machine-parsing-6.l: Likewise. opcode * s390.h (S390_INSTR_FLAG_HTM): New flag. (S390_INSTR_FLAG_VX): New flag. (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. opcodes * s390-mkopc.c (main): Parse htm and vx flag. * s390-opc.txt: Mark instructions from the hardware transactional memory and vector facilities with the "htm"/"vx" flag.
2015-09-28Updare French translation for binutils and German translation for opcodes.Nick Clifton2-3/+7
2015-09-28Patches for illegal ppc 500 instructionsTom Rix2-7/+11
This change marks a few opcodes as invalid for ppc e500 as well as adds a test to verify the change.
2015-09-25The FT32's disassembly of 10-bit literals has the incorrect mask.jamesbowman1-1/+1
[opcodes] * ft32-dis.c (print_insn_ft32): Fix incorrect data field mask.
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton11-44/+50
bfd * bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in order to avoid problems with left shifting negative values. (abs32code): Likewise. * mach-o.c (FILE_ALIGN): Likewise. * coff-rs6000.c (xcoff_debug_sections): Delete unused static array. * elf32-visium.c (visium_reloc_map): Likewise. * elf32-arm.c (elf32_arm_final_link_relocate): Remove useless calls to abs function. * elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise. * elf32-score.c (score_elf_final_link_relocate): Likewise. * elf32-score7.c (score_elf_final_link_relocate): Likewise. * elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead of shifting to create a negative mask. * elf32-msp430.c (elf_backend_special_sections): Define. * elfxx-mips.c (got_ofst_reloc_p): Delete unused function. (got_hi16_reloc_p): Delete unused function. * ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of partition name. gas * config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int. opcode * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left shifting. ld * emultempl/elf32.em (ehdr_start_empty): New static variable. (before_allocation): Use it to initialise ehdr_start_save. * emultempl/pe.em (write_build_id): Remove useless double parenthesis. * emultempl/pep.em (write_build_id): Likewise. opcodes * bfin-dis.c (fmtconst): Remove unnecessary call to the abs function. * tic30-dis.c (print_branch): Likewise. * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed value before left shifting. * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. * hppa-dis.c (print_insn_hppa): Likewise. * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static array. * msp430-dis.c (msp430_singleoperand): Likewise. (msp430_doubleoperand): Likewise. (print_insn_msp430): Likewise. * nds32-asm.c (parse_operand): Likewise. * sh-opc.h (MASK): Likewise. * v850-dis.c (get_operand_value): Likewise.
2015-09-22Enhance the RX disassembler to detect and report bad instructions.Nick Clifton4-28/+57
opcode * rx.h (enum RX_Size): Add RX_Bad_Size entry. opcodes * rx-decode.opc (bwl): Use RX_Bad_Size. (sbwl): Likewise. (ubwl): Likewise. Rename to ubw. (uBWL): Rename to uBW. Replace all references to uBWL with uBW. * rx-decode.c: Regenerate. * rx-dis.c (size_names): Add entry for RX_Bad_Size. (opsize_names): Likewise. (print_insn_rx): Detect and report RX_Bad_Size.
2015-09-22opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonicsAnton Blanchard2-0/+8
opcodes/ * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
2015-09-10S/390: Fix instruction format of crj*, clrj*, and clgrj*.Andreas Krebbel1-3/+3
This fixes the instruction format for 3 of the compare and branch extended mnemonics. That way the extended mnemonics are actually being found by objdump. gas/testsuite/ChangeLog: 2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/s390/zarch-z10.d: Fix testcase for some of the compare and branch extended mnemonics. opcodes/ChangeLog: 2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt: Fix instruction format of crj*, clrj*, and clgrj*.
2015-09-10S/390: Remove F_20 and FE_20. Adjust comments.Andreas Krebbel1-70/+66
This is cleanup only. opcodes/ChangeLog: 2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Remove unused (and broken) F_20 and FE_20 operand types and adjust numbering accordingly. Fix some comments.
2015-09-10S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.Andreas Krebbel1-2/+2
This makes objdump to be able to recognize some of the extended mnemonics more often. It does not lead to wrong being generated. opcodes/ChangeLog: 2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Fix MASK_RIE_R0PI and MASK_RIE_R0PU. gas/testsuite/ChangeLog: 2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/s390/zarch-z10.d: Fix testcase for compare and branch extended mnemonics.
2015-09-09S/390: Remove trailing zeros on 4-bytes opcodes.Andreas Krebbel2-7/+9
This is a NOP change only relevant when reading the file or parsing it with other tools. opcodes/ChangeLog: 2015-09-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Add OP32 definition. * s390-opc.txt: Reduce the opcode padding of some extended mnemonics from 6 to the actual length (which is 4).
2015-09-09S/390: Fix opcode of ppno.Andreas Krebbel1-1/+1
opcodes/ChangeLog: 2015-09-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt: Fix opcode of ppno instruction. gas/testsuite/ChangeLog: 2015-09-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/s390/zarch-z13.d: Fix opcode of ppno instruction.
2015-08-25Support for the sparc %pmcdper privileged register.Jose E. Marchesi2-2/+11
opcodes/ChangeLog: 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (print_insn_sparc): Handle the privileged register %pmcdper. gas/ChangeLog: 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (priv_reg_table): New privileged register %pmcdper. gas/testsuite/ChangeLog: 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> * gas/sparc/wrpr.s: Test writing to the privileged %pmcdper register. * gas/sparc/wrpr.d: ...and the expected result. * gas/sparc/rdpr.s: Test reading from the privileged %pmcdper register. * gas/sparc/rdpr.d: ...and the expected result.
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ↵Jan Stancek2-2/+8
a function. opcodes * i386-dis.c (print_insn): Fix decoding of three byte operands. tests * gas/i386/intel.s: Add test of disassembly of a potential three byte instuction at the end of a function. * gas/i386/intel.d: Update expected disassembly.
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin2-59/+450
opcodes/ PR binutils/18257 * i386-dis.c: Use MOD_TABLE for most of mask instructions. (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. (vex_w_table): Replace terminals with MOD_TABLE entries for most of mask instructions. gas/testsuite PR binutils/18257 * gas/i386/disassem.s: Add mask instructions with invalid ModR/M byte. * gas/i386/x86-64-disassem.s: Likewise. * gas/i386/disassem.d: Updated. * gas/i386/x86-64-disassem.d: Likewise.
2015-08-17Trailing space in opcodes/ generated filesAlan Modra5-845/+835
HJ recently removed trailing space in binutils files, but unfortunately they return when regenerating files in opcodes. This fixes the regen process. * cgen.sh: Trim trailing space from cgen output. * ia64-gen.c (print_dependency_table): Don't generate trailing space. (print_dis_table): Likewise. * opc2c.c (dump_lines): Likewise. (orig_filename): Warning fix. * ia64-asmtab.c: Regenerate.
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira2-3/+19
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6 and higher with ARM instruction set will now mark the 26-bit versions of teq,tst,cmn and cmp as UNPREDICTABLE. (arm_opcodes): Fix for unpredictable nop being recognized as a teq. test * gas/arm/nops.d: New. * gas/arm/nops.s: New. * gas/arm/inst.d: Changed expectation file for 26-bit teq, tst, cmn and cmp.
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis3-3/+8
The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This change affects microMIPS, MIPS32, MIPS64. 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> opcodes/ * micromips-opc.c (micromips_opcodes): Re-order table so that move based on 'or' is first. * mips-opc.c (mips_builtin_opcodes): Ditto. bfd/ * elfxx-mips.c (STUB_MOVE): Change to use 'or' only. (mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry, mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry): Update to use 'or' instead of 'addu/daddu'. (_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE. (move_insns_32): Reorder table. gas/ * config/tc-mips.c (move_register): Change to use 'or' only. (s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to use or for move. gas/testsuite/ * gas/mips/elf-rel23.d: Update test. * gas/mips/elf-rel23.d: Ditto. * gas/mips/elf-rel23a.d: Ditto. * gas/mips/elf-rel23b.d: Ditto. * gas/mips/elf_e_flags1.d: Ditto. * gas/mips/elf_e_flags2.d: Ditto. * gas/mips/elf_e_flags3.d: Ditto. * gas/mips/elf_e_flags4.d: Ditto. * gas/mips/loc-swap-dis.d: Ditto. * gas/mips/micromips-insn32.d: Ditto. * gas/mips/micromips-noinsn32.d: Ditto. * gas/mips/micromips-trap.d: Ditto. * gas/mips/micromips.d: Ditto. * gas/mips/mips-abi32-pic.d: Ditto. * gas/mips/mips-abi32.d: Ditto. * gas/mips/mips-gp32-fp32-pic.d: Ditto. * gas/mips/mips-gp32-fp32.d: Ditto. * gas/mips/mips-gp32-fp64-pic.d: Ditto. * gas/mips/mips-gp32-fp64.d: Ditto. * gas/mips/mips-gp64-fp32-pic.d: Ditto. * gas/mips/mips-gp64-fp32.d: Ditto. * gas/mips/mips-gp64-fp64-pic.d: Ditto. * gas/mips/mips-gp64-fp64.d: Ditto. * gas/mips/mipsr6@loc-swap-dis.d: Ditto. * gas/mips/tls-o32.d: Ditto. * gas/mips/uld2-eb.d: Ditto. * gas/mips/uld2-el.d: Ditto. * gas/mips/ulw2-eb-ilocks.d: Ditto. * gas/mips/ulw2-eb.d: Ditto. * gas/mips/ulw2-el-ilocks.d: Ditto. * gas/mips/ulw2-el.d: Ditto. * gas/mips/move.d: New test. * gas/mips/move.s: Ditto. * gas/mips/micromips32-move.d: Ditto. * gas/mips/micromips32-move.s: Ditto. * gas/mips/mips.exp: Run the new tests. gold/ * mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64, lazy_stub_normal_1, lazy_stub_normal_1_n64, lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big, lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64, lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big, lazy_stub_micromips32_big_n64): Update to use 'or' for move instead of 'addu/daddu'. ld/testsuite/ * ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test. * ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-se.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto. * ld-mips-elf/jalx-2.dd: Ditto. * ld-mips-elf/mips16-pic-3.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3a.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-5b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto. * ld-mips-elf/stub-dynsym-1-10000.d: Ditto. * ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto. * ld-mips-elf/stub-dynsym-1-7fff.d: Ditto. * ld-mips-elf/stub-dynsym-1-8000.d: Ditto. * ld-mips-elf/stub-dynsym-1-fff0.d: Ditto. * ld-mips-elf/tlsbin-o32.d: Ditto. * ld-mips-elf/tlsdyn-o32-1.d: Ditto. * ld-mips-elf/tlsdyn-o32-2.d: Ditto. * ld-mips-elf/tlsdyn-o32-3.d: Ditto. * ld-mips-elf/tlsdyn-o32.d: Ditto. * ld-mips-elf/tlslib-o32.d: Ditto.
2015-08-12Remove trailing spaces in opcodesH.J. Lu137-4012/+4012
2015-08-11Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton2-1/+7
PR 18800 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT instruction.
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek2-0/+5
opcodes/ * mips-opc.c (mips_builtin_opcodes): Add "sigrie". gas/testsuite/ * gas/mips/r6.s: Add tests for "sigrie". * gas/mips/r6.d: Check for "sigrie". * gas/mips/r6-n32.d: Likewise. * gas/mips/r6-n64.d: Likewise.
generated by cgit v1.1 at 2025-02-13 12:46:58 +0000