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2021-04-01Remove strneq macro and use startswith.Martin Liska5-18/+9
bfd/ChangeLog: * ecoff.c (strneq): Remove strneq and use startswith. (_bfd_ecoff_slurp_armap): Likewise. binutils/ChangeLog: * elfcomm.h (strneq): Remove strneq and use startswith. * readelf.c (ia64_process_unwind): Likewise. (process_note): Likewise. gas/ChangeLog: * config/obj-coff.c (strneq): Remove strneq and use startswith. (weak_is_altname): Likewise. (obj_coff_section): Likewise. * config/tc-cr16.c (process_label_constant): Likewise. * config/tc-crx.c (strneq): Likewise. include/ChangeLog: * opcode/cr16.h (strneq): Remove strneq and use startswith. ld/ChangeLog: * ldbuildid.c (strneq): Remove strneq and use startswith. (validate_build_id_style): Likewise. (compute_build_id_size): Likewise. opcodes/ChangeLog: * arm-dis.c (strneq): Remove strneq and use startswith. * cr16-dis.c (print_insn_cr16): Likewise. * score-dis.c (streq): Likewise. (strneq): Likewise. * score7-dis.c (strneq): Likewise.
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra2-0/+7
PR 27675 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
2021-03-31Use bool in opcodesAlan Modra49-1573/+1591
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
2021-03-31Remove bfd_stdint.hAlan Modra12-11/+25
If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-03-30x86: drop seg_entryJan Beulich3-21/+17
Use struct reg_entry instead for most purposes, with a separate array holding just the respective opcode prefix bytes.
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2-5/+4
The former two are unused anyway. And having such constants isn't very helpful either, when they live in a place where updating the register table wouldn't even allow noticing the need to adjust these constants.
2021-03-30x86: adjust st(<N>) parsingJan Beulich4-12/+13
st(1) ... st(7) will never be looked up in the hash table, so there's no point inserting the entries. It's also not really necessary to do a 2nd hash lookup after parsing the register number, nor is there a real reason for having both st and st(0) entries. Plus we can easily do away with the need for st to be first in the table.
2021-03-29x86: move some opcode table entriesJan Beulich3-489/+500
For a long time there hasn't been a need anymore to keep together all templates with identical mnemonics. Move the MOVQ and MOVABS ones next to their MOV counterparts. Move the string forms of CMPSD and MOVSD next to their CMPS / MOVS counterparts. Re-arrange what so fgar was the SSE3 section. This makes reasonably obvious that MONITOR/MWAIT aren't suitable to cover by CpuSSE3, but adjusting this is left for another time.
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich3-6/+12
In commit 79dec6b7baa2 ("x86-64: optimize certain commutative VEX-encoded insns") I missed the fact that there being subtraction involved here doesn't matter, as absolute differences get summed up.
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich4-924/+645
This way not only the overall (source) table size shrinks by quite a bit and the risk of related templates going out of sync with one another gets lowered, but also (dis)similarities between neighboring templates become easier to spot. Note that for certain SSE2AVX templates this results in benign attribute changes: - LDMXCSR and STMXCSR: NoAVX gets set, - MOVMSKPS, PMOVMSKB, PEXTR{B,W} (register destination), and PINSR{B,W} (register source): IgnoreSize and NoRex64 get set, - CVT{DQ,PS}2PD, CVTSD2SS, MOVMSKPD, MOVDDUP, PMOV{S,Z}X{BW,WD,DQ}, and ROUNDSD: NoRex64 gets set, - CVTSS2SD, INSERTPS, PEXTRW (memory destination), PINSRW (memory source), and PMOV{S,Z}X{BD,WQ,BQ}: IgnoreSize gets set. Similarly the "normal" (non-SSE2AVX) - non-64-bit CVTS{I,S}2SD forms get NoRex64 set, - CMP{EQ,ORD,NEQ,UNORD}{P,S}{S,D} forms get C set, all again in a benign way. The remaining differences in the generated table are due to re-ordering of entries in the course of being folded into templates.
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich3-375/+383
The table entries are more natural to read (and slightly shorter) when the prefixes, like is the case for VEX/XOP/EVEX-encoded entries, are specified as part of the opcode. This is particularly noticable for side-by-side legacy and SSE2AVX entries. An implication is that we now need to use "unsigned long long" for the initially parsed opcode in i386-gen. I don't expect this to be an issue.
2021-03-29x86: shrink some struct insn_template fieldsJan Beulich2-4/+10
Now that all base opcodes are only at most 2 bytes in size, shrink its template field to just as much. By also shrinking extension_opcode and operands to just what they really need, we can free up an entire 32-bit slot (plus 4 left bits past the bitfields themselves). At present this alters sizeof(struct insn_template) only for 32-bit builds. In 64-bit builds it instead leaves a padding hole that will allow to buffer future growth of other fields (opcode_modifier, cpu_flags, operand_types[]).
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich3-1601/+1641
Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-29TRUE/FALSE simplificationAlan Modra5-54/+68
There is really no need to write code like "foo != 0 ? TRUE : FALSE" unless we had stupidly defined FALSE as something other than 0 or TRUE as something other than 1. The simpler "foo != 0" does just as well. Similarly "(condition == TRUE)" or "(condition == FALSE) can be simplified to "(condition)" and "(!condition)" respectively. I'll note that there is reason to use "integer_expression != 0" when assigning a bfd_boolean rather than the simpler "integer_expression", if you expect the variable to have 0 or 1 value. It's probably even a good idea to not rely on implicit conversion if bfd_boolean were _Bool. bfd/ * aoutx.h (aout_link_write_symbols): Don't cast boolean expression to bfd_boolean. * elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans against FALSE. * elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE. (is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE". (is_reloc_SDA_relative, is_reloc_for_GOT): Likewise. (is_reloc_for_PLT, is_reloc_for_TLS): Likewise. * elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise. * elf32-nds32.c (insert_nds32_elf_blank): Likewise. * elf32-rx.c (rx_set_section_contents): Likewise. * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise. * mach-o.c (bfd_mach_o_read_command): Likewise. * targets.c (bfd_get_target_info): Likewise. binutils/ * dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE". * dwarf.c (read_and_display_attr_value): Likewise. (display_debug_str_offsets): Likewise. * objdump.c (dump_bfd): Likewise. * readelf.c (dump_section_as_strings): Likewise. (dump_section_as_bytes): Likewise. gas/ * atof-generic.c (FALSE, TRUE): Don't define. * config/obj-elf.h (FALSE, TRUE): Don't define. * config/obj-som.h (FALSE, TRUE): Don't define. * config/tc-hppa.h (FALSE, TRUE): Don't define. * config/tc-pdp11.c (FALSE, TRUE): Don't define. * config/tc-iq2000.h (obj_fix_adjustable): Delete. * config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-mt.h (obj_fix_adjustable): Delete. * config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-arc.c (parse_opcode_flags): Simplify boolean expression. (relaxable_flag, relaxable_operand, assemble_insn): Likewise. (tokenize_extregister): Likewise. * config/tc-csky.c (parse_opcode, get_operand_value): Likewise. (parse_operands_op, parse_operands, md_assemble): Likewise. * config/tc-d10v.c (build_insn): Likewise. * config/tc-score.c (s3_gen_insn_frag): Likewise. * config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise. * config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise. * config/tc-z80.c (emit_byte): Likewise. include/ * opcode/aarch64.h (alias_opcode_p): Simplify boolean expression. (opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise. (opcode_has_special_coder): Likewise. ld/ * emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify boolean expression. * lexsup.c (parse_args): Likewise. * pe-dll.c (pe_dll_id_target): Likewise. opcodes/ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. (fp_qualifier_p, get_data_pattern): Likewise. (aarch64_get_operand_modifier_from_value): Likewise. (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. (operand_variant_qualifier_p): Likewise. (qualifier_value_in_range_constraint_p): Likewise. (aarch64_get_qualifier_esize): Likewise. (aarch64_get_qualifier_nelem): Likewise. (aarch64_get_qualifier_standard_value): Likewise. (get_lower_bound, get_upper_bound): Likewise. (aarch64_find_best_match, match_operands_qualifier): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. (operand_need_sign_extension, operand_need_shift_by_two): Likewise. (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. (print_insn_tic6x): Likewise.
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra3-10/+15
cpu/ * frv.opc (frv_is_branch_major, frv_is_float_major), (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn), (frv_is_media_insn, spr_valid): Correct prototypes. include/ * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype. opcodes/ * arc-dis.c (extract_operand_value): Correct NULL cast. * frv-opc.h: Regenerate.
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich3-4/+10
While all of MMX, SSE, and SSE2 are included in "generic64", they can be individually disabled. There are two MOVQ forms lacking respective attributes. While the MMX one would get refused anyway (due to MMX registers not recognized with .nommx), the assembler did happily accept the SSE2 form. Add respective CPU settings to both, paralleling what the MOVD counterparts have.
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer2-1/+6
The code was checking wrong bit for sign extension. It caused it to zero-extend instead of sign-extend the immediate value. 2021-03-25 Abid Qadeer <abidh@codesourcery.com> opcodes/ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of immediate in br.n instruction. gas/ * testsuite/gas/nios2/brn.s: New. * testsuite/gas/nios2/brn.d: New.
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich3-16/+86
For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich2-0/+12
This combination makes no sense and is documented to cause #UD.
2021-03-25x86: fix AMD Zen3 insnsJan Beulich3-4/+66
For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra2-476/+486
opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-03-24x86: derive opcode length from opcode valueJan Beulich5-7463/+7468
In the majority of cases we can easily determine the length from the encoding, irrespective of whether a prefix is specified there as well. We further don't even need to record the value in the table entries, as it's easy enough to determine it (without any guesswork, unless an insn with major opcode 00 appeared that requires a 2nd opcode byte to be specified explicitly) when installing the chosen template for further processing. Should an encoding appear which - has a major opcode byte of 66, F3, or F2, - requires a 2nd opcode byte to be specified explicitly, - doesn't have a mandatory prefix we'd need to convert all templates presently encoding a mandatory prefix this way to the Prefix_0X<nn> model to eliminate the respective guessing i386-gen does.
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich3-5027/+5028
Just like is already done for legacy encoded insns, record the mandatory prefix information in the respective opcode modifier field. Do this without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich5-34/+40
This is in preparation of opcode_length going away as a field in the templates. Identify pseudo prefixes by a base opcode of zero instead: No real prefix has an opcode of zero. This at the same time allows dropping a curious special case from i386-gen. Since most attributes are identical for all pseudo prefixes, take the opportunity and also template them.
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich3-153/+160
In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX encoding templates, renumber the pseudo-enumerators such that their values can then also be used directly in the respective prefix bit fields.
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich4-12106/+12112
To facilitate a subsequent table parser change, re-order CPU flags and opcode modifier fields. No functional change intended.
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich5-9314/+9341
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") used the opcodeprefix field for two distinct purposes. In preparation of having VEX/XOP/EVEX and non-VEX templates become similar in the representatioon of both encoding space and opcode prefixes, split the field to have a separate one holding an insn's opcode space.
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska11-68/+86
bfd/ChangeLog: * bfd-in.h (startswith): Add startswith function. (CONST_STRNEQ): Remove. * bfd-in2.h (startswith): Regenerate with make headers. * archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith. (_bfd_slurp_extended_name_table): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * bfd.c (bfd_get_sign_extend_vma): Likewise. (bfd_convert_section_size): Likewise. (bfd_convert_section_contents): Likewise. * coff-stgo32.c (go32exe_create_stub): Likewise. (go32exe_check_format): Likewise. * coffcode.h (styp_to_sec_flags): Likewise. (GNU_DEBUGALTLINK): Likewise. * coffgen.c (_bfd_coff_section_already_linked): Likewise. (coff_gc_sweep): Likewise. (bfd_coff_gc_sections): Likewise. * cofflink.c (coff_link_add_symbols): Likewise. (process_embedded_commands): Likewise. * compress.c (bfd_is_section_compressed_with_header): Likewise. (bfd_init_section_decompress_status): Likewise. * dwarf2.c (find_debug_info): Likewise. (place_sections): Likewise. * ecoff.c (_bfd_ecoff_slurp_armap): Likewise. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. (assign_section_numbers): Likewise. (elfcore_grok_win32pstatus): Likewise. * elf32-arm.c (cmse_scan): Likewise. (elf32_arm_gc_mark_extra_sections): Likewise. (elf32_arm_size_dynamic_sections): Likewise. (is_arm_elf_unwind_section_name): Likewise. * elf32-bfin.c (bfin_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-csky.c (csky_elf_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise. (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. (xtensa_is_insntable_section): Likewise. (xtensa_is_littable_section): Likewise. (xtensa_is_proptable_section): Likewise. (xtensa_property_section_name): Likewise. (xtensa_callback_required_dependence): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ia64-vms.c (is_unwind_section_name): Likewise. (get_reloc_section): Likewise. (elf64_ia64_size_dynamic_sections): Likewise. (elf64_ia64_object_p): Likewise. * elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elflink.c (elf_link_add_object_symbols): Likewise. (_bfd_elf_gc_mark_extra_sections): Likewise. (bfd_elf_parse_eh_frame_entries): Likewise. (_bfd_elf_section_already_linked): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (is_unwind_section_name): Likewise. (elfNN_ia64_size_dynamic_sections): Likewise. (elfNN_ia64_object_p): Likewise. * elfxx-mips.c (FN_STUB_P): Likewise. (CALL_STUB_P): Likewise. (CALL_FP_STUB_P): Likewise. (_bfd_mips_elf_section_from_shdr): Likewise. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_link): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-x86.c (elf_i386_is_reloc_section): Likewise. (elf_x86_64_is_reloc_section): Likewise. * hpux-core.c (thread_section_p): Likewise. * libcoff.h (bfd_pei_p): Likewise. * linker.c (REAL): Likewise. (unwrap_hash_lookup): Likewise. (_bfd_generic_link_add_one_symbol): Likewise. * mmo.c (mmo_internal_write_section): Likewise. * osf-core.c (osf_core_core_file_p): Likewise. * pef.c (bfd_pef_print_symbol): Likewise. * pei-x86_64.c (pex64_print_all_pdata_sections): Likewise. * som.c (som_slurp_symbol_table): Likewise. (som_slurp_armap): Likewise. * wasm-module.c (wasm_compute_custom_section_file_position): Likewise. binutils/ChangeLog: * dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith. * emul_aix.c (ar_emul_aix_parse_arg): Likewise. * objcopy.c (is_mergeable_note_section): Likewise. * objdump.c (dump_dwarf_section): Likewise. * prdbg.c (pr_method_type): Likewise. (pr_class_baseclass): Likewise. (tg_class_baseclass): Likewise. * readelf.c (process_lto_symbol_tables): Likewise. * stabs.c (ULLHIGH): Likewise. (parse_stab_argtypes): Likewise. (stab_demangle_function_name): Likewise. gas/ChangeLog: * config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith. (x86_64_section_word): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. gdb/ChangeLog: * arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith. (_initialize_arm_tdep): Likewise. ld/ChangeLog: * emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith. * emultempl/beos.em: Likewise. * emultempl/elf.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. * ldctor.c (ctor_prio): Likewise. * ldelf.c (ldelf_try_needed): Likewise. (ldelf_parse_ld_so_conf): Likewise. (ldelf_after_open): Likewise. (output_rel_find): Likewise. (ldelf_place_orphan): Likewise. * ldfile.c (ldfile_add_library_path): Likewise. * ldlang.c (lang_add_input_file): Likewise. * ldmain.c (get_sysroot): Likewise. (get_emulation): Likewise. (add_archive_element): Likewise. * ldwrite.c (unsplittable_name): Likewise. (clone_section): Likewise. * lexsup.c (parse_args): Likewise. * pe-dll.c (is_import): Likewise. (pe_implied_import_dll): Likewise. opcodes/ChangeLog: * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. * arc-dis.c (parse_option): Likewise. * arm-dis.c (parse_arm_disassembler_options): Likewise. * cris-dis.c (print_with_operands): Likewise. * h8300-dis.c (bfd_h8_disassemble): Likewise. * i386-dis.c (print_insn): Likewise. * ia64-gen.c (fetch_insn_class): Likewise. (parse_resource_users): Likewise. (in_iclass): Likewise. (lookup_specifier): Likewise. (insert_opcode_dependencies): Likewise. * mips-dis.c (parse_mips_ase_option): Likewise. (parse_mips_dis_option): Likewise. * s390-dis.c (disassemble_init_s390): Likewise. * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2-4/+53
bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB*. * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus2-0/+15
This patch adds few missing system registers to GAS: LORC_EL1, LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2. gas/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. * testsuite/gas/aarch64/sysreg-7.d: New test. * testsuite/gas/aarch64/sysreg-7.s: New test. opcodes/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra2-1/+5
* i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich2-35/+35
Instead of excluding an increasing number of modes in the initial if(), check the special modes first.
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich2-4/+10
vex.b can only be set when vex.evex is also set. Similarly vex.evex can only be set when need_vex is also set.
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich2-4/+6
xmmq_mode is documented to not allow for broadcast - don't include it in respective checks in OP_E_memory().
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich6-114/+42
Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich2-77/+100
Some of the enumerators have ended up misplaced under the general current ordering scheme. Move them (and their table entries) around accordingly. Add a couple of blank lines as separators when close to code being touched anyway. Also drop the odd 0F from 0FXOP (there's no "0f" involved there anywhere) infixes where the respective enum gets played with anyway.
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich6-98/+46
When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich5-22/+20
By matching VEX decode order (L before W), some EVEX entries can refer back to VEX ones instead of carrying duplicates.
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich7-439/+249
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich2-600/+427
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich2-154/+104
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich2-70/+43
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich2-48/+61
All encodings not used in this range are (reserved) NOPs. Hence their decoding should be fully consistent. For this to work the PREFIX_IGNORED logic needs slightly extending, such that the attribute will also - have an effect when used inside prefix_table[], yet without always falling back to using slot 0, - cause prefixes marked as ignored while decoding through prefix_table[] to no longer be considered decoded, when encountered in a subsequent decoding step. In adjacent code also drop meaningless PREFIX_OPCODE.
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich5-7503/+7517
RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified together, so can share an enum-like field. IsLockable can be inferred from HLE setting and hence only needs specifying when neither of them is present.
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich4-3/+10
Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-03-03x86: infer operand count of templatesJan Beulich3-3453/+3447
Having this count explicitly in the table is redundant and (even if just slightly) disturbs clarity. Infer the count from the number of operands actually found. Also convert the "no operands" indicator from "{ 0 }" to just "{}", as that (now) ends up being easier to parse.
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu3-32/+54
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu3-95/+20
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
2021-02-17read_leb128 overflow checkingAlan Modra2-6/+27
There is a tiny error left in dwarf.c:read_leb128 after Nick fixed the signed overflow problem in code I wrote. It's to do with sleb128 values that have unnecessary excess bytes. For example, -1 is represented as 0x7f, the most efficient encoding, but also as 0xff,0x7f or 0xff,0xff,0x7f and so on. None of these sequences overflow any size signed value, but read_leb128 will report an overflow given enough excess bytes. This patch fixes that problem, and since the proper test for signed values with excess bytes can easily be adapted to also test a sleb byte with just some bits that overflow the result, I changed the code to not use signed right shifts. (The C standard ISO/IEC 9899:1999 6.5.7 says signed right shifts of negative values have an implementation defined value. A long time ago I even used a C compiler for a certain microprocessor that always did unsigned right shifts. Mind you, it is very unlikely to be compiling binutils with such a compiler.) bfd/ * wasm-module.c: Guard include of limits.h. (CHAR_BIT): Provide backup define. (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. opcodes/ * wasm32-dis.c: Include limits.h. (CHAR_BIT): Provide backup define. (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. binutils/ * dwarf.c: Include limits.h. (CHAR_BIT): Provide backup define. (read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. * testsuite/binutils-all/pr26548.s, * testsuite/binutils-all/pr26548.d, * testsuite/binutils-all/pr26548e.d: New tests. * testsuite/binutils-all/readelf.exp: Run them. (readelf_test): Drop unused "xfails" parameter. Update all uses.
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich3-2/+39
CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX logic. Therefore it - has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to SSE2AVX translation and SSE checking, - should not record MMX use in the respective ELF note.
generated by cgit v1.1 at 2024-12-27 11:58:01 +0000