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path: root/opcodes/i386-tbl.h
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2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-28Support APX pushp/poppCui, Lili1-182/+198
2023-12-28Support APX Push2/Pop2Mo, Zewei1-1/+42
2023-12-28Support APX NDDkonglin11-285/+1348
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-4087/+4407
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-11373/+11637
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-3743/+3743
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-2/+2
2023-12-15x86: fold assembly dialect attributesJan Beulich1-7486/+3743
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich1-308/+276
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-2/+2
2023-11-24x86: shrink opcode sets tableJan Beulich1-2343/+295
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich1-2/+2
2023-11-09x86: rework UWRMSR operand swappingJan Beulich1-2/+2
2023-11-09x86: do away with is_evex_encoding()Jan Beulich1-575/+575
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-161/+3908
2023-10-31Support Intel USER_MSRHu, Lin11-117/+155
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-1157/+497
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-299/+198
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich1-955/+621
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-2188/+2188
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-3846/+7692
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich1-290/+290
2023-09-01x86: drop Size64 from VMOVQJan Beulich1-1/+1
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-30768/+3846
2023-08-02Revert "2.41 Release sources"Sam James1-4415/+8525
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-8525/+4415
2023-07-27Support Intel PBNDKBHu, Lin11-3923/+3938
2023-07-27Support Intel SM4Haochen Jiang1-4439/+4477
2023-07-27Support Intel SM3Haochen Jiang1-4617/+4676
2023-07-27Support Intel SHA512Haochen Jiang1-4697/+4750
2023-07-27Support Intel AVX-VNNI-INT16konglin11-3991/+7936
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich1-2/+2
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich1-15/+15
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich1-3/+3
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich1-1057/+1057
2023-05-23Support Intel FRED LKGSZhang, Jun1-3913/+3967
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-3900/+3936
2023-03-31x86: introduce .insn directiveJan Beulich1-0/+1
2023-03-20x86: VexVVVV is now merely a booleanJan Beulich1-49/+49
2023-03-20x86: re-work build_modrm_byte()'s register assignmentJan Beulich1-44/+44
2023-02-24x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich1-6613/+6613
2023-02-24x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich1-4727/+4751
2023-02-24x86: have insns acting on segment selector values allow for consistent operandsJan Beulich1-892/+954
2023-02-24x86: restrict insn templates accepting negative 8-bit immediatesJan Beulich1-96/+96
2023-02-22x86-64: LAR and LSL don't need REX.WJan Beulich1-4/+4
2023-02-22x86: optimize BT{,C,R,S} $imm,%regJan Beulich1-4/+4
2023-02-14x86: {LD,ST}TILECFG use an extension opcodeJan Beulich1-2/+2
2023-02-13PR30120: fix x87 fucomp misassembledMichael Matz1-1/+1
2023-02-10x86: drop use of VEX3SOURCESJan Beulich1-7636/+3818
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