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2024-01-15opcodes: x86: new marker for insns that implicitly update stack pointerIndu Bhagat1-52/+53
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-1/+0
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich1-1/+7
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-28Support APX pushp/poppCui, Lili1-0/+3
2023-12-28Support APX Push2/Pop2Mo, Zewei1-0/+9
2023-12-28Support APX NDDkonglin11-0/+75
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-25/+65
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-13/+14
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-22/+19
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-2/+2
2023-12-15x86: fold assembly dialect attributesJan Beulich1-0/+4
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich1-20/+16
2023-12-14Remove redundant Byte, Word, Dword and Qword from insn templates.Cui, Lili1-123/+123
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-2/+2
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich1-0/+6
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich1-1/+1
2023-11-09x86: rework UWRMSR operand swappingJan Beulich1-1/+3
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-289/+289
2023-11-09x86: Cpu64 handling improvementsJan Beulich1-37/+39
2023-10-31Support Intel USER_MSRHu, Lin11-0/+11
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-26/+15
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-28/+9
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich1-73/+41
2023-09-14x86: Vxy naming correctionJan Beulich1-5/+5
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-19/+22
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich1-12/+14
2023-09-01x86: rename CpuPCLMULJan Beulich1-12/+12
2023-09-01x86: drop Size64 from VMOVQJan Beulich1-1/+1
2023-08-02Revert "2.41 Release sources"Sam James1-9/+48
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-48/+9
2023-07-27Support Intel PBNDKBHu, Lin11-0/+6
2023-07-27Support Intel SM4Haochen Jiang1-0/+7
2023-07-27Support Intel SM3Haochen Jiang1-0/+7
2023-07-27Support Intel SHA512Haochen Jiang1-0/+8
2023-07-27Support Intel AVX-VNNI-INT16konglin11-0/+11
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich1-1/+1
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich1-6/+6
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich1-2/+2
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich1-569/+568
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+14
2023-05-23Revert "Support Intel FRED LKGS"liuhongt1-14/+0
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+14
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-0/+3
2023-03-20x86: drop "shimm" special case template expansionsJan Beulich1-15/+15
2023-03-20x86: VexVVVV is now merely a booleanJan Beulich1-194/+196
2023-03-20x86: re-work build_modrm_byte()'s register assignmentJan Beulich1-13/+13
2023-02-24x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich1-5/+5
2023-02-24x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich1-2/+4
2023-02-24x86: have insns acting on segment selector values allow for consistent operandsJan Beulich1-5/+10
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