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path: root/opcodes/i386-gen.c
AgeCommit message (Expand)AuthorFilesLines
2022-09-30x86/Intel: restrict suffix derivationJan Beulich1-2/+0
2022-08-16x86: template-ize certain vector conversion insnsJan Beulich1-4/+26
2022-08-16x86: template-ize packed/scalar vector floating point insnsJan Beulich1-19/+24
2022-08-16revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich1-8/+27
2022-07-18x86: re-order insn template fieldsJan Beulich1-2/+2
2022-07-04x86: fold Disp32S and Disp32Jan Beulich1-14/+8
2022-07-04x86: restore masking of displacement kindsJan Beulich1-6/+6
2022-03-17x86: never set i386_cpu_flags' "unused" fieldJan Beulich1-4/+5
2022-03-17x86: unify CPU flag on/off processingJan Beulich1-21/+10
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich1-7/+1
2022-03-17x86: assorted IAMCU CPU checking fixesJan Beulich1-1/+1
2022-01-06x86: drop NoAVX insn attributeJan Beulich1-1/+0
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-2/+8
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-1/+1
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich1-6/+10
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-5/+35
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-17/+15
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-53/+41
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-2/+1
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-4/+4
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-0/+1
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-4/+1
2021-03-03x86: infer operand count of templatesJan Beulich1-34/+21
2021-02-16x86: have preprocessor expand macrosJan Beulich1-11/+0
2021-01-26Segmentation fault i386-genAlan Modra1-0/+2
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+11
2020-10-16Enhancement for avx-vnni patchCui,Lili1-2/+2
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+6
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+7
2020-10-14x86: Support Intel UINTRLili Cui1-0/+5
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-3/+52
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-1/+1
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+5
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+10
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+18
2020-07-02x86: Add SwapSourcesH.J. Lu1-0/+1
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-0/+5
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+5
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-0/+4
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-46/+267
2020-03-06x86: drop Rex64 attributeJan Beulich1-1/+0
2020-03-04x86: support VMGEXITJan Beulich1-0/+3
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-2/+1
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-7/+9
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu1-1/+1
2020-02-17Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra1-2/+2
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-2/+2
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