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path: root/opcodes/i386-gen.c
AgeCommit message (Expand)AuthorFilesLines
2025-01-17x86: Add CpuGMISM2 and CpuGMICCSMayShao-oc1-1/+2
2025-01-17x86/APX: convert runtime special case to build-time oneJan Beulich1-0/+14
2025-01-16x86: Support x86 Zhaoxin PadLock PHE2 instructionsMayShao-oc1-0/+3
2025-01-14Support Intel AMX-AVX512Haochen Jiang1-0/+3
2025-01-14Support Intel AMX-MOVRSHu, Lin11-0/+3
2025-01-14Support Intel MOVRSHu, Lin11-0/+1
2025-01-10x86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc1-0/+3
2025-01-08Support Intel AMX-FP8Liwei Xu1-0/+3
2025-01-02Support Intel AMX-TF32Haochen Jiang1-0/+3
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang1-0/+3
2025-01-01Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2024-12-02x86: default to not accepting MPX insnsJan Beulich1-1/+1
2024-11-19Support x86 Intel MSR_IMMHu, Lin11-0/+3
2024-11-18x86: rename SPACE_{,E}VEX_MAP<N>Jan Beulich1-4/+4
2024-11-18opcodes: fix -std=gnu23 compatibility wrt static_assertSam James1-0/+2
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc1-0/+1
2024-10-14x86: also template-expand trailing mnemonic partJan Beulich1-60/+72
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang1-0/+3
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-1/+0
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-0/+1
2024-05-22Support APX zero-upperCui, Lili1-0/+1
2024-05-03x86: zap value-less Disp8MemShift from non-EVEX templatesJan Beulich1-7/+19
2024-03-28x86: templatize INC/DECJan Beulich1-6/+18
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-0/+1
2024-01-05Add AMD znver5 processor supportTejas Joshi1-0/+2
2024-01-05x86: corrections to CPU attribute/flags splittingJan Beulich1-1/+10
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-0/+2
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-2/+48
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-1/+0
2023-12-15x86: fold assembly dialect attributesJan Beulich1-3/+1
2023-11-24x86: shrink opcode sets tableJan Beulich1-4/+7
2023-11-09x86: do away with is_evex_encoding()Jan Beulich1-0/+10
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-23/+51
2023-11-09x86: Cpu64 handling improvementsJan Beulich1-5/+41
2023-11-09x86: Intel Core processors do not support CMPXCHG16BJan Beulich1-1/+1
2023-10-31Support Intel USER_MSRHu, Lin11-0/+2
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-6/+8
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-0/+1
2023-09-14x86: support AVX10.1/512Jan Beulich1-0/+3
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich1-5/+12
2023-09-01x86: rename CpuPCLMULJan Beulich1-5/+5
2023-08-26opcodes i386 and ia64 gen file warningsAlan Modra1-1/+1
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-6/+36
2023-08-02Revert "2.41 Release sources"Sam James1-0/+13
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-13/+0
2023-07-27Support Intel PBNDKBHu, Lin11-0/+1
2023-07-27Support Intel SM4Haochen Jiang1-0/+3
2023-07-27Support Intel SM3Haochen Jiang1-0/+3
2023-07-27Support Intel SHA512Haochen Jiang1-0/+3
generated by cgit v1.1 at 2025-02-05 09:19:42 +0000