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path: root/opcodes/aarch64-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-1/+3
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina1-26/+26
2018-07-06Fix SBO bit in disassembly mask for ldrah on AArch64.Tamar Christina1-1/+1
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-22/+24
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-1/+1
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu1-2/+16
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina1-2/+2
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-3/+3
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina1-2/+2
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+26
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-0/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-2/+2
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-2/+2
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-4/+6
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina1-1/+60
2017-11-09Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina1-0/+90
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-2/+10
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+27
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-17/+28
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+24
2017-04-21Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L...Nick Clifton1-8/+8
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-96/+230
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-6/+8
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-3/+8
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-6/+6
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+30
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-0/+3
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-0/+10
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+11
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-0/+12
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+3
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-0/+18
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-0/+18
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang1-4/+4
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+1269
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+39
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+18
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-1/+88
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+2
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+4
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-1/+37
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-16/+16
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-1/+1
2016-08-23[AArch64] Add V8_2_INSN macroRichard Sandiford1-2/+4
2016-08-23[AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford1-67/+67
2016-08-23[AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford1-722/+722
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