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AgeCommit message (Expand)AuthorFilesLines
2021-03-03x86: infer operand count of templatesJan Beulich1-0/+7
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-0/+15
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-0/+7
2021-02-17read_leb128 overflow checkingAlan Modra1-0/+7
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich1-0/+5
2021-02-16x86: have preprocessor expand macrosJan Beulich1-0/+6
2021-02-15IBM Z: Implement instruction set extensionsAndreas Krebbel1-0/+5
2021-02-10bfd, opcodes, libctf: support --with-included-gettextNick Alcock1-0/+6
2021-02-08opcodes: tic54x: namespace exported variablesMike Frysinger1-0/+18
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu1-0/+6
2021-01-26Segmentation fault i386-genAlan Modra1-0/+5
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu1-0/+7
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-0/+4
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-0/+5
2021-01-13Regen Makefile.in for jobserver.m4 aclocal.m4 dependencyAlan Modra1-0/+4
2021-01-12Implement a workaround for GNU mak jobserverH.J. Lu1-0/+7
2021-01-12Updated translations for some subdirectoriesNick Clifton1-0/+4
2021-01-11Binutils: Check if AR works with --plugin and rcH.J. Lu1-0/+5
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-0/+12
2021-01-11Updated translations for multiple subdirectoriesNick Clifton1-0/+8
2021-01-09Binutils: Pass --plugin to AR and RANLIBH.J. Lu1-0/+4
2021-01-09Change version number to 2.36.50 and regenerate filesNick Clifton1-0/+5
2021-01-09Add Changelog entries and NEWS entries for 2.36 branchNick Clifton1-0/+4
2021-01-09POWER10: Add Return-Oriented Programming instructionsPeter Bergner1-0/+6
2021-01-09configure regenAlan Modra1-0/+4
2021-01-08Updated Swedish translation for the opcodes/ subdirectoryNick Clifton1-0/+4
2021-01-08Fix places in the AArch64 opcodes library code where a call to assert() has s...Nick Clifton1-0/+6
2021-01-08Treat the AArch64 register id_aa64mmfr2_el1 as a core system register.Nick Clifton1-0/+6
2021-01-07libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, 47a889a...Samuel Thibault1-0/+4
2021-01-07Updated French translation for the opcodes/ subdirectory.Nick Clifton1-0/+4
2021-01-07m68k: Require m68020up rather than m68000up for CHK.L instruction.Fredrik Noring1-0/+5
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich1-0/+4
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf1-0/+10
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-0/+4
2021-01-01ChangeLog rotationAlan Modra1-3269/+2
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+4
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu1-0/+11
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-0/+5
2020-12-04IBM Z: Add risbgz and risbgnz extended mnemonicsAndreas Krebbel1-0/+7
2020-12-03IBM Z: Add support for HLASM extended mnemonicsAndreas Krebbel1-0/+4
2020-12-01RISC-V: Remove the unimplemented extensions.Nelson Chu1-0/+5
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu1-0/+4
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-0/+5
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-0/+7
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-0/+7
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus1-0/+4
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson1-0/+5
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-0/+4
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+10
2020-11-06aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus1-0/+7
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