| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-04-07 | IBM zSystems: Add support for z16 as CPU name. | Andreas Krebbel | 1 | -0/+5 |
| 2022-03-16 | opcodes: handle bfd_amdgcn_arch in configure script | Simon Marchi | 1 | -0/+5 |
| 2022-03-06 | MIPS/opcodes: Fix alias annotation for branch instructions | Maciej W. Rozycki | 1 | -0/+8 |
| 2022-02-17 | Updated Serbian translations for the bfd, gold, ld and opcodes directories | Nick Clifton | 1 | -0/+4 |
| 2022-02-14 | microblaze: fix fsqrt collicion to build on glibc-2.35 | Sergei Trofimovich | 1 | -0/+5 |
| 2022-01-24 | Update Bulgarian, French, Romaniam and Ukranian translation for some of the s... | Nick Clifton | 1 | -0/+5 |
| 2022-01-22 | Change version number to 2.38.50 and regenerate files | Nick Clifton | 1 | -0/+5 |
| 2022-01-22 | Add markers for 2.38 branch | Nick Clifton | 1 | -0/+4 |
| 2022-01-17 | Update the config.guess and config.sub files from the master repository and r... | Nick Clifton | 1 | -0/+5 |
| 2022-01-02 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2021-12-02 | Allow the --visualize-jumps feature to work with the AVR disassembler. | Marcus Nilsson | 1 | -0/+5 |
| 2021-11-26 | opcodes/riscv: add disassembler options support to libopcodes | Andrew Burgess | 1 | -0/+9 |
| 2021-11-25 | Fix building the AArch64 assembler and disassembler when assertions are disab... | Nick Clifton | 1 | -0/+7 |
| 2021-11-25 | Updated French translation for the opcodes directory. | Nick Clifton | 1 | -0/+4 |
| 2021-10-27 | opcodes: Fix RPATH not being set for dynamic libbfd dependency | Maciej W. Rozycki | 1 | -0/+8 |
| 2021-09-27 | configure: regenerate in all projects that use libtool.m4 | Nick Alcock | 1 | -0/+4 |
| 2021-09-25 | PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5 | Peter Bergner | 1 | -0/+5 |
| 2021-09-20 | riscv: print .2byte or .4byte before an unknown instruction encoding | Andrew Burgess | 1 | -0/+6 |
| 2021-09-02 | Fix the V850 assembler's generation of relocations for the st.b instruction. | Nick Clifton | 1 | -0/+6 |
| 2021-08-17 | opcodes: Fix the auxiliary register numbers for ARC HS | Shahab Vahedi | 1 | -0/+4 |
| 2021-08-10 | Updated Serbian and Russian translations for various sub-directories | Nick Clifton | 1 | -0/+4 |
| 2021-07-27 | Correct gs264e bfd_mach in mips_arch_choices. | Chenghua Xu | 1 | -0/+4 |
| 2021-07-07 | Add changelog entries for last commit | Andreas Krebbel | 1 | -0/+4 |
| 2021-07-03 | Update version number and regenerate files | Nick Clifton | 1 | -0/+5 |
| 2021-07-03 | Add markers for 2.37 branch | Nick Clifton | 1 | -0/+4 |
| 2021-07-02 | Re: Fix minor NDS32 renaming snafu | Alan Modra | 1 | -0/+9 |
| 2021-07-01 | cgen: split GUILE setting out | Mike Frysinger | 1 | -0/+6 |
| 2021-07-01 | opcodes: constify & local meps macros | Mike Frysinger | 1 | -0/+7 |
| 2021-07-01 | opcodes: cleanup nds32 variables | Mike Frysinger | 1 | -0/+17 |
| 2021-07-01 | opcodes: constify & localize z80 opcodes | Mike Frysinger | 1 | -0/+5 |
| 2021-07-01 | opcodes: constify & scope microblaze opcodes | Mike Frysinger | 1 | -0/+12 |
| 2021-07-01 | opcodes: constify aarch64_opcode_tables | Mike Frysinger | 1 | -1/+6 |
| 2021-06-22 | opcodes: make use of __builtin_popcount when available | Andrew Burgess | 1 | -0/+5 |
| 2021-06-22 | picojava assembler and disassembler fixes | Alan Modra | 1 | -0/+5 |
| 2021-06-19 | ubsan: vax: pointer overflow | Alan Modra | 1 | -0/+4 |
| 2021-06-19 | Fix another strncpy warning | Alan Modra | 1 | -0/+5 |
| 2021-06-17 | powerpc: move cell "or rx,rx,rx" hints | Alan Modra | 1 | -0/+5 |
| 2021-06-03 | PR1202, mcore disassembler: wrong address loopt | Alan Modra | 1 | -0/+6 |
| 2021-06-02 | arc: Construct disassembler options dynamically | Shahab Vahedi | 1 | -0/+8 |
| 2021-05-29 | PowerPC table driven -Mraw disassembly | Alan Modra | 1 | -0/+15 |
| 2021-05-29 | MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions | Maciej W. Rozycki | 1 | -0/+5 |
| 2021-05-29 | MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership | Maciej W. Rozycki | 1 | -0/+10 |
| 2021-05-29 | MIPS/opcodes: Remove DMFC3 and DMTC3 instructions | Maciej W. Rozycki | 1 | -0/+5 |
| 2021-05-29 | MIPS/opcodes: Disassemble the RFE instruction | Maciej W. Rozycki | 1 | -0/+5 |
| 2021-05-29 | MIPS/opcodes: Add legacy CP1 control register names | Maciej W. Rozycki | 1 | -0/+10 |
| 2021-05-29 | MIPS/opcodes: Do not use CP0 register names for control registers | Maciej W. Rozycki | 1 | -0/+14 |
| 2021-05-29 | MIPS/opcodes: Add TX39 CP0 register names | Maciej W. Rozycki | 1 | -0/+6 |
| 2021-05-29 | MIPS/opcodes: Free up redundant `g' operand code | Maciej W. Rozycki | 1 | -0/+6 |
| 2021-05-29 | microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 | Maciej W. Rozycki | 1 | -0/+5 |
| 2021-05-27 | PowerPC: Add new xxmr and xxlnot extended mnemonics | Peter Bergner | 1 | -0/+4 |
