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Adjust x86-64 linker tests after reverting
commit 31b4d3a16f200bf04db8439a63b72bba7af4e1be
Author: Alan Modra <amodra@gmail.com>
Date: Thu Feb 3 08:57:47 2022 +1030
PR28824, relro security issues, x86 keep COMMONPAGESIZE relro
to use MAXPAGESIZE for the end of the relro segment alignment, like other
ELF targets.
* testsuite/ld-x86-64/plt-main-bnd.dd: Updated.
* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
* testsuite/ld-x86-64/pr14207.d: Likewise.
* testsuite/ld-x86-64/pr18176.d: Likewise.
* testsuite/ld-x86-64/pr20830a-now.d: Likewise.
* testsuite/ld-x86-64/pr20830a.d: Likewise.
* testsuite/ld-x86-64/pr20830b-now.d: Likewise.
* testsuite/ld-x86-64/pr20830b.d: Likewise.
* testsuite/ld-x86-64/pr21038a-now.d: Likewise.
* testsuite/ld-x86-64/pr21038a.d: Likewise.
* testsuite/ld-x86-64/pr21038b-now.d: Likewise.
* testsuite/ld-x86-64/pr21038b.d: Likewise.
* testsuite/ld-x86-64/pr21038c-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c.d: Likewise.
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This reverts commit 31b4d3a16f200bf04db8439a63b72bba7af4e1be.
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x86 treats MAXPAGESIZE as a memory optimisation parameter, actual
hardware paging is always COMMPAGESIZE of 4k. Use COMMONPAGESIZE for
the end of the relro segment alignment.
The previous patch regresses pr18176, increasing the testcase file
size from 322208 to 2099872 bytes. Fixing this on x86 will require
introducing a gap after the end of the relro segment (of up to
relropagesize-1 bytes).
PR 28824
PR 18176
* ld.h (ld_config_type): Add relro_use_commonpagesize field.
* ldexp.c (fold_segment_align): Set relropagesize depending on
relro_use_commonpagesize.
* emultempl/elf-x86.em (elf_x86_create_output_section_statements):
Set relro_use_commonpagesize.
* testsuite/ld-x86-64/pr18176.d: xfail.
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This reverts commit 2f83249c13d86065b4c7cdb198ea871017b4bba1.
PR ld/28743
* ldlang.c (lang_size_relro_segment_1): Revert 2022-01-10 changes.
* testsuite/ld-i386/pr20830.d: Likewise.
* testsuite/ld-s390/gotreloc_64-relro-1.dd: Likewise.
* testsuite/ld-x86-64/pr14207.d: Likewise.
* testsuite/ld-x86-64/pr18176.d: Likewise.
* testsuite/ld-x86-64/pr20830a-now.d: Likewise.
* testsuite/ld-x86-64/pr20830a.d: Likewise.
* testsuite/ld-x86-64/pr20830b-now.d: Likewise.
* testsuite/ld-x86-64/pr20830b.d: Likewise.
* testsuite/ld-x86-64/pr21038a-now.d: Likewise.
* testsuite/ld-x86-64/pr21038a.d: Likewise.
* testsuite/ld-x86-64/pr21038b-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c.d: Likewise.
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The existing RELRO scheme may leave a 1-page gap before the RELRO segment
and align the end of the RELRO segment to the page size:
[18] .eh_frame PROGBITS 408fa0 008fa0 005e80 00 A 0 0 8
[19] .init_array INIT_ARRAY 410de0 00fde0 000008 08 WA 0 0 8
[20] .fini_array FINI_ARRAY 410de8 00fde8 000008 08 WA 0 0 8
[21] .dynamic DYNAMIC 410df0 00fdf0 000200 10 WA 7 0 8
[22] .got PROGBITS 410ff0 00fff0 000010 08 WA 0 0 8
[23] .got.plt PROGBITS 411000 010000 000048 08 WA 0 0 8
Instead, we can remove the 1-page gap if the maximum page size >= the
maximum section alignment:
[18] .eh_frame PROGBITS 408fa0 008fa0 005e80 00 A 0 0 8
[19] .init_array INIT_ARRAY 40fde0 00fde0 000008 08 WA 0 0 8
[20] .fini_array FINI_ARRAY 40fde8 00fde8 000008 08 WA 0 0 8
[21] .dynamic DYNAMIC 40fdf0 00fdf0 000200 10 WA 7 0 8
[22] .got PROGBITS 40fff0 00fff0 000010 08 WA 0 0 8
[23] .got.plt PROGBITS 410000 010000 000048 08 WA 0 0 8
Because the end of the RELRO segment is always aligned to the page size
and may not be moved, the RELRO segment size may be increased:
[ 3] .dynstr STRTAB 000148 000148 000001 00 A 0 0 1
[ 4] .eh_frame PROGBITS 000150 000150 000000 00 A 0 0 8
[ 5] .init_array INIT_ARRAY 200150 000150 000010 08 WA 0 0 1
[ 6] .fini_array FINI_ARRAY 200160 000160 000010 08 WA 0 0 1
[ 7] .jcr PROGBITS 200170 000170 000008 00 WA 0 0 1
[ 8] .data.rel.ro PROGBITS 200180 000180 000020 00 WA 0 0 16
[ 9] .dynamic DYNAMIC 2001a0 0001a0 0001c0 10 WA 3 0 8
[10] .got PROGBITS 200360 000360 0002a8 00 WA 0 0 8
[11] .bss NOBITS 201000 000608 000840 00 WA 0 0 1
vs the old section layout:
[ 3] .dynstr STRTAB 000148 000148 000001 00 A 0 0 1
[ 4] .eh_frame PROGBITS 000150 000150 000000 00 A 0 0 8
[ 5] .init_array INIT_ARRAY 200b48 000b48 000010 08 WA 0 0 1
[ 6] .fini_array FINI_ARRAY 200b58 000b58 000010 08 WA 0 0 1
[ 7] .jcr PROGBITS 200b68 000b68 000008 00 WA 0 0 1
[ 8] .data.rel.ro PROGBITS 200b70 000b70 000020 00 WA 0 0 16
[ 9] .dynamic DYNAMIC 200b90 000b90 0001c0 10 WA 3 0 8
[10] .got PROGBITS 200d50 000d50 0002a8 00 WA 0 0 8
[11] .bss NOBITS 201000 000ff8 000840 00 WA 0 0 1
But there is no 1-page gap.
PR ld/28743
* ldlang.c (lang_size_relro_segment_1): Remove the 1-page gap
before the RELRO segment if the maximum page size >= the maximum
section alignment.
* testsuite/ld-i386/pr20830.d: Adjusted.
* testsuite/ld-s390/gotreloc_64-relro-1.dd: Likewise.
* testsuite/ld-x86-64/pr14207.d: Likewise.
* testsuite/ld-x86-64/pr18176.d: Likewise.
* testsuite/ld-x86-64/pr20830a-now.d: Likewise.
* testsuite/ld-x86-64/pr20830a.d: Likewise.
* testsuite/ld-x86-64/pr20830b-now.d: Likewise.
* testsuite/ld-x86-64/pr20830b.d: Likewise.
* testsuite/ld-x86-64/pr21038a-now.d: Likewise.
* testsuite/ld-x86-64/pr21038a.d: Likewise.
* testsuite/ld-x86-64/pr21038b-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c-now.d: Likewise.
* testsuite/ld-x86-64/pr21038c.d: Likewise.
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Allow eabling and disabling DT_RELR in linker tests. Disable DT_RELR in
linker tests which don't expect DT_RELR in linker outputs.
binutils/
* testsuite/lib/binutils-common.exp (run_dump_test): Make
DT_RELR_LDFLAGS and NO_DT_RELR_LDFLAGS global.
ld/
* testsuite/config/default.exp (DT_RELR_LDFLAGS): New.
(DT_RELR_CC_LDFLAGS): Likewise.
(NO_DT_RELR_LDFLAGS): Likewise.
(NO_DT_RELR_CC_LDFLAGS): Likewise.
* testsuite/ld-elf/shared.exp: Pass $NO_DT_RELR_LDFLAGS to
linker for some tests.
* testsuite/ld-i386/export-class.exp: Likewise.
* testsuite/ld-i386/i386.exp: Likewise.
* testsuite/ld-i386/ibt-plt-2a.d: Pass $NO_DT_RELR_LDFLAGS to
linker.
* testsuite/ld-i386/ibt-plt-3a.d: Likewise.
* testsuite/ld-i386/ibt-plt-3c.d: Likewise.
* testsuite/ld-i386/pr26869.d: Likewise.
* testsuite/ld-i386/report-reloc-1.d: Likewise.
* testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise.
* testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise.
* testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise.
* testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise.
* testsuite/ld-ifunc/pr17154-x86-64.d: Likewise.
* testsuite/ld-x86-64/bnd-branch-1-now.d: Likewise.
* testsuite/ld-x86-64/bnd-ifunc-1-now.d: Likewise.
* testsuite/ld-x86-64/bnd-ifunc-2-now.d: Likewise.
* testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise.
* testsuite/ld-x86-64/bnd-plt-1-now.d: Likewise.
* testsuite/ld-x86-64/bnd-plt-1.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2a.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3a.d: Likewise.
* testsuite/ld-x86-64/ilp32-4.d: Likewise.
* testsuite/ld-x86-64/load1c.d: Likewise.
* testsuite/ld-x86-64/load1d.d: Likewise.
* testsuite/ld-x86-64/pr13082-2b.d: Likewise.
* testsuite/ld-x86-64/pr14207.d: Likewise.
* testsuite/ld-x86-64/pr18176.d: Likewise.
* testsuite/ld-x86-64/pr19162.d: Likewise.
* testsuite/ld-x86-64/pr19636-2d.d: Likewise.
* testsuite/ld-x86-64/pr19636-2l.d: Likewise.
* testsuite/ld-x86-64/pr20253-1d.d: Likewise.
* testsuite/ld-x86-64/pr20253-1f.d: Likewise.
* testsuite/ld-x86-64/pr20253-1j.d: Likewise.
* testsuite/ld-x86-64/pr20253-1l.d: Likewise.
* testsuite/ld-x86-64/report-reloc-1-x32.d: Likewise.
* testsuite/ld-x86-64/report-reloc-1.d: Likewise.
* testsuite/ld-x86-64/export-class.exp (x86_64_export_class_test):
Pass $NO_DT_RELR_LDFLAGS to linker.
* testsuite/ld-x86-64/x86-64.exp: Pass $NO_DT_RELR_LDFLAGS to
linker for some tests.
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The linker tries to put the end of the last section in the relro
segment exactly on a page boundary, because the relro segment itself
must end on a page boundary. If for any reason this can't be done,
padding is inserted. Since the end of the relro segment is typically
between .got and .got.plt, padding effectively increases the size of
the GOT. This isn't nice for targets and code models with limited GOT
addressing.
The problem with the current code is that it doesn't cope very well
with aligned sections in the relro segment. When making .got aligned
to a 256 byte boundary for PowerPC64, I found that often the initial
alignment attempt failed and the fallback attempt to be less than
adequate. This is a particular problem for PowerPC64 since the
distance between .got and .plt affects the size of plt call stubs,
leading to "stubs don't match calculated size" errors.
So this rewrite takes a direct approach to calculating a new relro
base. Starting from the last section in the segment, we calculate
where it must start to position its end on the boundary, or as near as
possible considering alignment requirements. The new start then
becomes the goal for the previous section to end, and so on for all
sections. This of course ignores the possibility that user scripts
will place . = ALIGN(xxx); in the relro segment, or provide section
address expressions. In those cases we might fail, but the old code
probably did too, and a fallback is provided.
ld/
* ldexp.h (struct ldexp_control): Delete dataseg.min_base. Add
data_seg.relro_offset.
* ldexp.c (fold_binary <DATA_SEGMENT_ALIGN>): Don't set min_base.
(fold_binary <DATA_SEGMENT_RELRO_END>): Do set relro_offset.
* ldlang.c (lang_size_sections): Rewrite code adjusting relro
segment base to line up last section on page boundary.
ld/testsuite/
* ld-x86-64/pr18176.d: Update.
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PR ld/18176
* ld-x86-64/pr18176.d: New file.
* ld-x86-64/pr18176.s: Likewise.
* ld-x86-64/pr18176.t: Likewise.
* ld-x86-64/x86-64.exp: Run pr18176.
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