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2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo1-0/+2
This patch add support for FEAT_ITE "Instrumentation Extension" adding the "trcit" instruction. This is enabled by the +ite march flag.
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo1-1/+4
This patch add supports for FEAT_SPECRES2 "Enhanced speculation restriction instructions" adding the "cosp" instruction. This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+. It is enabled by the +predres2 march flag.
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma1-4/+4
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the XTheadFmv extension in T-Head specific is incorrect, and it also has some impact on the implementation of the binutils, so this patch corrects this. For details see: https://github.com/T-head-Semi/thead-extension-spec/pull/34 gas/ChangeLog: * testsuite/gas/riscv/x-thead-fmv.d: Correct test. * testsuite/gas/riscv/x-thead-fmv.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding. (MASK_TH_FMV_HW_X): Likewise. (MATCH_TH_FMV_X_HW): Likewise. (MASK_TH_FMV_X_HW): Likewise. opcodes/ChangeLog: * riscv-opc.c: Correct operands.
2023-12-04s390: Support for jump visualization in disassemblyJens Remus1-3/+22
Add support for jump visualization for the s390 architecture in disassembly: objdump -d --visualize-jumps ... Annotate the (conditional) jump and branch relative instructions with information required for jump visualization: - jump: Unconditional jump / branch relative. - condjump: Conditional jump / branch relative. - jumpsr: Jump / branch relative to subroutine. Unconditional jump and branch relative instructions are annotated as jump. Conditional jump and branch relative instructions, jump / branch relative on count/index, and compare and jump / branch relative instructions are annotated as condjump. Jump and save (jas, jasl) and branch relative and save (bras, brasl) instructions are annotated as jumpsr (jump to subroutine). Provide instruction information required for jump visualization during disassembly. The instruction type is provided after determining the opcode. For non-code it is set to dis_noninsn. Otherwise it defaults to dis_nonbranch. No annotation is done for data reference instructions (i.e. instruction types dis_dref and dis_dref2). Note that the instruction type needs to be provided before printing of the instruction, as it is used in print_address_func() to translate the argument value into an address if it is assumed to be a PC-relative offset. Note that this is never the case on s390, as print_address_func() is only called with addresses and never with offsets. The target of the (conditional) jump and branch relative instructions is provided during print, when the PC relative operand is decoded. include/ * opcode/s390.h: Define opcode flags to annotate instruction class information for jump visualization: S390_INSTR_FLAG_CLASS_BRANCH, S390_INSTR_FLAG_CLASS_RELATIVE, S390_INSTR_FLAG_CLASS_CONDITIONAL, and S390_INSTR_FLAG_CLASS_SUBROUTINE. Define opcode flags mask S390_INSTR_FLAG_CLASS_MASK for above instruction class information. Define helpers for common instruction class flag combinations: S390_INSTR_FLAGS_CLASS_JUMP, S390_INSTR_FLAGS_CLASS_CONDJUMP, and S390_INSTR_FLAGS_CLASS_JUMPSR. opcodes/ * s390-mkopc.c: Add opcode flags to annotate information for jump visualization: jump, condjump, and jumpsr. * s390-opc.txt: Annotate (conditional) jump and branch relative instructions with information for jump visualization. * s390-dis.c (print_insn_s390, s390_print_insn_with_opcode): Provide instruction information for jump visualization. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2-0/+64
SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu <hau.hsu@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner2-2/+3
Back then when the support for the RISC-V vector crypto extensions was merged, the specification was frozen, but not ratified. A frozen specification is allowed to change within tight bounds before ratification and this has happend with the vector crypto extensions. The following changes were applied: * A new extension Zvkb was defined, which is a strict subset of Zvbb. * Zvkn and Zvks include now Zvkb instead of Zvbb. This patch implements these changes between the frozen and the ratified specification. Note, that this technically an incompatible change of Zvkn and Zvks, but I am not aware of any project that depends on the currently implemented behaviour of Zvkn and Zvks. So this patch should be fine. Reported-By: Jerry Shih <jerry.shih@sifive.com> Reported-By: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-2/+1
Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold riscv_ext()'s calls md_assemblef(), the first of which were entirely identical, while the other pair differed in just a single character. Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-23RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extensionJin Ma1-0/+10
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds permutation instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for permutation instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMVXS): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add vector mask instructions for T-Head VECTOR vendor extensionJin Ma1-0/+14
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds mask instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for mask instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor ↵Jin Ma1-0/+36
extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds floating-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for floating-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor ↵Jin Ma1-0/+12
extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds fixed-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for fixed-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAADDVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma1-0/+12
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds integer arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for integer arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VADCVVM): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma2-1/+37
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvamo" for the "XTheadVector" extension, and it provides AMO instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvamo" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-zvamo.d: New test. * testsuite/gas/riscv/x-thead-vector-zvamo.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma1-0/+169
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds provides load/store segment instructions for T-Head VECTOR vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector extension, but belongs to the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add test. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma1-0/+33
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds load/store instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for load/store instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLBV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-0/+7
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the CSRs for XTheadVector. Because of the conflict between encoding and teh 'V' extension, it is implemented by alias. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add the class for the CSRs of the "XTheadVector" extension. (riscv_csr_address): Likewise. * testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test. * testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test. * testsuite/gas/riscv/x-thead-vector-csr.d: New test. * testsuite/gas/riscv/x-thead-vector-csr.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma1-0/+1
T-Head has a range of vendor-specific instructions ([2]). Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 [2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): The "XTheadVector" extension and the 'V' extension are in conflict. (riscv_multi_subset_supports): Likewise.. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-fail.d: New test. * testsuite/gas/riscv/x-thead-vector-fail.l: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class):
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni1-1/+20
This patch adds the permission model enhancement and memory attribute index enhancement features and their corresponding system registers in AArch64 assembler. Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE) Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE) Memory Attribute Index Enhancement (FEAT_AIE) Extension to Translation Control Registers (FEAT_TCR2) These features are available by default from Armv9.4-A architecture.
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-1/+4
This patch adds 3 new AT system instructions through FEAT_ATS1A feature, which are available by default from Armv9.4-A architecture.
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-1/+13
This patch also adds support for: 1. FEAT_RASv2 feature and "ERXGSR_EL1" system register. RASv2 feature is enabled by passing +rasv2 to -march (eg: -march=armv8-a+rasv2). 2. FEAT_SCTLR2 and following system registers. SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3. 3. FEAT_FGT2 and following system registers. HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2 4. FEAT_PFAR and following system registers. PFAR_EL1, PFAR_EL2 and PFAR_EL12. FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default enabled from Armv9.4-A architecture. This patch also adds support for two read only system registers id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from Armv8-A Architecture.
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni1-1/+10
This patch adds features to the Statistical Profiling Extension, identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which are enabled by default from Armv9.4-A. Also adds support for system register "pmsdsfr_el1".
2023-11-10Add support for ilp32 register alias.Lulu Cai1-4/+4
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+3
Enable the `+lse128' feature modifier which, together with new internal feature flags, enables LSE128 instructions, which are represented via the new `_LSE128_INSN' macro. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add new "lse128" entry. include/ChangeLog: * include/opcode/aarch64.h (enum aarch64_feature_bit): New AARCH64_FEATURE_LSE128 feature bit. (enum aarch64_insn_class): New lse128_atomic instruction class. opcodes/ChangeLog: * opcodes/aarch64-tbl.h (aarch64_feature_lse128): New. (LSE128): Likewise. (_LSE128_INSN): Likewise.
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento1-0/+2
Given the particular encoding of the LSE128 instructions, create the necessary shared input+output operand register description and handling in the code to allow for the encoding of the LSE128 128-bit atomic operations. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): opcodes/ChangeLog: * aarch64-opc.c (fields): (aarch64_print_operand): * aarch64-opc.h (enum aarch64_field_kind): * aarch64-tbl.h (AARCH64_OPERANDS):
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento1-0/+2
Add Binutils support for system registers associated with the Translation Hardening Extension (THE). In doing so, we also add core feature support for THE, enabling its associated feature flag and implementing the necessary feature-checking machinery. Regression tested on aarch64-linux-gnu, no regressions. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier. * doc/c-aarch64.texi (AArch64 Extensions): Update documentation for `the' option. * testsuite/gas/aarch64/sysreg-8.s: Add tests for `the' associated system registers. * testsuite/gas/aarch64/sysreg-8.d: Likewise. include/ChangeLog: * opcode/aarch64.h (enum aarch64_feature_bit): Add AARCH64_FEATURE_THE. opcode/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the' system register check support. * aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1' * aarch64-tbl.h: Define `THE' preprocessor macro.
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett2-0/+72
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett2-0/+44
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mac-fail-march.d: New test. * testsuite/gas/riscv/cv-mac-fail-march.l: New test. * testsuite/gas/riscv/cv-mac-fail-march.s: New test. * testsuite/gas/riscv/cv-mac-fail-operand.d: New test. * testsuite/gas/riscv/cv-mac-fail-operand.l: New test. * testsuite/gas/riscv/cv-mac-fail-operand.s: New test. * testsuite/gas/riscv/cv-mac-insns.d: New test. * testsuite/gas/riscv/cv-mac-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble information with the EXTRACT macro implemented. * riscv-opc.c: Defined the MASK and added XCVmac instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCVmac. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for uimm. (enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+3
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and FS{H,W,D,Q} the sole difference between the handling is the insn mnemonic passed to the common handling functions. The intended mnemonic, however, can easily be retrieved. Furthermore leverags that Sx and FSx are then handled identically, too, and hence their cases can also be folded.
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni1-0/+2
This patch adds support for Guarded control stack data synchronization instruction (GCSB DSYNC). This instruction is allocated to existing HINT space and uses the HINT number 19 and to match this an entry is added to the aarch64_hint_options array.
2023-11-02aarch64: Add support for GCS extension.srinath1-1/+3
This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is optional from Armv9.4-A architecture and enabled by passing +gcs option to -march (eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file. Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx, gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni1-2/+5
This patch adds support for Check Feature Status Extension (CHK) which is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction (hint #40).
2023-11-02aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.srinath1-1/+8
This patch adds AArch64 support for Armv8.9-A architecture (-march=armv8.9-a) and Armv9.4-A architecture (-march=armv9.4-a).
2023-10-19RISC-V: Remove semicolons from DECLARE_INSNTsukasa OI1-15/+15
This is for consistency and to prevent possible unnecessary errors due to this inconsistency. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): Remove semicolons from the end of each entry.
2023-10-17RISC-V: Fix typoTsukasa OI1-1/+1
include/ChangeLog: * opcode/riscv-opc.h: Fix typo.
2023-10-10LoongArch/GAS: Add support for branch relaxationmengqinggang1-0/+12
For the instructions of R_LARCH_B16/B21, if the immediate overflow, add a B instruction and R_LARCH_B26 relocation. For example: .L1 ... blt $t0, $t1, .L1 R_LARCH_B16 change to: .L1 ... bge $t0, $t1, .L2 b .L1 R_LARCH_B26 .L2
2023-10-08as: add option for generate R_LARCH_32/64_PCREL.cailulu1-0/+1
Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL as much as possible. The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL relocation in .eh_frame.
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento1-0/+1
This patch adds a mechanism for system register name alias detection to register-matching mechanisms. A new `F_REG_ALIAS' flag is added to the set of register flags and used to label which entries in aarch64_sys_regs[] correspond to aliases (and thus which CPENC values are non-unique in this array). Where this is used is, for example, in `aarch64_print_operand' where, in the case of system register decoding, the aarch64_sys_regs[] array is iterated through until a match in CPENC value is made and the first match accepted. If insufficient care is given in the ordering of system registers in this array, the alias is encountered before the "real" register and used incorrectly as the register name in the disassembled output. With this flag and the new `aarch64_sys_reg_alias_p' test, search candidates corresponding to aliases can be conveniently skipped over. One concrete example of where this is useful is with the `trcextinselr0' system register. It was initially placed in the system register list before `trcextinselr', in contrast to a more natural alphabetical order. include/ChangeLog: * opcode/aarch64.h: add `aarch64_sys_reg_alias_p' prototype. opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_reg_alias_p): New. (aarch64_print_operand): add aarch64_sys_reg_alias_p check. (aarch64_sys_regs): Add F_REG_ALIAS flag to "trcextinselr" entry. * aarch64-opc.h (F_REG_ALIAS): New.
2023-09-26aarch64: Allow feature flags to occupy >64 bitsRichard Sandiford1-23/+39
Following on from the previous patch to make the feature macros take a word number, this one increases the number of flag words from 1 to 2. The patch uses some dummy features to push the number of features over 64. The intention is that these should be reused by real features rather than kept as-is.
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-151/+268
The AArch64 feature-flag code is currently limited to a maximum of 64 features. This patch reworks it so that the limit can be increased more easily. The basic idea is: (1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum counting bit positions. (2) Make the feature-list macros take an array index argument (currently always 0). The macros then return the aarch64_feature_set contents for that array index. An N-element array would then be initialised as: { MACRO (0), ..., MACRO (N - 1) } (3) Provide convenience macros for initialising an aarch64_feature_set for: - a single feature - a list of individual features - an architecture version - an architecture version + a list of additional features (2) and (3) use the preprocessor to generate static initialisers. The main restriction was that uses of the same preprocessor macro cannot be nested. So if a macro wants to do something for N individual arguments, it needs to use a chain of N macros to do it. There then needs to be a way of deriving N, as a preprocessor token suitable for pasting. The easiest way of doing that was to precede each list of features by the number of features in the list. So an aarch64_feature_set initialiser for three features A, B and C would be written: AARCH64_FEATURES (3, A, B, C) This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-25Revert "arc: Update opcode related include files for ARCv3."Claudiu Zissulescu3-257/+56
This reverts commit 04414221df53bb5129e34bec354dae3121db436a.
2023-09-25arc: Update opcode related include files for ARCv3.Claudiu Zissulescu3-56/+257
Add new ARCv3 CPUs and required bits to decode/encode ARCv3 ISA opcodes. Fix 32 bit relocations which were set as signed but should be bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE. Remove non-ABI relocation ARC_32_ME_S. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cupertinomiranda@gmail.com> Bruno Mauricio <brunoasmauricio@gmail.com> * include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs. * include/elf/arc-reloc.def: Add new ARC64 relocations. * include/elf/arc.h (EF_ARC_CPU_ARC64): New define. * include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate. * include/opcode/arc-func.h: Update formating. (replace_disp8ls): New function. (replace_disp9s): Likewise. (replace_disp6s): Likewise. (replace_disp7s): Likewise. (replace_disp12s): Likewise. * include/opcode/arc.h (ARC_OPCODE_ARC64): New define. (ARC_OPCODE_ARC32): Likewise. (ARC_OPERAND_FP): Likewise. (HARD_FIELDF): Likewise. (ARC_OPCODE_ARCVx): New macro. (arc_flag_class): Update structure to hold new extract/insert functions for flags. (INSN3OP): Update macro. (FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-1/+0
There's no need to have almost identical code twice. Do away with M_VMSGEU and instead simply use an unused (for these macros) field to tell apart both variants.
2023-09-05RISC-V: Add 'Smcntrpmf' extension and its CSRsTsukasa OI1-4/+12
This commit adds now stable and approved 'Smcntrpmf' extension defined by the RISC-V Cycle and Instret Privilege Mode Filtering specification. Note that, because mcyclecfg and minstretcfg CSRs conflict with the privileged specification version 1.9.1, CSRs for this extension are only enabled on the privileged specification version 1.10 or later. By checking the base privileged specification, we no longer need to change the design of base CSR handling. This is based on the specification version v1.0_rc1 (Frozen): <https://github.com/riscv/riscv-smcntrpmf/commit/32b752c40d59c1b5e95de83399c1f54be6669163> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add implication rule from the new 'Smcntrpmf' extension. (riscv_supported_std_s_ext): Add 'Smcntrpmf' to the supported S extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add new CSR classes CSR_CLASS_SMCNTRPMF and CSR_CLASS_SMCNTRPMF_32. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now aliases. * testsuite/gas/riscv/csr-dw-regnums.d: Reflect the change. * testsuite/gas/riscv/csr.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now reused for the 'Smcntrpmf' extension. * testsuite/gas/riscv/csr-version-1p9p1.d: Reflect the changes of csr.s. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h: Add new CSRs noting that this extension is incompatible with the privileged specification version 1.9.1. Move "mscounteren" and "mhcounteren" CSRs, make them aliases and reuse the CSR numbers from the 'Smcntrpmf' extension. (CSR_MSCOUNTEREN, CSR_MHCOUNTEREN) Remove as "mscounteren" and "mhcounteren" are now aliases and new CSR macros are used instead. (CSR_MCYCLECFG, CSR_MINSTRETCFG, CSR_MCYCLECFGH, CSR_MINSTRETCFGH): New CSR macros.
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-54/+54
Historically, flags and variables relating to architectural revisions for the A-profile architecture omitted the trailing `A' such that, for example, assembling for `-march=armv8.4-a' set the `AARCH64_ARCH_V8_4' flag in the assembler. This leads to some ambiguity, since Binutils also targets the R-profile Arm architecture. Therefore, it seems prudent to have everything associated with the A-profile cores end in `A' and likewise `R' for the R-profile. Referring back to the example above, the flag set for `-march=armv8.4-a' is better characterized if labeled `AARCH64_ARCH_V8_4A'. The only exception to the rule of appending `A' to variables is found in the handling of the `AARCH64_FEATURE_V8' macro, as it is the baseline from which ALL processors derive and should therefore be left unchanged. In reflecting the `ARM' architectural nomenclature choices, where we have `ARM_ARCH_V8A' and `ARM_ARCH_V8R', the choice is made to not have an underscore separating the numerical revision number and the A/R-profile indicator suffix. This has meant that renaming of R-profile related flags and variables was warranted, thus going from `.*_[vV]8_[rR]' to `.*_[vV]8[rR]'. Finally, this is more in line with conventions within GCC and adds consistency across the toolchain. gas/ChangeLog: * gas/config/tc-aarch64.c: (aarch64_cpus): Reference to arch feature macros updated. (aarch64_archs): Likewise. include/ChangeLog: * include/opcode/aarch64.h: (AARCH64_FEATURE_V8A): Updated name: V8_A -> V8A. (AARCH64_FEATURE_V8_1A): A-suffix added. (AARCH64_FEATURE_V8_2A): Likewise. (AARCH64_FEATURE_V8_3A): Likewise. (AARCH64_FEATURE_V8_4A): Likewise. (AARCH64_FEATURE_V8_5A): Likewise. (AARCH64_FEATURE_V8_6A): Likewise. (AARCH64_FEATURE_V8_7A): Likewise. (AARCH64_FEATURE_V8_8A):Likewise. (AARCH64_FEATURE_V9A): Likewise. (AARCH64_FEATURE_V8R): Updated name: V8_R -> V8R. (AARCH64_ARCH_V8A_FEATURES): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A_FEATURES): A-suffix added. (AARCH64_ARCH_V8_2A_FEATURES): Likewise. (AARCH64_ARCH_V8_3A_FEATURES): Likewise. (AARCH64_ARCH_V8_4A_FEATURES): Likewise. (AARCH64_ARCH_V8_5A_FEATURES): Likewise. (AARCH64_ARCH_V8_6A_FEATURES): Likewise. (AARCH64_ARCH_V8_7A_FEATURES): Likewise. (AARCH64_ARCH_V8_8A_FEATURES): Likewise. (AARCH64_ARCH_V9A_FEATURES): Likewise. (AARCH64_ARCH_V9_1A_FEATURES): Likewise. (AARCH64_ARCH_V9_2A_FEATURES): Likewise. (AARCH64_ARCH_V9_3A_FEATURES): Likewise. (AARCH64_ARCH_V8A): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A): A-suffix added. (AARCH64_ARCH_V8_2A): Likewise. (AARCH64_ARCH_V8_3A): Likewise. (AARCH64_ARCH_V8_4A): Likewise. (AARCH64_ARCH_V8_5A): Likewise. (AARCH64_ARCH_V8_6A): Likewise. (AARCH64_ARCH_V8_7A): Likewise. (AARCH64_ARCH_V8_8A): Likewise. (AARCH64_ARCH_V9A): Likewise. (AARCH64_ARCH_V9_1A): Likewise. (AARCH64_ARCH_V9_2A): Likewise. (AARCH64_ARCH_V9_3A): Likewise. (AARCH64_ARCH_V8_R): Updated name: V8_R -> V8R. opcodes/ChangeLog: * opcodes/aarch64-opc.c (SR_V8A): Updated name: V8_A -> V8A. (SR_V8_1A): A-suffix added. (SR_V8_2A): Likewise. (SR_V8_3A): Likewise. (SR_V8_4A): Likewise. (SR_V8_6A): Likewise. (SR_V8_7A): Likewise. (SR_V8_8A): Likewise. (aarch64_sys_regs): Reference to arch feature macros updated. (aarch64_pstatefields): Reference to arch feature macros updated. (aarch64_sys_ins_reg_supported_p): Reference to arch feature macros updated. * opcodes/aarch64-tbl.h: (aarch64_feature_v8_2a): a-suffix added. (aarch64_feature_v8_3a): Likewise. (aarch64_feature_fp_v8_3a): Likewise. (aarch64_feature_v8_4a): Likewise. (aarch64_feature_fp_16_v8_2a): Likewise. (aarch64_feature_v8_5a): Likewise. (aarch64_feature_v8_6a): Likewise. (aarch64_feature_v8_7a): Likewise. (aarch64_feature_v8r): Updated name: v8_r-> v8r. (ARMV8R): Updated name: V8_R-> V8R. (ARMV8_2A): A-suffix added. (ARMV8_3A): Likewise. (FP_V8_3A): Likewise. (ARMV8_4A): Likewise. (FP_F16_V8_2A): Likewise. (ARMV8_5): Likewise. (ARMV8_6A): Likewise. (ARMV8_6A_SVE): Likewise. (ARMV8_7A): Likewise. (V8_2A_INSN): `A' added to macro symbol. (V8_3A_INSN): Likewise. (V8_4A_INSN): Likewise. (FP16_V8_2A_INSN): Likewise. (V8_5A_INSN): Likewise. (V8_6A_INSN): Likewise. (V8_7A_INSN): Likewise. (V8R_INSN): Updated name: V8_R-> V8R.
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-2/+2
The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header source bit, despite operating on registers. If BPF_SRC_X (=1) is set, the instructions are rejected by the kernel. Because of this there are also no neg/neg32 instructions which operate on immediates, so remove them. bd434cc4d94ec3d2f9fc1e7c00c27b074f962bc1 was a similar fix in the old CGEN-based port, but was not carried forward in the new port. include/ * opcode/bpf.h (enum bpf_insn_id): Remove spurious entries BPF_INSN_NEGI and BPF_INSN_NEG32I. opcodes/ * bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I instructions. gas/ * doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and neg32 instructions operating on immediates. * testsuite/gas/bpf/alu.s: Adapt accordingly. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-08-16kvx: New port.Paul Iannetta1-0/+3159
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-0/+1
The documentation of the 'Zfa' extension states that "fli.h" is available "if the Zfh or Zvfh extension is implemented" (both the latest and the oldest editions are checked). This fact was not reflected in Binutils ('Zvfh' implies 'Zfhmin', not full 'Zfh' extension and "fli.h" required 'Zfh' and 'Zfa' extensions). This commit makes "fli.h" also available when both 'Zfa' and 'Zvfh' extensions are implemented. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add new instruction class handling. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zfa-zvfh.s: New test. * testsuite/gas/riscv/zfa-zvfh.d: Ditto. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction class. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction class of "fli.h" from INSN_CLASS_ZFH_AND_ZFA to new INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA.
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI2-0/+28
This commit adds 'Zihintntl' extension and its hint instructions. This is based on: <https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6da7791d5a733c553e6e2506ddcab5>, the first ISA Manual noting that the 'Zihintntl' extension is ratified. Note that compressed 'Zihintntl' hints require either 'C' or 'Zca' extension. Co-authored-by: Nelson Chu <nelson@rivosinc.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl' standard hint 'Z' extension. (riscv_multi_subset_supports): Support new instruction classes. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zihintntl.s: New test for 'Zihintntl' including auto-compression without C prefix and explicit C prefix. * testsuite/gas/riscv/zihintntl.d: Likewise. * testsuite/gas/riscv/zihintntl-na.d: Likewise. * testsuite/gas/riscv/zihintntl-base.s: New test for correspondence between 'Zihintntl' and base 'I' or 'C' instructions. * testsuite/gas/riscv/zihintntl-base.d: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C. (MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL, MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL, MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL, MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL, MATCH_C_NTL_ALL): New. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add instructions from the 'Zihintntl' extension.
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-7/+9
The longest register name is 4 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also reduces the number of base relocations in the final image. To avoid old gcc, when generating 32-bit code, bogusly warning about bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD, an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply a 64-bit value, and it also doesn't need to - all operand fields to date are far more narrow than 32 bits. This in turn allows dropping a number of casts elsewhere.
2023-08-02Revert "2.41 Release sources"Sam James2-2/+52
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
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