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2024-09-11arm: don't engage symver scrubber hack in CCS modeJan Beulich3-1/+20
In that mode the comment char is ; while @ has no special meaning. Engaging the special logic in that case results in comments not being respected on .symver lines.
2024-09-11x86: error handling in set_cpu_arch()Jan Beulich1-30/+34
Error messages there would better not be followed by further "junk at end of line" diagnostics. Arrange for this to be the case uniformly. While there also replace a somewhat unhelpful open-coding of restore_line_pointer().
2024-09-09s390: Document syntax to omit base register operandJens Remus1-2/+3
Document the s390-specific assembler syntax introduced by commit aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") to omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). While at it document the alternative syntax to omit the index register operand X in D(X,B) by coding D(,B) instead of D(B). gas/ * doc/c-s390.texi (s390 Operands): Document syntax to omit base register operand. Fixes: aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-09LoongArch: Fixed precedence of expression operators in instructionsLulu Cai3-12/+23
The precedence of the operators "+" and "-" in the current loongarch instruction expression is higher than "<<" and ">>", which is different from the explanation in the user guide. We modified the precedence of "<<" and ">>" to be higher than "+" and "-".
2024-09-07Add macros to get opcode of instructions approriatelyXin Wang2-122/+122
LoongArch: Add macros to get opcode and register of instructions appropriately Currently, we get opcode of an instruction by manipulate the binary with it's mask, it's a bit of a pain. Now a macro is defined to do this and a macro to get the RD and RJ registers which is applicable to most instructions of LoongArch are added.
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich1-1/+7
There's no need to have 30 redundant templates when we can easily take care of the operand swapping like we do for various other insns.
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich3-0/+55
Along the lines of 2513312930b2 ("x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms") these can similarly be converted to the shorter legacy-encoded CMOVcc.
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett9-2/+4222
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang12-57/+2652
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-30x86: replace conditional operators used to calculate booleansJan Beulich1-10/+11
The boolean expressions themselves are fine to use there.
2024-08-30x86: limit RegRex64 useJan Beulich1-9/+7
The special property really only applies to the "extended" byte regs having legacy word/dword counterparts. While touching involved code also drop redundant byte checks from a conditional in establish_rex(): The other remaining RegRex64 uses only exist on registers which can't be used as register operands anyway. Hence RegRex64 as an attribute of a (valid) register operand implies that it's a byte reg.
2024-08-30gas: properly check for ELF in LISTING_NODEBUG handlingJan Beulich1-36/+35
While OBJ_MAYBE_ELF presently implies OBJ_ELF (due to obj-multi.h including obj-elf.h for obscure reasons), there still need to be IS_ELF checks to cover for the OBJ_MAYBE_ELF case. Note, however, that code checking for ->debugging being true doesn't need such extra checks, as the field can only ever be true when IS_ELF. On the same basis reduce #ifdef-ary in debugging_pseudo(). Also move the field (into what on 64-bit architectures is a 32-bit gap) and put it inside an OBJ_ELF conditional, too. While there further switch int to bool in related code.
2024-08-30gas: generated code/data listing output vs .endr and alikeJan Beulich3-0/+14
These ending directives are swallowed by buffer_and_nest() and hence aren't seen by read_a_source_file(). Thus they also weren't announced to the listing subsystem. That was, when macro expansions are included, thus misguided to associate possible output resulting from the first line of the construct being expanded with both the .endr and that first line (i.e. showing it twice).
2024-08-30LoongArch: LoongArch64 allows relocations to use 64-bit addendsLulu Cai3-0/+23
Relocations using 64-bit addends allow larger constant offset address calculations to be fused.
2024-08-28x86: Report invalid TLS operatorH.J. Lu3-5/+5
Report invalid TLS operator, instead of relocation. PR gas/28595 * config/tc-i386.c (gotrel): Replace int with unsigned int. (i386_assemble): Report invalid TLS operator. * testsuite/gas/i386/inval-tls.l: updated. * testsuite/gas/i386/x86-64-inval-tls.l: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27x86: Report invalid TLS relocation nameH.J. Lu3-94/+101
Get TLS relocation name from its lex_got entry when reporting invalid instructions with TLS relocations. PR gas/28595 * config/tc-i386.c (gotrel): Moved from ... (lex_got): There. (i386_assemble): Get invalid TLS relocation name from its lex_got entry when reporting TLS relocation error. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27x86: Allow R_386_TLS_LE_32 with KMOVDH.J. Lu3-4/+2
Since there is no TLS IE transition, allow R_386_TLS_LE_32 with KMOVD. gas/ PR gas/28595 * config/tc-i386.c (i386_assemble): Remove BFD_RELOC_386_TLS_LE_32 from TLS code check. * testsuite/gas/i386/inval-tls.s: Remove foo@tpoff(%eax). * testsuite/gas/i386/inval-tls.l: Updated. ld/ PR gas/28595 * testsuite/ld-i386/i386.exp: Run tlsle1. * testsuite/ld-i386/tlsle1.d: New file. * testsuite/ld-i386/tlsle1.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei4-1/+64
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
2024-08-23x86: simplify SAE checkingJan Beulich1-12/+10
To determine whether SAE (with or without StaticRounding) is permitted there's no need to iterate over all operands. Even less so starting at the front (thus needlessly inspecting immediate operands as well). Leverage the pattern across all relevant templates and check only the last two operands, and also only for non-512 ones (besides the non-LIG case that was already checked for).
2024-08-23gas: update lex_type[] also for .mri directivesJan Beulich1-0/+2
Doing this just from read_begin(), i.e. merely based on command line options, can't be sufficient (assuming it's really relevant).
2024-08-23RISC-V: process rs_align_code also when relaxingJan Beulich2-35/+29
riscv_handle_align() runs after all input was processed. Whether relaxation is enabled for any particular piece of code is not recorded anywhere. (This issue was even "worked around" in a gas testcase, which is adjusted accordingly.) Furthermore, as demonstrated by an ld testcase, tail padding in an object file's executable sections depended on whether relaxation was enabled at the end of assembly: NOPs were emitted only when relaxation was off; zeroes were emitted with relaxation enabled. (It could probably be either way, but it should be independent of relaxation state at the end of assembly. Except of course write.c, in a comment ahead of #define-ing SUB_SEGMENT_ALIGN(), explicitly says "proper nop-filling".) While re-indenting, drop the "odd_padding" variable. It's used exactly once, and having the actual expression right in the if() is imo helping readers to understand what the intentions are. While touching the ld testcase, also tighten the expectations for the addresses of the two symbols: The last two digits have to have fixed values.
2024-08-19gas: ginsn: x86: pacify Wmaybe-uininitialized compiler warningIndu Bhagat1-0/+2
Fix PR binutils/32091 After commit d56083b5047b8e7cc9eda2f867bd2b75724920a1, some gcc versions may warn about unintialized usage of ginsn_func. Albeit false positive, adapt the code to escape the warning. gas/config/ * tc-i386-ginsn.c (x86_ginsn_indirect_branch): Early exit if unexpected args.
2024-08-16gas: don't open-code LEX_*NAMEJan Beulich6-7/+8
... except in read.c's definition of lex_type[], where readbility would otherwise suffer.
2024-08-15Revert "Arm: correct macro use in gas testsuite"H.J. Lu2-2/+2
This reverts commit cfa18744d435b55bbbbc5ef1ae1df67e84aa1777. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15Revert "bfin: correct macro use in gas testsuite"H.J. Lu1-4/+4
This reverts commit a1b7023447d19d70bc36d71b7627f457dbfae5ce. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15Revert "ia64: correct macro use in gas testsuite"H.J. Lu1-6/+6
This reverts commit 2231ac9b9e88191178001d0ae5845e292acb2a56. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15Revert "MIPS: correct macro use in gas and ld testsuites"H.J. Lu16-32/+32
This reverts commit c0e9aca554e33e900efbd6425c1830f0a20012f5. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15gas: pru: Fix trailing whitespace handlingDimitar Dimitrov3-0/+25
With commit 6ae8a30d44f016cafb46a75843b5109316eb1996, arguments followed by a C-style comment ended up with a trailing space. That extra space character confused the PRU register name matching, leading to spurious errors about unrecognized registers. This affected existing code like newlib's setjmp.s for pru. Fix by stripping the trailing whitespace for any argument. Even with 6ae8a30d44f016cafb46a75843b5109316eb1996 reverted, this patch is safe to be applied. Successfully regression-tested with GCC and newlib testsuites for pru-unknown-elf. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-08-14gas: correct .irpc handling with empty stringJan Beulich2-2/+3
Following 69cab370cf66 ("gas: adjust handling of quotes for .irpc") the closing quote was mistakenly treated as the first quoted character.
2024-08-14x86: correct .insn with opcode extension and VEX/XOP/EVEX encodingJan Beulich3-5/+15
When VexVVVV handling was re-worked, .insn broke: When an opcode extension is in use, VexVVVV_DST needs using now, as ModR/M.reg is already occupied, matching what c8866e3ec5e2 ("x86: Drop using extension_opcode to encode vvvv register") did. While adding (bad) POP2 forms, also slightly adjust existing ones: No need to use XMM registers, and no need to specify %r8 when really %rax is meant twice (EVEX.vvvv not really being the culprit there, or else EVEX.V' would also have needed mentioning).
2024-08-13gas macro arg1 testAlan Modra2-4/+7
A number of targets pad out the data section, and there are targets that have 2 or 4 octets per byte. And some even that don't have '#' as a line comment char. tic6x-elf fails the test with "Error: too many positional arguments". * testsuite/gas/macros/arg1.s: Pad out data section. Use C style comments. * testsuite/gas/macros/arg1.d: Adjust to suit. Don't run on multi-octet per byte targes. xfail tic6x.
2024-08-12gas: Add macro tests for PR gas/32073H.J. Lu6-0/+43
1. Add a macro test for expression argument with inner white spaces and a white space before argument added by C preprocessor. 2. Add a x86-64 specific macro test. PR gas/32073 * testsuite/gas/i386/x86-64-macro-1.d: New file. * testsuite/gas/i386/x86-64-macro-1.s: Likewise. * testsuite/gas/i386/x86-64.exp: Run x86-64-macro-1. * testsuite/gas/macros/arg1.d: New file. * testsuite/gas/macros/arg1.s: Likewise. * testsuite/gas/macros/macros.exp: Run arg1. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-12Revert "gas: have scrubber retain more whitespace"H.J. Lu12-173/+171
This reverts commit 6ae8a30d44f016cafb46a75843b5109316eb1996. This fixes PR gas/32073.
2024-08-12Revert "gas: drop scrubber states 14 and 15"H.J. Lu3-0/+34
This reverts commit 7dd0dfbde7ee31167a3b2e192a575493d26b7b0a. This is a prerequisite for the PR gas/32073 fix.
2024-08-09gas: drop scrubber states 14 and 15Jan Beulich3-34/+0
While sadly 5262831592fb doesn't say anything on why these would have been needed, the latest with the removal of most of the opcode vs operands distinction in the scrubber these shouldn't be needed anymore. The implementation was a little questionable anyway, in moving back to states expecting labels, when clearly labels shouldn't really be following predicates (in practice, due to another bug, at least ia64 permits such).
2024-08-09gas: have scrubber retain more whitespaceJan Beulich12-171/+173
According to the description of the state machine, the expectation appears to be that (leaving aside labels) any insn mnemonic or directive would be followed by a comma separated list of operands. That may have been true very long ago, but the latest with the advent of more elaborate macros this isn't rhe case anymore. Neither macro parameters in macro definitions nor macro arguments in macro invocations are required to be separated by commas. Hence whitespace serves a crucial role there. Plus even without "real" macros issues exist, in e.g. .irp n, ... insn\n\(suffix) operand1, operand2 .endr Whitespace following the closing parenthesis would have been removed (ahead of even processing the .irp), as the "opcode" was deemed to have ended earlier already. Therefore, squash the distinction between "opcode" and operands, i.e. fold state 10 back into state 3. Also drop most of the distinction between "symbol chars" and "relatively normal" ones. Not entirely unexpectedly this results in the need to skip whitespace in a few more places in arch-specific code (and quite likely more changes are needed for insn forms not covered by the testsuite). As a result the D10V special case is no longer necessary. In config/tc-sparc.c also move a comment to be next to the code being commented. In opcodes/cgen-asm.in some further cleanup is done, following the local var adjustments.
2024-08-09MIPS: relax gas testsuite whitespace expectationsJan Beulich10-32/+32
In a subsequent change the scrubber is going to be changed to retain further whitespace. Test case expectations generally would better not depend on the specific whitespace treatment by the scrubber, unless of course a test is specifically about it. Adjust relevant test cases to permit blanks where those will subsequently appear.
2024-08-09aarch64: relax gas testsuite whitespace expectationsJan Beulich108-8976/+8976
In a subsequent change the scrubber is going to be changed to retain further whitespace. Test case expectations generally would better not depend on the specific whitespace treatment by the scrubber, unless of course a test is specifically about it. Adjust relevant test cases to permit blanks where those will subsequently appear.
2024-08-09Arm: relax gas testsuite whitespace expectationsJan Beulich12-171/+171
In a subsequent change the scrubber is going to be changed to retain further whitespace. Test case expectations generally would better not depend on the specific whitespace treatment by the scrubber, unless of course a test is specifically about it. Adjust relevant test cases to permit blanks where those will subsequently appear.
2024-08-09m32r: move scrubber override to target headerJan Beulich2-3/+3
Other than LEX_IS_* settings, such #define-s don't belong into the common source file.
2024-08-09Arm: respect line separators for .symver scrubber special caseJan Beulich1-1/+1
Directives end at "line" (really: statement) separators, not just at new-line chars.
2024-08-09gas: respect CR_EOL also for scrubbingJan Beulich1-1/+7
While apparently intended to be only externally controlled (e.g. via specifying CFLAGS at make invocation), we should still keep scrubber and lexer in sync in this regard. There's one place which imo was previously wrong already, but would go further wrong and hence is being adjusted right here: An .mri directive can be terminated by any kind of "line" (really: statement) separators.
2024-08-09gas: have scrubber also respect quoted labelsJan Beulich4-0/+16
For the handling of ':' elsewhere in the scrubber to be correct with regard to labels, the state after parsing a string found at the start of a line must match that after finding a symbol character at the start of a line. (Things are largely okay when there's whitespace ahead of the label: Whitespace after the colon then is retained rather than dropped for typical targets like x86, but read.c will know to deal with that.)
2024-08-09RISC-V: PR32014, .option directives shuoldn't affect elf attribute.Nelson Chu11-66/+60
The .option arch/rvc/norvc/push/pop directives can only take effect for a small/large specific code region, so they are not file-level architecture setting. They should only affect the mapping symbols only rather than the file-level elf architecture attribute. Otherwise, the elf architecture attribute will appear to missing some extensions when -flto merges files with different .option architecture settings. gas/ PR 32014 * config/tc-riscv.c (file_arch_str): New const char *, rather than the arch_str in the riscv_rps_as.subset_list, it's file-level so only be affected by .attribute arch directive. (riscv_reset_subsets_list_arch_str): Renamed to riscv_set_arch_str, and also can handle both file_arch_str and arch_str in subset_list, just give the pointer address as the input. (riscv_set_arch): Called by -march and .attribute arch, so set both file_arch_str and arch_str in subset_list. (s_riscv_option): Updated .option arch/rvc/norvc/push/pop that only set the arch_str in subset_list. (riscv_write_out_attrs): Output elf architecture attribute according to file_arch_str. Freed file_arch_str. * doc/c-riscv.texi: Added destrbution that .option directives shouldn't affect the elf attribute settings. * testsuite/gas/riscv/option-arch.s: From option-arch-01/02/03 merged. * testsuite/gas/riscv/option-arch-dis.d: Likewise, for dis-assembler. * testsuite/gas/riscv/option-arch-attr.d: Likewise, to check readelf -A.
2024-08-09gas: sparc: Fix faligndatai assembly and disassemblyRichard Henderson3-10/+11
The first operand is a general register, not an fp register; the third operand is encoded into RS2, not RS3; the second operand must match the destination operand.
2024-08-07score: drop TC_ALPHA codeJan Beulich2-24/+0
I can't see how that could ever have come into play.
2024-08-07gas: drop dead VMS code from command line handlingJan Beulich1-23/+6
The only time 'v' was overridden, allowing for an optional value, was when OBJ_VMS support still existed (until a little less than 20 years ago). Drop the respective leftovers. With that OPTION_VERBOSE also becomes redundant and hence is being dropped.
2024-08-07VAX: drop OBJ_VMS leftoversJan Beulich2-55/+7
OBJ_VMS support was dropped almost 20 years ago (e330299ed5ee). Drop respective code from tc-vax.c as well. While there, make adjustments for OBJ_ELF as well: -K was dropped over 20 years ago (530556a951f5), yet left in md_shortopts. OPTION_PIC isn't really necessary either; 'k' can be used instead. And then the ELF options available weren't displayed by md_show_usage().
2024-08-07gas: improve unrecognized command line option diagnosticJan Beulich4-4/+8
Printing optc with %c makes sense only when optc is actually a character. Add logic to also deal with unrecognized long options, rejected by md_parse_option() rather than get_opt_long_only(). Also quote the reproduced strings, such that possible included whitespace can be recognized.
2024-08-07gas/NEWS: Moved RISC-V Zimop/Zcmop changes into 2.43 section due to backport.Nelson Chu1-2/+2
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