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2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti1-1/+0
2025-01-10aarch64: Fix incorrect gating of sme-lutv2 instructionsAndrew Carlotti2-0/+8
Only the strided form of the luti4 intrinsic requires FEAT_SME2p1.
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.Srinath Parvathaneni5-0/+90
This patch adds support for FEAT_SME_F16F16 instructions fcvt and fcvtl, which are available on passing command line flags +sme-f16f16 and the spec is available here[1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.Srinath Parvathaneni5-0/+489
This patch adds support for FEAT_SME_F16F16 instructions fmla and fmls, which are available on passing command line flags +sme-f16f16 and the spec is available here[1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.Srinath Parvathaneni5-0/+99
This patch adds support for FEAT_SME_F16F16 instructions fmops and fmopa, which are available on passing command line flags +sme-f16f16 and the spec is available here[1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni7-1/+133
This patch adds support for FEAT_SME_F16F16 feature (Non-widening half-precision FP16 to FP16 arithmetic for SME2), which is enabled using command line flags +sme-f16f16 to -march (which enables both FEAT_SME2 and FEAT_SME_F16F16). There are couple of instructions (fadd and fsub variants) which should be allowed by the assembler on either passing +sme-f16f16 or +sme-f8f16. Those instructions are already supported in the current assembler, this patch adds tests for those instructions as well.
2025-01-10x86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc6-3/+28
This patch adds support for Zhaoxin PadLock RNG2 instruction, the CPUID EDX bit[23] indicates its enablement, it includes REP XRNG2 instruction. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock RNG2 instruction. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLock RNG2 instruction. (output_insn): Handle PadLock RNG2 instruction. * doc/c-i386.texi: Document PadLock RNG2. * testsuite/gas/i386/i386.exp: Add PadLock RNG2 test. * testsuite/gas/i386/padlock_rng2.d: Ditto. * testsuite/gas/i386/padlock_rng2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockRNG2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockRNG2): New. * i386-opc.tbl: Add Zhaoxin PadLock RNG2 instruction. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-10gas: consolidate . latchingJan Beulich7-20/+28
... by purging dot_{frag,value}. Right now these two and dot_symbol are updated independently, which can't be quite right. Centralize .-related information in dot_symbol, updating it also where previously dot_{frag,value} were updated. Since S_GET_VALUE() can't be used to retrieve what used to be dot_value, introduce a new helper to fetch both frag and offset.
2025-01-10aarch64: re-work PR gas/27217 fix againJan Beulich3-22/+64
Commit c1723a8118f0 ("Arm64: re-work PR gas/27217 fix") really was only a band-aid; Nick's original solution to the problem was technically preferable, yet didn't work when . came into play. Undo most of that change, now that expr_defer expression parsing mode latches dot as is desired here. Also add testing for the . case, which I should have done already back at the time.
2025-01-10gas: make deferred expression evaluation generally latch dotJan Beulich8-16/+19
Deferring expression evaluation is often necessary. However, the value current_location() records typically is intended to represent the location at the point of use of the expression, with the exception being .eqv (or its == equivalent). Change how expr_defer behaves in this regard, and introduce a special mode just for pseudo_set() to use. Introduce a predicate to cover both "deferred" modes, and use it everywhere except in current_location(), where only the new mode wants checking for.
2025-01-09xfail quad-div2 test for am33Alan Modra1-1/+1
2025-01-09Excessive gas .irpt countAlan Modra2-3/+3
There is a test in do_repeat to error on "negative" repeat counts. Just at what value a ssize_t is negative of course depends on the host. Change the excessive repeat count to a fixed value, 0x80000000, ie. what would be seen as negative on a 32-bit host.
2025-01-09RISC-V: Add partial instruction display testsCharlie Jenkins4-0/+35
When objdump is specified with a stop address that ends up in the middle of an instruction, the partial instruction is expected to be displayed. These three tests check that the partial instruction is correctly displayed when there are 1, 2, or 3 bytes of the instruction dumped. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
2025-01-08Support Intel AMX-FP8Liwei Xu10-1/+146
In this patch, we will support AMX-FP8 feature. Since in the foreseeable future, only AMX-MOVRS will also use VEX_MAP5, we currently will not add a table of 256 entries and handle just like MAP7. gas/ChangeLog: * config/tc-i386.c: Add amx_fp8. * doc/c-i386.texi: Document .amx_fp8. * testsuite/gas/i386/x86-64.exp: Run AMX-FP8 tests. * testsuite/gas/i386/x86-64-amx-fp8-bad.d: New test. * testsuite/gas/i386/x86-64-amx-fp8-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0): New. (X86_64_VEX_MAP5_FD): Ditto. (VEX_LEN_MAP5_FD_X86_64): Ditto. (VEX_W_MAP5_FD_X86_64_L_0):Ditto. (prefix_table): Add PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0. (x86_64_table): Add X86_64_VEX_MAP5_FD. (vex_len_table): Add VEX_LEN_MAP5_FD_X86_64. (vex_w_table): Add VEX_W_MAP5_FD_X86_64_L_0. * i386-gen.c: Add CPU_AMX_FP8_FLAGS and CPU_ANY_AMX_FP8_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: Add cpuamx_fp8. * i386-opc.tbl: Add AMX_FP8 instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-06x86/Intel: don't accept memory operands with J*CXZ and LOOP*Jan Beulich1-6/+2
PR gas/31887 Like for, in particular, J<cc> such should be rejected. Simplify the respective conditional in i386_intel_operand(), leveraging that JumpAbsolute will never occur in the first template of a mnemonic- specific group (thus making it unnecessary to exclude that one case). At this occasion do the same simplification later in the function as well: The resulting two operands will uniformly be invalid for all mnemonics other than CALL and JMP (and their AT&T counterparts, which we've been wrongly accepting in Intel syntax) anyway.
2025-01-06gas: special-case division / modulo by ±1Jan Beulich9-6/+180
Dividing the largest possible negative value by -1 generally is UB, for the result not being representable at least in commonly used binary notation. This UB on x86, for example, is a Floating Point Exception on Linux, i.e. resulting in an internal error (albeit only when sizeof(valueT) == sizeof(void *); the library routine otherwise involved apparently deals with the inputs quite okay). Leave original values unaltered for division by 1; this may matter down the road, in case we start including X_unsigned and X_extrabit in arithmetic. For the same reason treat modulo by 1 the same as modulo by -1. The quad and octa tests have more relaxed expecations than intended, for X_unsigned and X_extrabit not being taken into account [yet]. The upper halves can wrongly end up as all ones (for .octa, when !BFD64, even the upper three quarters). Yet it makes little sense to address this just for div/mod by ±1. quad-div2 is yet more special, to cover for most 32-bit targets being unable to deal with forward-ref expressions in .quad even when BFD64; even ones being able to (like x86) then still don't get the values right.
2025-01-03macro nesting testcasesAlan Modra3-22/+25
Fix a bunch of regressions. Don't start anything besides a label in first column, don't name macros the same as directives, and make labels global.
2025-01-03nesting[123].d: Replace Sone with Some in commentH.J. Lu3-3/+3
* testsuite/gas/macros/nesting1.d: Replace Sone with Some in comment. * testsuite/gas/macros/nesting2.d: Likewise. * testsuite/gas/macros/nesting3.d: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-01-02gas: Revert PR 32391 related commits to fix 3 regressionsH.J. Lu15-445/+126
9f2e3c21f65 Fix the handling or arguments and macro pseudo-variables inside nested assembler macros. introduced 3 regressions of PR gas/32484, PR gas/32486 and PR gas/32487. Revert all PR 32391 related commits and add tests for PR gas/32484, PR gas/32486, PR gas/32487. PR gas/32484 PR gas/32486 PR gas/32487 * testsuite/gas/macros/macros.exp: Run nesting1, nesting2 and nesting3. * testsuite/gas/macros/nesting1.d: New file. * testsuite/gas/macros/nesting1.s: Likewise. * testsuite/gas/macros/nesting2.d: Likewise. * testsuite/gas/macros/nesting2.s: Likewise. * testsuite/gas/macros/nesting3.d: Likewise. * testsuite/gas/macros/nesting3.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-01-02Support Intel AMX-TF32Haochen Jiang10-1/+102
In this patch, we will support AMX-TF32. It is a simple ISA comparing to the previous ones, so there is no special handling. gas/ChangeLog: * config/tc-i386.c: Add amx_tf32. * doc/c-i386.texi: Document .amx_tf32. * testsuite/gas/i386/x86-64.exp: Run AMX-TF32 tests. * testsuite/gas/i386/x86-64-amx-tf32-bad.d: New test. * testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F3848_X86_64_W_0_L_0): New. (X86_64_VEX_0F3848): Ditto. (VEX_LEN_0F3848_X86_64_W_0): Ditto. (VEX_W_0F3848_X86_64): Ditto. (prefix_table): Add PREFIX_VEX_0F3848_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F3848. (vex_len_table): Add VEX_LEN_0F3848_X86_64_W_0. (vex_w_table): Add VEX_W_0F3848_X86_64. * i386-gen.c (isa_dependencies): Add AMX_TF32. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TF32): New. (i386_cpu_flags): Add cpuamx_tf32. * i386-opc.tbl: Add AMX-TF32 instructions. * i386-tbl.h: Regenerated.
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang14-8/+239
In this patch, we will support AMX-TRANSPOSE. Since AMX-TRANSPOSE will be used with other CPUIDs very often, we put it into CPU_FLAGS_COMMON. To implement TMM pair, we reused ImplicitGroup and adjust the condition in process_operands for the instructions. APX_F extension is also handled in this patch, where it extends T2RPNTLVW[Z0,Z1][,T1] to EVEX.128.NP/66.0F38.W0 6E/6F !(11):rrr:100 with NF=0. Also, TTDPFP16PS should base on AMX_FP16, not AMX_BF16 in ISE055. It would be fixed in ISE056. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_transpose. (_is_cpu): Ditto. (process_operands): Adjust the condition for AMX-TRANSPOSE. * doc/c-i386.texi: Document .amx_transpose. * testsuite/gas/i386/x86-64.exp: Run AMX-TRANSPOSE tests. * testsuite/gas/i386/x86-64-amx-transpose-bad.d: New test. * testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_VEX_0F386E_X86_64_W_0): New. (MOD_VEX_0F386F_X86_64_W_0): Ditto. (PREFIX_VEX_0F385F_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386B_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0): Ditto. (PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0): Ditto. (X86_64_VEX_0F385F): Ditto. (X86_64_VEX_0F386B): Ditto. (X86_64_VEX_0F386E): Ditto. (X86_64_VEX_0F386F): Ditto. (VEX_LEN_0F385F_X86_64_W_0): Ditto. (VEX_LEN_0F386B_X86_64_W_0): Ditto. (VEX_LEN_0F386E_X86_64_W_0_M_0): Ditto. (VEX_LEN_0F386F_X86_64_W_0_M_0): Ditto. (VEX_W_0F385F_X86_64): Ditto. (VEX_W_0F386B_X86_64): Ditto. (VEX_W_0F386E_X86_64): Ditto. (VEX_W_0F386F_X86_64): Ditto. (mod_table): Add MOD_VEX_0F386E_X86_64_W_0, MOD_VEX_0F386F_X86_64_W_0. (prefix_table): Add PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0, PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0. Add new instructions for PREFIX_VEX_0F386C_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F385F, X86_64_VEX_0F386B, X86_64_VEX_0F386E, X86_64_VEX_0F386F. (vex_len_table): Add VEX_LEN_0F385F_X86_64_W_0, VEX_LEN_0F386B_X86_64_W_0, VEX_LEN_0F386E_X86_64_W_0_M_0, VEX_LEN_0F386F_X86_64_W_0_M_0. (vex_w_table): Add VEX_W_0F385F_X86_64, VEX_W_0F386B_X86_64, VEX_W_0F386E_X86_64, VEX_W_0F386F_X86_64. * i386-gen.c (cpu_flag_init): Add AMX_TRANSPOSE. (cpu_flags): Add CpuAMX_TRANSPOSE. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TRANSPOSE): New. (i386_cpu): Add cpuamx_transpose. * i386-opc.tbl: Add AMX-TRANSPOSE instructions. * i386-tbl.h: Regenerated. Co-authored-by: Hu, Lin1 <lin1.hu@intel.com>
2025-01-01memory leak in gas dwarf2dbg.cAlan Modra1-0/+4
Found when running the pr27355 testcase. PR 27355 PR 27426 * dwarf2dbg.c (allocate_filename_to_slot): Update dirs_in_use.
2025-01-01gas obj-elf.c memory leaksAlan Modra1-4/+4
* config/obj-elf.c (obj_elf_section): Use notes_memdup for linked_to_symbol_name. (obj_elf_find_and_add_versioned_name): Use notes_alloc for versioned_name.
2025-01-01PR 32391 memory leakAlan Modra1-0/+1
* macro.c (sub_actual): Free newadd.
2025-01-01gas reloc_list memory leaksAlan Modra3-5/+5
Put these on the notes obstack too. * config/tc-wasm32.c (wasm32_leb128): Use notes_alloc for reloc_list vars. * read.c (s_reloc): Likewise. * write.c (create_note_reloc): Likewise. (write_object_file): Reset reloc_list after write_relocs.
2025-01-01gas tc_gen_reloc memory leaksAlan Modra67-345/+288
This makes all the tc_gen_reloc functions and the associated array in write.c:write_relocs use notes_alloc rather than malloc. tc-hppa.c tc_gen_reloc gets a few more changes, deleting some dead code, and tidying code that duplicates prior initialisation.
2025-01-01gas gen-sframe memory leaksAlan Modra2-75/+62
More freeing required. * gen-sframe.c (all_sframe_fdes, last_sframe_fde): Move earlier, make file scope. (sframe_row_entry_new): Move earlier. (sframe_row_entry_free): New function. (sframe_fde_alloc, sframe_fde_free): Move earlier. (sframe_fde_link): Delete. Expand into.. (create_sframe_all): ..here. (output_sframe_internal): Delete silly sframe_flags init. Free fdes. Reset static vars. (sframe_xlate_ctx_cleanup): Use sframe_row_entry_free. Free remember_fre too. Don't re-init xlate_ctx we're about to drop. * gen-sframe.h (all_sframe_fdes): Don't declare.
2025-01-01gas dw2gencfi memory leaksAlan Modra1-25/+30
Some of these could have remained as malloc'd memory, but that would require quite a bit of code to traverse frch_cfi_data for example, and would rely on matching cfi directives (ie. valid input). Just put them on the notes obstack instead. * dw2gencfi.c (alloc_fde_entry): Use notes_calloc. (alloc_cfi_insn_data): Likewise. (cfi_end_fde): Don't free frch_cfi_data. (cfi_add_label): Use notes_strdup. (cfi_add_CFA_remember_state): Use notes_alloc. (cfi_add_CFA_restore_state): Don't free. (dot_cfi_escape): Use notes_alloc. (cfi_finish): Free cies after each pass, not before. Clear out static vars too.
2025-01-01gas include_dirs memory leakAlan Modra2-1/+2
This is the first of a series of patches aimed at making it possible to configure with CFLAGS="-g -O2 -fsanitize=address,undefined" and run the binutils and gas testsuite on x86_64-linux without using ASAN_OPTIONS=detect_leaks=0. ie. the patch series is aimed at fixing common gas, ar, objcopy, objdump, and readelf leaks. * config/tc-tic54x.c (md_begin): Make use of notes_strdup rather than xstrdup to copy entries added to include_dirs. * read.c (read_end): Free include_dirs array.
2025-01-01gas totalfragsAlan Modra2-3/+3
Avoid any possibility of signed overflow. (Seen on oss-fuzz). * frags.c (totalfrags): Make unsigned. (get_frag_count): Return unsigned. * frags.h (get_frag_count): Likewise.
2025-01-01Update year range in copyright notice of binutils filesAlan Modra589-593/+593
2024-12-26macro.c:871 heap-buffer-overflowAlan Modra1-2/+2
PR 32391 commit 9f2e3c21f6 fallout again. Also fix another 'macro' may be used uninitialized.
2024-12-26buffer overflow in gas/app.cAlan Modra1-4/+10
This testcase: .irp x x x " .end # .endr manages to access lex[EOF]. xxx: Warning: end of file in string; '"' inserted xxx:1: Warning: missing closing `"' gas/app.c:844:16: runtime error: index -1 out of bounds for type 'char [256] Following that there is a buffer overflow. Stop this happening, and in other similar places, by checking for EOF.
2024-12-24PR 32391 testcaseAlan Modra1-60/+60
The new testcase results in these regressions: hppa64-hp-hpux11.23 +FAIL: Nested macros (PR 32391) hppa-hp-hpux10 +FAIL: Nested macros (PR 32391) i386-darwin +FAIL: Nested macros (PR 32391) Fix the hppa regressions by ensuring that only symbols start on the first column.
2024-12-24Fix error: macro may be used uninitializedAlan Modra1-3/+2
PR 32391 commit 9f2e3c21f6 fallout
2024-12-23Support Intel AVX10.2 minmax, vector copy and compare instructionsHaochen Jiang15-0/+942
In this patch, we will support AVX10.2 minmax, vector copy and compare instructions. This will finish the new instruction form support for AVX10.2. Most of them are new instructions forms except for vmovd and vmovw, which are extended usage from the old ones. gas/ChangeLog: * NEWS: Mention AVX10.2. * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-5-intel.d: New test. * testsuite/gas/i386/avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/avx10_2-512-miscs-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-512-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h: Add EVEX_LEN_0F7E_P_1_W_1, EVEX_LEN_0FD6_P_2_W_0, EVEX_LEN_MAP5_6E and EVEX_LEN_MAP5_7E. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F3A52, PREFIX_EVEX_0F3A53, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_6E and PREFIX_EVEX_MAP5_7E. * i386-dis-evex-w.h: Adjust EVEX_W_0F3A42, EVEX_W_0F7E_P_1 and EVEX_W_0FD6. Add EVEX_W_MAP5_6E_P_1 and EVEX_W_MAP5_7E_P_1. * i386-dis-evex.h: Add and adjust table entries for AVX10.2. * i386-dis.c (PREFIX_EVEX_0F2E): New. (PREFIX_EVEX_0F2F): Ditto. (PREFIX_EVEX_0F3A52): Ditto. (PREFIX_EVEX_0F3A53): Ditto. (PREFIX_EVEX_MAP5_2E): Ditto. (PREFIX_EVEX_MAP5_2F): Ditto. (PREFIX_EVEX_MAP5_6E_L_0): Ditto. (PREFIX_EVEX_MAP5_7E_L_0): Ditto. (EVEX_LEN_0F7E_P_1_W_1): Ditto. (EVEX_LEN_0FD6_P_2_W_0): Ditto. (EVEX_LEN_MAP5_6E): Ditto. (EVEX_LEN_MAP5_7E): Ditto. (EVEX_W_MAP5_6E_P_1): Ditto. (EVEX_W_MAP5_7E_P_1): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Jun Zhang <jun.zhang@intel.com> Co-authored-by: Zewei Mo <zewei.mo@intel.com>
2024-12-20arm: fix incorrect assembly of stm{,ia} as push [PR32363]Richard Earnshaw3-52/+67
PR/32363. Gas was incorrectly translating stm sp!, {regs} into push {regs} but this is invalid. Conversely, it was also failing to translate stmfd sp!, {lowregs[, lr]} into a 16-bit push instruction. Fortunately stmia SP! is unlikely to be a common idiom on a full-descending stack as it writes values to the stack, then immediately deallocates that bit of the stack. Fixed this and cleaned up the logic somewhat. While there, change some of the ordering so that "ldm base, {base}" is transformed preferentially to LDR. This is in keeping with the general preference in the Arm ARM for avoiding single register LDM instructions.
2024-12-19Fix the handling or arguments and macro pseudo-variables inside nested ↵Nick Clifton9-64/+444
assembler macros. PR 32391
2024-12-19PPC: drop redundant value conversion from md_assemble()Jan Beulich1-7/+0
Just ahead of the enclosing OBJ_ELF conditional the exact same conversion was already carried out, with "val" not further changed in between.
2024-12-19Adjust expected loongarch32 test resultsAlan Modra2-17/+17
readelf and objdump differ in output for 32-bit vs 64-bit. * testsuite/gas/loongarch/dwarf-regnum.d: Adjust to suit both 32-bit and 64-bit output. * testsuite/gas/loongarch/localpic.d: Likewise.
2024-12-18Support Intel SM4 AVX10.2 extensionHaochen Jiang20-0/+389
In this patch, we will support SM4 AVX10.2 extension part. It is a promotion from VEX encoding to EVEX encoding. The EVEX encoding is based on AVX10.2, which is the same as the upcoming MOVRS ISA. Thus, we decide to pull AVX10.2 out to CPU_COMMON_FLAGS. While I have also tried to merge the table like AVX/AVX512, I choose to just templatize the table. I am okay to go either way, but slightly prefer the templatizing one since probably SM4 would be the only ISA with AVX10.2 needs such VEX to EVEX extension (MOVRS does not need that). Also, it is a tendancy that we will directly provide EVEX encodings and no VEX encodings for vector instructions since AVX10. This will make the adding in gas/config/tc-i386.c not that worthy. gas/ChangeLog: * NEWS: Support Intel SM4 EVEX instructions. * config/tc-i386.c (_is_cpu): Handle AVX10.2. * testsuite/gas/i386/i386.exp: Run SM4 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-sm4-intel.d: Add SM4 tests. * testsuite/gas/i386/avx10_2-256-sm4.d: Ditto. * testsuite/gas/i386/avx10_2-256-sm4.s: Ditto. * testsuite/gas/i386/avx10_2-512-sm4-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-sm4.d: Ditto. * testsuite/gas/i386/avx10_2-512-sm4.s: Ditto. * testsuite/gas/i386/avx10_2-sm4-inval.l: Ditto. * testsuite/gas/i386/avx10_2-sm4-inval.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-sm4.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-sm4.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-sm4.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-sm4.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-sm4-inval.l: Ditto. * testsuite/gas/i386/x86-64-avx10_2-sm4-inval.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add evex table entry for SM4. * i386-dis.h: Ditto. * i386-opc.h: (i386_cpu): Move AVX10.2 to CPU_FLAGS_COMMON. * i386-opc.tbl: Add SM4 EVEX instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2024-12-17aarch64: testsuite: remove macro expansion messages from expected error outputMatthieu Longo10-502/+6
gas generates an information diagnostic message for every context invoking a macro and generating a warning or error message. For the specific case of sysreg tests, this pollutes the expected error output for no benefit in term of test debug or testing coverage. This patch aims at stopping such diagnostic messages to be generated for the failure tests by providing --no-info flag to gas. It also removed from the expected outputs the information messages related to macro expansions.
2024-12-17gas: add new command line options to control diagnostic informational messagesMatthieu Longo5-1/+60
gas currently emits informational messages for context information along warnings. In the context of system register tests in AArch64 backend, these messages pollute the tests when checking for error message patterns in stderr output. This patch aims at providing two new flags while preserving the existing behavior if none of the options is provided. * --info, similar to the existing --warn flag to enable diagnostic informational messages (default behavior). * --no-info, similar to the existing --no-warn flag to disable diagnostic informational messages. It also adds the flags to the existing documentation, and command manual.
2024-12-16Move modification of bfd abs and und back to gasAlan Modra1-26/+34
In commit f592407e4d75 I deleted gas' obj_sec_set_private_data, and instead put the gas modification of bfd's *ABS* and *UND* sections in bfd_make_section_old_way. More recently in commit 8b5a21249537 I made tekhex symbol creation use bfd_make_section_old_way for symbol sections. After that we saw numerous non-repeatable oss-fuzz reports of accesses to freed memory involving relocation symbols. I think what is happening is: A tekhex testcase with an absolute symbol is run through the tool, modifying bfd_abs_section.symbol to point to a symbol on the bfd's objalloc memory. On closing that bfd bfd_abs_section.symbol points to freed memory. A second testcase is run through the tool with some access to the *ABS* symbol. This triggers the invalid memory access. The same thing could happen if a user runs objdump or nm with two files on the command line, the first being a tekhex file with absolute symbols, or if ld is given tekhex input among other files. Clearly, it's a bad idea to modify the *ABS* or *UND* sections for input files. bfd/ * section.c (bfd_make_section_old_way): Don't call _new_section_hook for standard abs, com, und and ind sections. gas/ * as.c (bfd_std_section_init): New function. (perform_an_assembly_pass): Move section initialisation to.. (gas_init): ..here. Use bfd_std_section_init.
2024-12-14Delete asection.symbol_ptr_ptrAlan Modra5-15/+8
This field is always set to point to asection.symbol, and no code ever changes it from its initial value. With one exception. elfxx-mips.c creates two sections with separate pointers to their symbols, and uses those as asection.symbol_ptr_ptr. Those pointers aren't modified, so they disappear in this patch too.
2024-12-13Give unique names to s390 assembler opcode tests.Nick Clifton17-17/+17
2024-12-13msp430/gas: correct BFD_RELOC_32 handlingJan Beulich1-1/+1
It was likely a copy-and-paste oversight that bfd_putl16() was used here from the very beginning. And of course there's a difference only if the value to be stored is different from the value that's already there; typically both are 0.
2024-12-13gas: avoid UB on signed multiplication in resolve_symbol_value()Jan Beulich1-1/+2
Commit 487b0ff02dda ("ubsan: signed integer multiply overflow") touched only one of the two affected places (the 3rd, resolve_expression(), is already using valueT type local variables).
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai4-17/+780
.cfi directives only support the use of register numbers and not register names or aliases. This commit adds support for 4 formats, for example: .cfi_offset r1, 8 .cfi_offset ra, 8 .cfi_offset $r1,8 .cfi_offset $ra,8 The above .cfi directives are equivalent and all represent dwarf register number 1. Display register aliases as specified in the psABI during disassembly.
2024-12-05Support Intel AVX10.2 satcvt instructionsHu, Lin114-0/+2416
In this patch, we will support AVX10.2 satcvt instructions. All of them are new instruction forms. In current documentation, it is still VCVTTNEBF162I[,U]BS, but it will change to VCVTTBF162I[,U]BS eventually. In table part, we used temporary <sign> iterator to reduce redundancy. It definitely could be done for legacy cvt insns, but it is out of this patch's scope. gas/ChangeLog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt-intel.d: New test. * testsuite/gas/i386/avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_68, PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B, PREFIX_EVEX_MAP5_6C, PREFIX_EVEX_MAP5_6D. * i386-dis-evex-w.h: Add EVEX_W_MAP5_6C_P_0, EVEX_W_MAP5_6C_P_2, EVEX_W_MAP5_6D_P_0, EVEX_W_MAP5_6D_P_2. * i386-dis-evex.h (prefix_table): Add PREFIX_EVEX_MAP5_68, * PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B. * i386-dis.c: (PREFIX_EVEX_MAP5_68): New. (PREFIX_EVEX_MAP5_69): Ditto. (PREFIX_EVEX_MAP5_6A): Ditto. (PREFIX_EVEX_MAP5_6B): Ditto. (PREFIX_EVEX_MAP5_6C): Ditto. (PREFIX_EVEX_MAP5_6D): Ditto. (EVEX_MAP5_6C_P_0): Ditto. (EVEX_MAP5_6C_P_2): Ditto. (EVEX_MAP5_6D_P_0): Ditto. (EVEX_MAP5_6D_P_2): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Zewei Mo <zewei.mo@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Co-authored-by: Levy Hsu <admin@levyhsu.com>
generated by cgit v1.1 at 2025-09-20 02:12:45 +0000