aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2024-09-26x86 TLS relocation checksAlan Modra1-7/+8
Some configurations (eg. i386-bsd, i386-msdos) broke with the addition of the TLS relocation checking. The "x86_elf_abi undeclared" error has been fixed, but "gotrel defined but not used" remains. Fix that. Also invert the preprocessor test around lex_got to make it positive logic and remove the LEX_AT condition which is no longer necessary. (The only x86 config files defining LEX_AT also define TE_PE.)
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei10-2/+85
This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
2024-09-24x86: Enable TLS relocation check only for ELFH.J. Lu1-11/+11
Since TLS relocation check is ELF specific, enable it only for ELF. PR gas/32022 * config/tc-i386.c (x86_tls_error_type): Define only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (x86_check_tls_relocation): Likewise. (x86_report_tls_error): Likewise. (i386_assemble): Check TLS relocations only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (md_show_usage): Output -mtls-check= only if OBJ_MAYBE_ELF or OBJ_ELF is defined. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-23Fix compile time error introduced by ↵Nick Clifton1-2/+8
d774bf9b3623239a1cfa729afcf048a15da657d3 for non-ELF x86 targets
2024-09-23x86: Turn PLT32 to PC32 only for PC-relative relocationsH.J. Lu5-1/+21
commit 292676c15a615b5a95bede9ee91004d3f7ee7dfd Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Feb 13 13:44:17 2020 -0800 x86: Resolve PLT32 reloc aganst local symbol to section resolved PLT32 relocation against local symbol to section and commit 2585b7a5ce5830e60a089aa2316a329558902f0c Author: H.J. Lu <hjl.tools@gmail.com> Date: Sun Jul 19 06:51:19 2020 -0700 x86: Change PLT32 reloc against section to PC32 turned PLT32 relocation against section into PC32 relocation. But these transformations are valid only for PC-relative relocations. Add fx_pcrel check for PC-relative relocations when performing these transformations to keep PLT32 relocation in `movq $foo@PLT, %rax`. gas/ PR gas/32196 * config/tc-i386.c (tc_i386_fix_adjustable): Return fixP->fx_pcrel for PLT32 relocations. (i386_validate_fix): Turn PLT32 relocation into PC32 relocation only if fixp->fx_pcrel is set. * testsuite/gas/i386/reloc32.d: Updated. * testsuite/gas/i386/reloc64.d: Likewise. * testsuite/gas/i386/reloc32.s: Add PR gas/32196 test. * testsuite/gas/i386/reloc64.s: Likewise. ld/ PR gas/32196 * testsuite/ld-x86-64/plt3.s: New file. * testsuite/ld-x86-64/x86-64.exp: Run plt3. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-21x86: Add tls check in gasCui, Lili23-32/+866
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-20x86-64: Never make R_X86_64_GOT64 section relativeH.J. Lu3-0/+17
R_X86_64_GOT64 relocation should never be made section relative. Change tc_i386_fix_adjustable to return 0 for BFD_RELOC_X86_64_GOT64. gas/ PR gas/32189 * config/tc-i386.c (tc_i386_fix_adjustable): Return 0 for BFD_RELOC_X86_64_GOT64. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/reloc64.s: Add more tests for R_X86_64_GOT64 and R_X86_64_GOTOFF64. ld/ PR gas/32189 * testsuite/ld-x86-64/x86-64.exp: Run PR gas/32189 test. * testsuite/ld-x86-64/pr32189.s: New file. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-18x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu7-44/+18
V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} aren't promoted to support EGPR in APX spec. Don't promote them out of APX spec. This commit effectively reverted: ec3babb8c10 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed 5a635f1f59a x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} eea4357967b x86/APX: VROUND{P,S}{S,D} can generally be encoded gas/ PR gas/32171 * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Add V{BROADCAST,EXTRACT,INSERT}{F,I}128 tests with EGPR. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} tests with EGPR. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Updated. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise. opcodes/ PR gas/32171 * i386-opc.tbl: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} entries with EGPR. * i386-tbl.h: Regenerated. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-15MIPS/GAS: Discard redundant instruction from DDIV/DREM macrosMaciej W. Rozycki12-29/+5
A sequence such as: li at,-1 bne xx,at,0f li at,1 dsll32 at,at,0x1f is produced in the expansion of the DDIV and DREM assembly macros, where a redundant `li at,1' instruction is used to load an intermediate value of 1 into $at, which is then left-shifted by 63 with `dsll32 at,at,0x1f' yielding 0x8000000000000000. However this value likewise results from left-shifting the value of -1, already present in $at at this point. Remove the extraneous instruction then, shortening the sequence emitted. Adjust dumps in the testsuite accordingly.
2024-09-15MIPS/GAS/testsuite: Print instructions in hex in division testsMaciej W. Rozycki21-241/+249
Add `--show-raw-insn' to division tests so as to verify branch offsets without the need to know actual offsets into the text section individual instructions have been assembled at. Add `-z' where applicable to make interlock NOP instructions appear in output so as to verify them without the need to know the offsets too. Replace individual offsets to match against with generic patterns so that a change in the expansion of an assembly macro does not affect code that follows.
2024-09-12s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus2-12/+12
This leverages commit ("s390: Simplify (dis)assembly of insn operands with const bits") to relax the operand constraints of the immediate operand that contains the constant Z- or T-bit of the following extended mnemonics: risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt Previously those instructions were the only ones where the assembler on s390 restricted the specification of the subject I3/I4 operand values exactly according to their specification to an unsigned 6- or 5-bit unsigned integer. For any other instructions the assembler allows to specify any operand value allowed by the instruction format, regardless of whether the instruction specification is more restrictive. Allow to specify the subject I3/I4 operand as unsigned 8-bit integer with the constant operand bits being ORed during assembly. Relax the instructions subject significant operand bit masks to only consider the Z/T-bit as significant, so that the instructions get disassembled as their *z or *t flavor regardless of whether any reserved bits are set in addition to the Z/T-bit. Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set the T-bit in operand I3, as they otherwise get disassembled as their rnsbgt, rosbgt, and rxsbgt counterpart. This aligns GNU Assembler to LLVM Assembler. opcodes/ * s390-opc.c (U6_18, U5_27, U6_26): Remove. (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define as INSTR_RIE_RRUUU while retaining insn fmt mask. (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only Z/T-bit of I3/I4 operand as significant. gas/testsuite/ * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. Reported-by: Dominik Steenken <dost@de.ibm.com> Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus1-7/+0
Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-11gas: avoid (scrubber) diagnostics for stuff past .endJan Beulich6-1/+108
What's past an active .end directive (when that has its default purpose) is supposed to be entirely ignored. That should be true not just for regular processing, but also for "pre-processing" (aka scrubbing). A complication is that such a directive may of course occur inside a (false) conditional or a macro definition. To deal with that make sure we can continue as usual if called another time. Note however that .end inside a macro will still have the full macro body expanded; dealing with that would require further (perhaps intrusive) adjustments in sb_scrub_and_add_sb() and/or callers thereof. However, at least some of the warnings issued by do_scrub_chars() are unlikely to occur when expanding a macro. (If we needed to go that far, presumably .exitm would also want recognizing.)
2024-09-11gas: restrict scrubber mri_{state,last_ch} varsJan Beulich1-5/+7
They're needed with TC_M68K only. Group them accordingly, just like is the case for Arm's symver vars.
2024-09-11arm: don't engage symver scrubber hack in CCS modeJan Beulich3-1/+20
In that mode the comment char is ; while @ has no special meaning. Engaging the special logic in that case results in comments not being respected on .symver lines.
2024-09-11x86: error handling in set_cpu_arch()Jan Beulich1-30/+34
Error messages there would better not be followed by further "junk at end of line" diagnostics. Arrange for this to be the case uniformly. While there also replace a somewhat unhelpful open-coding of restore_line_pointer().
2024-09-09s390: Document syntax to omit base register operandJens Remus1-2/+3
Document the s390-specific assembler syntax introduced by commit aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") to omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). While at it document the alternative syntax to omit the index register operand X in D(X,B) by coding D(,B) instead of D(B). gas/ * doc/c-s390.texi (s390 Operands): Document syntax to omit base register operand. Fixes: aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-09LoongArch: Fixed precedence of expression operators in instructionsLulu Cai3-12/+23
The precedence of the operators "+" and "-" in the current loongarch instruction expression is higher than "<<" and ">>", which is different from the explanation in the user guide. We modified the precedence of "<<" and ">>" to be higher than "+" and "-".
2024-09-07Add macros to get opcode of instructions approriatelyXin Wang2-122/+122
LoongArch: Add macros to get opcode and register of instructions appropriately Currently, we get opcode of an instruction by manipulate the binary with it's mask, it's a bit of a pain. Now a macro is defined to do this and a macro to get the RD and RJ registers which is applicable to most instructions of LoongArch are added.
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich1-1/+7
There's no need to have 30 redundant templates when we can easily take care of the operand swapping like we do for various other insns.
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich3-0/+55
Along the lines of 2513312930b2 ("x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms") these can similarly be converted to the shorter legacy-encoded CMOVcc.
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett9-2/+4222
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang12-57/+2652
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-30x86: replace conditional operators used to calculate booleansJan Beulich1-10/+11
The boolean expressions themselves are fine to use there.
2024-08-30x86: limit RegRex64 useJan Beulich1-9/+7
The special property really only applies to the "extended" byte regs having legacy word/dword counterparts. While touching involved code also drop redundant byte checks from a conditional in establish_rex(): The other remaining RegRex64 uses only exist on registers which can't be used as register operands anyway. Hence RegRex64 as an attribute of a (valid) register operand implies that it's a byte reg.
2024-08-30gas: properly check for ELF in LISTING_NODEBUG handlingJan Beulich1-36/+35
While OBJ_MAYBE_ELF presently implies OBJ_ELF (due to obj-multi.h including obj-elf.h for obscure reasons), there still need to be IS_ELF checks to cover for the OBJ_MAYBE_ELF case. Note, however, that code checking for ->debugging being true doesn't need such extra checks, as the field can only ever be true when IS_ELF. On the same basis reduce #ifdef-ary in debugging_pseudo(). Also move the field (into what on 64-bit architectures is a 32-bit gap) and put it inside an OBJ_ELF conditional, too. While there further switch int to bool in related code.
2024-08-30gas: generated code/data listing output vs .endr and alikeJan Beulich3-0/+14
These ending directives are swallowed by buffer_and_nest() and hence aren't seen by read_a_source_file(). Thus they also weren't announced to the listing subsystem. That was, when macro expansions are included, thus misguided to associate possible output resulting from the first line of the construct being expanded with both the .endr and that first line (i.e. showing it twice).
2024-08-30LoongArch: LoongArch64 allows relocations to use 64-bit addendsLulu Cai3-0/+23
Relocations using 64-bit addends allow larger constant offset address calculations to be fused.
2024-08-28x86: Report invalid TLS operatorH.J. Lu3-5/+5
Report invalid TLS operator, instead of relocation. PR gas/28595 * config/tc-i386.c (gotrel): Replace int with unsigned int. (i386_assemble): Report invalid TLS operator. * testsuite/gas/i386/inval-tls.l: updated. * testsuite/gas/i386/x86-64-inval-tls.l: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27x86: Report invalid TLS relocation nameH.J. Lu3-94/+101
Get TLS relocation name from its lex_got entry when reporting invalid instructions with TLS relocations. PR gas/28595 * config/tc-i386.c (gotrel): Moved from ... (lex_got): There. (i386_assemble): Get invalid TLS relocation name from its lex_got entry when reporting TLS relocation error. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27x86: Allow R_386_TLS_LE_32 with KMOVDH.J. Lu3-4/+2
Since there is no TLS IE transition, allow R_386_TLS_LE_32 with KMOVD. gas/ PR gas/28595 * config/tc-i386.c (i386_assemble): Remove BFD_RELOC_386_TLS_LE_32 from TLS code check. * testsuite/gas/i386/inval-tls.s: Remove foo@tpoff(%eax). * testsuite/gas/i386/inval-tls.l: Updated. ld/ PR gas/28595 * testsuite/ld-i386/i386.exp: Run tlsle1. * testsuite/ld-i386/tlsle1.d: New file. * testsuite/ld-i386/tlsle1.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei4-1/+64
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
2024-08-23x86: simplify SAE checkingJan Beulich1-12/+10
To determine whether SAE (with or without StaticRounding) is permitted there's no need to iterate over all operands. Even less so starting at the front (thus needlessly inspecting immediate operands as well). Leverage the pattern across all relevant templates and check only the last two operands, and also only for non-512 ones (besides the non-LIG case that was already checked for).
2024-08-23gas: update lex_type[] also for .mri directivesJan Beulich1-0/+2
Doing this just from read_begin(), i.e. merely based on command line options, can't be sufficient (assuming it's really relevant).
2024-08-23RISC-V: process rs_align_code also when relaxingJan Beulich2-35/+29
riscv_handle_align() runs after all input was processed. Whether relaxation is enabled for any particular piece of code is not recorded anywhere. (This issue was even "worked around" in a gas testcase, which is adjusted accordingly.) Furthermore, as demonstrated by an ld testcase, tail padding in an object file's executable sections depended on whether relaxation was enabled at the end of assembly: NOPs were emitted only when relaxation was off; zeroes were emitted with relaxation enabled. (It could probably be either way, but it should be independent of relaxation state at the end of assembly. Except of course write.c, in a comment ahead of #define-ing SUB_SEGMENT_ALIGN(), explicitly says "proper nop-filling".) While re-indenting, drop the "odd_padding" variable. It's used exactly once, and having the actual expression right in the if() is imo helping readers to understand what the intentions are. While touching the ld testcase, also tighten the expectations for the addresses of the two symbols: The last two digits have to have fixed values.
2024-08-19gas: ginsn: x86: pacify Wmaybe-uininitialized compiler warningIndu Bhagat1-0/+2
Fix PR binutils/32091 After commit d56083b5047b8e7cc9eda2f867bd2b75724920a1, some gcc versions may warn about unintialized usage of ginsn_func. Albeit false positive, adapt the code to escape the warning. gas/config/ * tc-i386-ginsn.c (x86_ginsn_indirect_branch): Early exit if unexpected args.
2024-08-16gas: don't open-code LEX_*NAMEJan Beulich6-7/+8
... except in read.c's definition of lex_type[], where readbility would otherwise suffer.
2024-08-15Revert "Arm: correct macro use in gas testsuite"H.J. Lu2-2/+2
This reverts commit cfa18744d435b55bbbbc5ef1ae1df67e84aa1777. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15Revert "bfin: correct macro use in gas testsuite"H.J. Lu1-4/+4
This reverts commit a1b7023447d19d70bc36d71b7627f457dbfae5ce. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15Revert "ia64: correct macro use in gas testsuite"H.J. Lu1-6/+6
This reverts commit 2231ac9b9e88191178001d0ae5845e292acb2a56. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15Revert "MIPS: correct macro use in gas and ld testsuites"H.J. Lu16-32/+32
This reverts commit c0e9aca554e33e900efbd6425c1830f0a20012f5. commit 6ae8a30d44f016cafb46a75843b5109316eb1996 Author: Jan Beulich <jbeulich@suse.com> Date: Fri Aug 9 11:59:31 2024 +0200 gas: have scrubber retain more whitespace has been reverted to fix PR gas/32073.
2024-08-15gas: pru: Fix trailing whitespace handlingDimitar Dimitrov3-0/+25
With commit 6ae8a30d44f016cafb46a75843b5109316eb1996, arguments followed by a C-style comment ended up with a trailing space. That extra space character confused the PRU register name matching, leading to spurious errors about unrecognized registers. This affected existing code like newlib's setjmp.s for pru. Fix by stripping the trailing whitespace for any argument. Even with 6ae8a30d44f016cafb46a75843b5109316eb1996 reverted, this patch is safe to be applied. Successfully regression-tested with GCC and newlib testsuites for pru-unknown-elf. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-08-14gas: correct .irpc handling with empty stringJan Beulich2-2/+3
Following 69cab370cf66 ("gas: adjust handling of quotes for .irpc") the closing quote was mistakenly treated as the first quoted character.
2024-08-14x86: correct .insn with opcode extension and VEX/XOP/EVEX encodingJan Beulich3-5/+15
When VexVVVV handling was re-worked, .insn broke: When an opcode extension is in use, VexVVVV_DST needs using now, as ModR/M.reg is already occupied, matching what c8866e3ec5e2 ("x86: Drop using extension_opcode to encode vvvv register") did. While adding (bad) POP2 forms, also slightly adjust existing ones: No need to use XMM registers, and no need to specify %r8 when really %rax is meant twice (EVEX.vvvv not really being the culprit there, or else EVEX.V' would also have needed mentioning).
2024-08-13gas macro arg1 testAlan Modra2-4/+7
A number of targets pad out the data section, and there are targets that have 2 or 4 octets per byte. And some even that don't have '#' as a line comment char. tic6x-elf fails the test with "Error: too many positional arguments". * testsuite/gas/macros/arg1.s: Pad out data section. Use C style comments. * testsuite/gas/macros/arg1.d: Adjust to suit. Don't run on multi-octet per byte targes. xfail tic6x.
2024-08-12gas: Add macro tests for PR gas/32073H.J. Lu6-0/+43
1. Add a macro test for expression argument with inner white spaces and a white space before argument added by C preprocessor. 2. Add a x86-64 specific macro test. PR gas/32073 * testsuite/gas/i386/x86-64-macro-1.d: New file. * testsuite/gas/i386/x86-64-macro-1.s: Likewise. * testsuite/gas/i386/x86-64.exp: Run x86-64-macro-1. * testsuite/gas/macros/arg1.d: New file. * testsuite/gas/macros/arg1.s: Likewise. * testsuite/gas/macros/macros.exp: Run arg1. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-12Revert "gas: have scrubber retain more whitespace"H.J. Lu12-173/+171
This reverts commit 6ae8a30d44f016cafb46a75843b5109316eb1996. This fixes PR gas/32073.
2024-08-12Revert "gas: drop scrubber states 14 and 15"H.J. Lu3-0/+34
This reverts commit 7dd0dfbde7ee31167a3b2e192a575493d26b7b0a. This is a prerequisite for the PR gas/32073 fix.
2024-08-09gas: drop scrubber states 14 and 15Jan Beulich3-34/+0
While sadly 5262831592fb doesn't say anything on why these would have been needed, the latest with the removal of most of the opcode vs operands distinction in the scrubber these shouldn't be needed anymore. The implementation was a little questionable anyway, in moving back to states expecting labels, when clearly labels shouldn't really be following predicates (in practice, due to another bug, at least ia64 permits such).
2024-08-09gas: have scrubber retain more whitespaceJan Beulich12-171/+173
According to the description of the state machine, the expectation appears to be that (leaving aside labels) any insn mnemonic or directive would be followed by a comma separated list of operands. That may have been true very long ago, but the latest with the advent of more elaborate macros this isn't rhe case anymore. Neither macro parameters in macro definitions nor macro arguments in macro invocations are required to be separated by commas. Hence whitespace serves a crucial role there. Plus even without "real" macros issues exist, in e.g. .irp n, ... insn\n\(suffix) operand1, operand2 .endr Whitespace following the closing parenthesis would have been removed (ahead of even processing the .irp), as the "opcode" was deemed to have ended earlier already. Therefore, squash the distinction between "opcode" and operands, i.e. fold state 10 back into state 3. Also drop most of the distinction between "symbol chars" and "relatively normal" ones. Not entirely unexpectedly this results in the need to skip whitespace in a few more places in arch-specific code (and quite likely more changes are needed for insn forms not covered by the testsuite). As a result the D10V special case is no longer necessary. In config/tc-sparc.c also move a comment to be next to the code being commented. In opcodes/cgen-asm.in some further cleanup is done, following the local var adjustments.
generated by cgit v1.1 at 2024-11-16 13:58:31 +0000