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2020-01-31Fix compile time build problem building the s390 assembler.Nick Clifton2-1/+6
2020-01-31[ARM]: Add support for vldmia/vldmdb/vstmia/vstmdb instructions in MVE.Srinath Parvathaneni4-4/+75
2020-01-31Updated translations for some of the binutils sub-directoriesNick Clifton3-6008/+7790
2020-01-31aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford6-2/+95
2020-01-30x86: prevent undue use of GOT32X and alike relocationsJan Beulich5-29/+68
2020-01-30cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi5-4/+11
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich8-22/+62
2020-01-30x86-64: also diagnose far returns / IRET with ambiguous operand sizeJan Beulich17-46/+134
2020-01-30x86: drop further pointless/bogus DefaultSizeJan Beulich2-5/+9
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu14-1/+270
2020-01-27Replace deprecated tcl case statements with switch statementsAlan Modra5-104/+114
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina3-0/+10
2020-01-22RISC-V: Change -march parsing.Jim Wilson8-1/+23
2020-01-22x86: Always disallow double word suffix with word general registerH.J. Lu6-30/+35
2020-01-22PowerPC64 __tls_get_addr_descAlan Modra2-1/+9
2020-01-21x86: testsuite adjustments after commit 1a0351246a5cJan Beulich5-0/+15
2020-01-21x86: replace adhoc ambiguous operand checking for CRC32Jan Beulich13-50/+60
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich46-128/+1068
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich5-0/+25
2020-01-20Updated translations for various binutils sub-directoriesNick Clifton2-3001/+3886
2020-01-20x86-64: Fix TLSDESC relaxation for x32H.J. Lu4-2/+19
2020-01-18Update version to 2.34.50. Regenerate configure and .pot files.Nick Clifton3-472/+482
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton2-0/+6
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu5-11/+22
2020-01-17Forgot to add testcases to commit for [binutils][arm] PR25376 Change MVE ...Andre Vieira4-0/+30
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2-7/+16
2020-01-16x86: drop found_cpu_match local variableJan Beulich2-8/+7
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich4-0/+42
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz5-11/+65
2020-01-15Reinstate gas em=freebsd for sparc-freebsdAlan Modra2-0/+5
2020-01-14x86: Updated align branch tests for Darwin and i686-pc-elfLili Cui22-179/+246
2020-01-14Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov11-126/+244
2020-01-13[gas][aarch64] Turn on SVE when using f32mm or f64mm extensionsMatthew Malcomson2-2/+7
2020-01-13[ARC][committed] Code cleanup and improvements.Claudiu Zissulescu4-4/+24
2020-01-13ubsan: wasm32: signed integer overflowAlan Modra2-2/+6
2020-01-13tic4x: sign extension using shiftsAlan Modra2-1/+6
2020-01-10HPUX gas testsuite fixesAlan Modra3-2/+8
2020-01-09Fix compile time warnings about comparisons always being false.Sergey Belyashov2-89/+101
2020-01-09x86: refine when to trigger optimizationsJan Beulich2-10/+15
2020-01-09x86-64: assert sane internal state for REX conversionsJan Beulich2-1/+8
2020-01-09x86: consistently convert to byte registers for TEST w/ imm optimizationJan Beulich2-11/+15
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich7-0/+60
2020-01-08Document the fact that the assembler's alignment pseudo-ops can be issued wit...Nick Clifton2-9/+20
2020-01-08Make the assembler generate an error if there is an attempt to define a secti...Nick Clifton6-0/+34
2020-01-08ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'Alan Modra2-2/+7
2020-01-07[ARC] Improve parsing instruction operands.Claudiu Zissulescu2-91/+117
2020-01-03Allow individual targets to decide if string escapes should be allowed. Disa...Sergey Belyashov7-9/+22
2020-01-03Updated Swedish translation for the GAS subdirectory.Nick Clifton2-408/+185
2020-01-03Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich3-24/+29
2020-01-03Arm64: correct {su,us}dot SIMD encodingsJan Beulich3-12/+34
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