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2022-09-21RISC-V: Implement Ztso extensionShihua2-0/+19
This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of, https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag. * elfxx-riscv.c: Add Ztso's arch. binutils\ChangeLog: * readelf.c (get_machine_flags): Set TSO flag. gas\ChangeLog: * config/tc-riscv.c (riscv_set_tso): Ditto. (riscv_set_arch): Ditto. * testsuite/gas/riscv/ztso.d: New test. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO): Ditto.
2022-09-21RISC-V: Always generate R_RISCV_CALL_PLT reloc for call in assembler.Nelson Chu3-8/+4
Since we have the same behaviors of CALL and CALL_PLT relocs in linker for now, https://github.com/bminor/binutils-gdb/commit/3b1450b38c644f99aa2e211747b428b9f8d15cca And the psabi already deprecate the CALL reloc, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a0dced85018d7a0ec17023c9389cbd70b1dbc1b0 Therefore, we should always generate R_RISCV_CALL_PLT reloc for call, even if it has @plt postfix. I believe LLVM (https://reviews.llvm.org/D132530) already support this, so GNU as should do the same thing. gas/ * config/tc-riscv.c (riscv_ip): Always generate CALL_PLT reloc for call, even if it has @plt postfix. * testsuite/gas/riscv/no-relax-reloc.d: Updated CALL to CALL_PLT. * testsuite/gas/riscv/relax-reloc.d: Likewise. ld/ * testsuite/ld-riscv-elf/variant_cc-r.d: Updated CALL to CALL_PLT.
2022-09-21Re: PowerPC64 pcrel got relocs against local symbolsAlan Modra1-6/+52
The last patch wasn't all that shiny. There are rather a lot more relocations that can hit the assertion in md_apply_fix if the symbol is local or absolute. Fix them all. * config/tc-ppc.c (ppc_force_relocation): Add all relocs that expect a symbol in md_apply_fix. Remove tls pcrel relocs already covered in general tls match range.
2022-09-21ppc/svp64: test setvl ms operandDmitry Selyutin2-0/+2
2022-09-20LoongArch: Set macro SUB_SEGMENT_ALIGN to 0.liuzhensong1-0/+2
2022-09-16PowerPC64 pcrel got relocs against local symbolsAlan Modra1-0/+6
Not that anyone would want to indirect via the GOT when an address can be loaded directly with pla, the following: pld 3,x@got@pcrel x: leads to "Internal error in md_apply_fix", because the generic parts of assembler fixup handling convert the fx_pcrel fixup to one without a symbol. Stop that happening. * config/tc-ppc.c (ppc_force_relocation): Add PLT_PCREL34 and assorted GOT_PCREL34 relocs.
2022-09-16RISC-V: Make g imply zmmul extension.Nelson Chu8-8/+8
bfd/ * elfxx-riscv.c (riscv_implicit_subset): Moved entry of m after g, so that g can imply zmmul. gas/ * testsuite/gas/riscv/attribute-01.d: Updated. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/march-imply-g.d: Likewise. * testsuite/gas/riscv/march-imply-unsupported.d: Likewise.
2022-09-15bfd, binutils, gas: Remove/mark unused variablesTsukasa OI1-3/+0
Clang generates a warning on unused (technically, written but not read thereafter) variables. By the default configuration (with "-Werror"), it causes a build failure (unless "--disable-werror" is specified). This commit adds ATTRIBUTE_UNUSED attribute to some of them, which means they are *possibly* unused (can be used but no warnings occur when unused) and removes others. bfd/ChangeLog: * elf32-lm32.c (lm32_elf_size_dynamic_sections): Mark unused rgot_count variable. * elf32-nds32.c (elf32_nds32_unify_relax_group): Remove unused count variable. * mmo.c (mmo_scan): Mark unused lineno variable. binutils/ChangeLog: * windmc.c (write_rc): Remove unused i variable. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Remove unused argnum variable. ld/ChangeLog: * pe-dll.c (generate_reloc): Remove unused bi and page_count variables.
2022-09-14bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI1-0/+18
Some components of GNU Binutils will pass "-Wstack-usage=262144" when "GCC >= 5.0" is detected. However, Clang does not support "-Wstack-usage", despite that related configuration part in bfd/warning.m4 handles the latest Clang (15.0.0 as of this writing) as "GCC >= 5.0". The option "-Wstack-usage" was ignored when the first version of Clang is released but even this "ignoring" behavior is removed before Clang 4.0.0. So, if we give Clang "-Wstack-usage=262144", it generates a warning, making the build failure. This commit checks "__clang__" macro to prevent adding the option if the compiler is identified as Clang. bfd/ChangeLog: * warning.m4: Stop appending "-Wstack-usage=262144" option when compiled with Clang. * configure: Regenerate. binutils/ChangeLog: * configure: Regenerate. gas/ChangeLog: * configure: Regenerate. gold/ChangeLog: * configure: Regenerate. gprof/ChangeLog: * configure: Regenerate. ld/ChangeLog: * configure: Regenerate. opcodes/ChangeLog: * configure: Regenerate.
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2-0/+5
The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. binutils/ * doc/binutils.texi: Document -Mfuture. gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. opcodes/ * ppc-dis.c (ppc_opts) <future>: Use it. * ppc-opc.c (FUTURE): Define.
2022-09-10Re: PR29466, APP/NO_APP with linefileAlan Modra1-1/+1
It looks like I copied the SIZE init across from binutils/testsuite/config/default.exp without some necessary editing. * testsuite/config/default.exp (SIZE): Adjust relative path.
2022-09-09RISC-V: Fix vector CSR requirementsTsukasa OI5-57/+57
Vector CSRs are also required on smaller vector subsets. Not only that the most of vector CSRs are general purpose (and must be accessible for every vector subsets), current minimum vector subset 'Zve32x' requires fixed point arithmetic, making remaining non-general purpose (fixed point arithmetic only) CSRs mandatory for such subsets. So, those CSRs must be accessible from 'Zve32x', not just from 'V'. This commit fixes this issue which caused CSR accessibility warnings. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise.
2022-09-08Gas generated incorrect debug info (top-level DW_TAG_unspecified_type DIE)Nick Clifton6-30/+50
PR 29559 * dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at the end of the list of children, not at the start of the CU information. * testsuite/gas/elf/dwarf-3-func.d: Update expected output. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
2022-09-07LoongArch: fix gas BFD_RELOC_8/16/24 bugmengqinggang3-18/+58
If fixP->fx_subsy is NULL, BFD_RELOC_8/16/24 can't convert to BFD_RELOC_LARCH_xxx. gas/config/tc-loongarch.c
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI6-0/+71
This patch makes possible to print the highest address (-1) and the addresses related to gp which value is -1. This is particularly useful if the highest address space is used for I/O registers and corresponding symbols are defined. Besides, despite that it is very rare to have GP the highest address, it would be nice because we enabled highest address printing on regular cases. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top address (-1) printing. * testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for GP-relative addressing when GP is the highest address (-1). * testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to enable printing the highest address. (maybe_print_address): Utilize `to_print_addr'. (riscv_disassemble_insn): Likewise.
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI4-1/+135
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an incorrectly sign-extended address is produced when printing. This commit fixes this by fitting an address into a 32-bit value on RV32. Besides, H. Peter Anvin discovered that we have wrong address computation for JALR instruction (the initial bug is back in 2018). This commit also fixes that based on the idea of Palmer Dabbelt. gas/ pr29342 * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. * testsuite/gas/riscv/dis-addr-overflow.s: New testcase. * testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise. opcodes/ pr29342 * riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32. (print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
2022-09-02RISC-V: Add address printer tests with ADDIWTsukasa OI3-0/+64
Address sequences involving ADDIW/C.ADDIW instructions require special handling to sign-extend lower 32-bits of the original result. This commit tests whether this sign-extension works. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-addiw.s: New to test the address computation with sign extension as used in ADDIW/C.ADDIW. * testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0. * testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-addiw-a.d: New test. * testsuite/gas/riscv/dis-addr-addiw-b.d: New test. * testsuite/gas/riscv/dis-addr-addiw.s: New test.
2022-08-31Add OpenBSD AArch64 GAS support.Frederic Cambus2-0/+5
* configure.tgt (aarch64*-*-openbsd*): Add target.
2022-08-30Add a testcase for PR 29494.Nick Clifton3-0/+10001
PR 29494 * testsuite/gas/arm/pr29494.s: New test source file. * testsuite/gas/arm/pr29494.d: New test driver.
2022-08-30LoongArch: Fix redefinition of "PACKAGE".liuzhensong1-1/+1
Running configure and make in binutils-gdb. $ ./configure $ make In file included from ./as.h:37, from ./config/loongarch-lex.l:21, from config/loongarch-lex-wrapper.c:20: ./config.h:206: error: “PACKAGE” redefined [-Werror] #define PACKAGE "gas" ... gas/config * loongarch-lex-wrapper.c
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI15-2/+143
Three-part patch set from Tsukasa OI to support zmmul in assembler. The 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a subset of 'M' which has multiply and divide instructions). bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'. (riscv_supported_std_z_ext): Add 'Zmmul' extension. (riscv_multi_subset_supports): Add handling for new instruction class. gas/ * testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/m-ext.s: New test. * testsuite/gas/riscv/m-ext-32.d: New test (RV32). * testsuite/gas/riscv/m-ext-64.d: New test (RV64). * testsuite/gas/riscv/zmmul-32.d: New expected output. * testsuite/gas/riscv/zmmul-64.d: Likewise. * testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure by using RV64-only instructions in RV32). * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test (RV32 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test (RV64 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise. * testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test (no Zmmul or M). * testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise. include/ * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in these testcases, so just replaced m by a. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed. opcodes/ * riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
2022-08-28PR29494 Trailing jump table on ARMAlan Modra1-6/+6
out_inc_line_addr and relax_inc_line_addr are passed INT_MAX as line_delta to flag end of section. This filters its way down to size_inc_line_addr and emit_inc_line_addr. Pass line_delta on to scale_addr_delta where it can be used to omit an unaligned opcode error. PR 29494 * dwarf2dbg.c (scale_addr_delta): Delete unnecessary forward decl. Add line_delta param. Don't print error at end of section, just round the address down. (size_inc_line_addr, emit_inc_line_addr): Adjust calls.
2022-08-25GAS: Add a return type tag to DWARF DIEs generated for function symbols.Nick Clifton6-4/+82
PR 29517 * dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant. (GAS_ABBREV_SUBPROG): New defined constant. (GAS_ABBREV_NO_TYPE): New defined constant. (out_debug_abbrev): Use the new defined constants when emitting abbreviation numbers. Generate an abbreviation for an unspecified type. (out_debug_info): Use the new defined constants when referring to abbreviations. Generate a use of the no_type abbreviation. Reference the use when generating DIEs for functions. * testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly extended output from the assembler. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
2022-08-25GAS: Allow AArch64 pseudo-ops to accept the command line separator character.Nick Clifton4-12/+30
PR 29519 * config/tc-aarch64.c (s_unreq): Use find_end_of_line(). (s_aarch64_cpu): Likewise. (s_aarch64_arch): Likewise. (s_aarch64_arch_extension): Likewise. * testsuite/gas/aarch64/pr29519.d: New test driver file. * testsuite/gas/aarch64/pr29519.s: New test source file.
2022-08-25gas: NEWS: Add the RISC-V features for 2.39Palmer Dabbelt1-0/+12
2022-08-25gas: NEWS: Add the RISC-V features for 2.38Palmer Dabbelt1-0/+11
2022-08-25gas: NEWS: Add the RISC-V features for 2.37Palmer Dabbelt1-0/+3
2022-08-25gas: NEWS: Add the RISC-V features for 2.36Palmer Dabbelt1-0/+2
2022-08-25gas: NEWS: Add the RISC-V features for 2.35Palmer Dabbelt1-0/+5
2022-08-25gas: NEWS: Add the RISC-V features for 2.31Palmer Dabbelt1-0/+2
2022-08-24gas: arm: handle multiple .directives on a single line (PR29519)Richard Earnshaw3-20/+73
There's been a long-standing bug in the arm backend where target-specific directives did not correctly handle lines with multiple statements. This patch fixes the issue for all the cases I've been able to find. It does result in a slight change in behaviour when errors are encountered: where, previously, .cpu arm6 bar would result in the error "junk at end of line, first unrecognized character is `b'", we now get "unknown cpu `arm6 bar'", which I think is slightly more helpful anyway. Similar errors are generated for other directives.
2022-08-22LoongArch: gas: add support using constant variable in instructions.tangxiaolin11-18/+352
Instructions that can load immediate support using constant variable like ".equ var, 123 li.w/d resgister, var". gas/ * config/loongarch-parse.y * config/tc-loongarch.c Add four testcases.One is a program using constant variable, one test using label is unsupported, and another two test almost instructions that can load immediate. gas/ * testsuite/gas/loongarch/li.d * testsuite/gas/loongarch/li.s * testsuite/gas/loongarch/imm_ins_label-fail.d * testsuite/gas/loongarch/imm_ins_label-fail.l * testsuite/gas/loongarch/imm_ins_label-fail.s * testsuite/gas/loongarch/imm_ins.d * testsuite/gas/loongarch/imm_ins.s * testsuite/gas/loongarch/imm_ins_32.d * testsuite/gas/loongarch/imm_ins_32.s
2022-08-18x86: move / quiesce pre-386 non-16-bit warningJan Beulich1-6/+12
Emitting this warning for every insn, including ones having actual errors, is annoying. Introduce a boolean variable to emit the warning just once on the first insn after .arch may have changed the things, and move the warning to output_insn(). (I didn't want to go as far as checking whether the .arch actually turned off the i386 bit, but doing so would be an option.)
2022-08-18x86: insert "no error" enumerator in i386_error enumerationJan Beulich1-0/+1
The value of zero would better not indicate any error, but rather hit the abort() at the top of the consuming switch().
2022-08-16i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu3-0/+14
When displaying operands, invalid opcodes may overflow operand buffer due to additional styling characters. Each style is encoded with 3 bytes. Define MAX_OPERAND_BUFFER_SIZE for operand buffer size and increase it from 100 bytes to 128 bytes to accommodate 9 sets of styles in an operand. gas/ PR binutils/29483 * testsuite/gas/i386/i386.exp: Run pr29483. * testsuite/gas/i386/pr29483.d: New file. * testsuite/gas/i386/pr29483.s: Likewise. opcodes/ PR binutils/29483 * i386-dis.c (MAX_OPERAND_BUFFER_SIZE): New. (obuf): Replace 100 with MAX_OPERAND_BUFFER_SIZE. (staging_area): Likewise. (op_out): Likewise.
2022-08-13readelf: print 0x0 as 0, and remove trailing spacesAlan Modra54-154/+153
This changes readelf output a little, removing the 0x prefix on hex output when the value is 0, except in cases where a fixed field width is shown. %#010x is not a good replacement for 0x%08x.
2022-08-11ppc/svp64: support svindex instructionDmitry Selyutin3-0/+25
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svindex https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svremap instructionDmitry Selyutin3-0/+25
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svremap https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svshape instructionDmitry Selyutin3-0/+19
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svshape https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svstep instructionsDmitry Selyutin3-0/+19
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/svstep/ https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support setvl instructionsDmitry Selyutin3-0/+24
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/setvl/ https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: introduce non-zero operand flagDmitry Selyutin1-3/+18
svstep and svshape instructions subtract 1 before encoding some of the operands. Obviously zero is not supported for these operands. Whilst PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be incremented, there is no flag which marks the fact that zero values are not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this purpose.
2022-08-11ppc/svp64: support LibreSOC architectureDmitry Selyutin1-0/+2
This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org.
2022-08-11PR29466, APP/NO_APP with .linefileAlan Modra9-4/+43
Commit 53f2b36a54b9 exposed a bug in sb_scrub_and_add_sb that could result in losing input. If scrubbing results in expansion past the holding capacity of do_scrub_chars output buffer, then do_scrub_chars stashes the extra input for the next call. That call never came because sb_scrub_and_add_sb wrongly decided it was done. Fix that by allowing sb_scrub_and_add_sb to see whether there is pending input. Also allow a little extra space so that in most cases we won't need to resize the output buffer. sb_scrub_and_add_sb also limited output to the size of the input, rather than the actual output buffer size. Fixing that resulted in a fail of gas/testsuite/macros/dot with an extra warning: "end of file not at end of a line; newline inserted". OK, so the macro in dot.s really does finish without end-of-line. Apparently the macro expansion code relied on do_scrub_chars returning early. So fix that too by adding a newline if needed in macro_expand_body. PR 29466 * app.c (do_scrub_pending): New function. * as.h: Declare it. * input-scrub.c (input_scrub_include_sb): Add extra space for two .linefile directives. * sb.c (sb_scrub_and_add_sb): Take into account pending input. Allow output to max. * macro.c (macro_expand_body): Add terminating newline. * testsuite/config/default.exp (SIZE, SIZEFLAGS): Define. * testsuite/gas/macros/app5.d, * testsuite/gas/macros/app5.s: New test. * testsuite/gas/macros/macros.exp: Run it.
2022-08-10gas/Dwarf: properly skip zero-size functionsJan Beulich1-19/+20
PR gas/29451 While out_debug_abbrev() properly skips such functions, out_debug_info() mistakenly didn't. It needs to calculate the high_pc expression ahead of time, in order to skip emitting any data for the function if the value is zero. The one case which would still leave a zero-size entry is when symbol_get_obj(symp)->size ends up evaluating to zero. I hope we can expect that to not be the case, otherwise we'd need to have a way to post-process .debug_info contents between resolving expressions and actually writing the data out to the file. Even then it wouldn't be entirely obvious in which way to alter the data.
2022-08-09Another gas manual typo correction.Stepan Nemec1-1/+1
2022-08-09Fix typos in assembler documentation.Stepan Nemec1-10/+11
2022-08-09x86-64: adjust MOVQ to/from SReg attributesJan Beulich2-6/+20
It is unclear to me why the corresponding MOV (no Q suffix) can be issued without REX.W, but MOVQ has to have that prefix (bit). Add NoRex64 and in exchange drop Size64.
2022-08-09x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich6-0/+9
While the x/y/z suffix isn't necessary to use in this case, it is still odd that these forms don't support broadcast (unlike their AVX512F / AVX512DQ counterparts). The lack thereof can e.g. make macro-ized programming more difficult.
2022-08-08Mach-O: i18n enablement on some error messages.Tsukasa OI2-2/+7
* config/obj-macho.c (obj_mach_o_get_section_names): Wrap two string literals within with gettext macro.
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