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2023-12-29x86: Append "#pass" to APX testsH.J. Lu5-0/+5
Append "#pass" to APX tests for targets which pad text sections with NOPs. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Append "#pass". * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Likewise.
2023-12-29x86: Don't use .insn with '/'H.J. Lu1-3/+3
'/' starts a comment for some targets. Use .byte instead of .insn with '/'. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Use .byte instead of .insn with '/'.
2023-12-29Fix x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu1-0/+1
commit 3d5a60de52556f6a53d71d7e607c6696450ae3e4 Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Jun 8 10:01:03 2023 -0700 x86-64: Add R_X86_64_CODE_4_GOTPCRELX added a new field, fx_tcbit3, to fix. But it didn't initialize it. Fix it by clearing it in fix_new_internal. * wrtite.c (fix_new_internal): Clear fx_tcbit3.
2023-12-29LoongArch: gas: Add support for tls le relax.changjiachen5-0/+85
Add tls le relax related relocs support and testsuites in gas. The main test is three new relocation items, R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R, R_LARCH_TLS_LE_LO12_R can be generated properly and tls le insn format check. gas/ChangeLog: * config/tc-loongarch.c: (loongarch_args_parser_can_match_arg_helper): Add support for relax. * gas/testsuite/gas/loongarch/reloc.d: Likewise. * gas/testsuite/gas/loongarch/reloc.s: Likewise. * gas/testsuite/gas/loongarch/loongarch.exp: Likewise. * gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test.
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma2-0/+24
In order to make it easier to complete the compiler's support for the XTheadVector extension and to be as compatible as possible with the programming model of the 'V' extension ([1]), we consider adding a few pseudo instructions ([2]). th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0 th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs Ref: [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html [2] https://github.com/T-head-Semi/thead-extension-spec/pull/40 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for new pseudoinstructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. opcodes/ChangeLog: * riscv-opc.c: Add new pseudoinstructions.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu6-0/+87
For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu8-8/+60
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-12-28gas: Mention initial support for Intel APX in NEWSH.J. Lu1-0/+2
2023-12-28Support APX JMPABS for disassemblerHu, Lin16-0/+87
gas/ChangeLog: * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto. opcodes/ChangeLog: * i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs. (print_insn): Add #UD exception for jmpabs. (dis386): Modify a1 unit for support jmpabs. * i386-mnem.h: Regenerated. * i386-opc.tbl: New insns. * i386-tbl.h: Regenerated.
2023-12-28Support APX NDD optimized encoding.Hu, Lin14-0/+362
This patch aims to optimize: add %r16, %r15, %r15 -> add %r16, %r15 gas/ChangeLog: * config/tc-i386.c (check_Rex_required): New function. (can_convert_NDD_to_legacy): Ditto. (match_template): If we can optimzie APX NDD insns, so rematch template. * testsuite/gas/i386/x86-64.exp: Add test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto.
2023-12-28Support APX pushp/poppCui, Lili7-1/+53
gas/ChangeLog: * config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires rex2.w == 1." * testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto. opcodes/ChangeLog: * i386-dis.c (putop): print pushp and popp. * i386-opc.tbl: Added new insns. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-tbl.h: Regenerated.
2023-12-28Support APX Push2/Pop2Mo, Zewei12-0/+227
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28Support APX NDDkonglin18-17/+452
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28Add tests for APX GPR32 with extend evex prefixCui, Lili12-0/+1498
gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't support gpr32. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add new test. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili3-14/+75
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili17-160/+577
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-25LoongArch: Add testsuit for DESC and tls transition and tls relaxation.Lulu Cai10-0/+214
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang5-280/+296
The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-1/+13
The normal DESC instruction sequence is: pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL add.d $a0,$a0,$tp
2023-12-22nios2: fix .text/.data interaction with .previousJan Beulich1-2/+2
Just like obj_elf_section() is called for .section, obj_elf_{text,data}() need calling for .text/.data.
2023-12-22hppa/ELF: fix .text/.data interaction with .previousJan Beulich1-4/+15
For some ELF targets .text/.data are overridden. In that case obj_elf_{text,data}() need calling, just like .code vectors to that function for the remaining ELF targets. While there also hand on the function arguments, even if right now they're meaningless. This matches what other targets' code does.
2023-12-22RISC-V: drop .bss overrideJan Beulich2-14/+0
It doesn't look to be a good idea to override the custom handler that ELF has; afaict doing so broke .previous, and a sub-section specifier wasn't accepted either.
2023-12-22x86-64: refuse "high" 8-bit regs with .insn and VEX/XOP/EVEX encodingsJan Beulich1-0/+10
Much like REX, those encodings - if permitting 8-bit regs at all, i.e. only starting with APX - permit use of "new" 8-bit registers only. %ah, %ch, %dh, and %bh cannot be encoded and hence should be rejected. Permit their use outside of 64-bit code though, as "new" registers simply don't exist there.
2023-12-22x86: properly respect rex/{rex}Jan Beulich6-62/+98
This addresses two issues: For one, a user specified "rex" did not cause the diagnostic to trigger when there was no other need for a REX prefix; instead, another than the specified insn+operands was encoded. And then (which is what this started from) .insn didn't respect {rex} (and was otherwise similarly flawed as ordinary insns). The latter requires splitting out code from md_assemble(), for it to become re-usable. Besides the addition to address the first issue, that code then also needs generalizing to account for immediate operands, as with .insn we can't make assumptions anymore on all respective templates having at most two operands (we still can build upon there being at most two non-immediate operands, though). While moving the code also simplify the first if(), by folding redundant checks. In the new testcase also test a few more things which afaics weren't tested till now.
2023-12-22LoongArch: Add support for the third expression of .align for R_LARCH_ALIGNmengqinggang4-27/+47
If the symbol index is not zero, the addend is used to represent the first and the third expressions of the .align. The lowest 8 bits are used to represent the first expression. Other bits are used to represent the third expression. The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405. The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405.
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus2-0/+4
Suffix the instruction description of conditional branch extended mnemonics with their condition (e.g. "on A high"). This complements the optional printing of instruction descriptions as comments in the disassembly. Due to the added text the maximum description length is increased from 80 to 128 characters (including the trailing '\0' character). opcodes/ * s390-mkopc.c: Add suffix to conditional branch extended mnemonic instruction descriptions. gas/ * testsuite/gas/s390/zarch-insndesc.s: Add test cases for printing of suffixed instruction description of conditional branch extended mnemonics. * testsuite/gas/s390/zarch-insndesc.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus3-0/+28
Print instruction description as comment in disassembly with s390 architecture specific option "insndesc": - For objdump it can be enabled with option "-M insndesc" - In gdb it can be enabled with "set disassembler-options insndesc" Since comments are not column aligned the output can enhanced for readability by postprocessing using a filter such as "expand": ... | expand -t 8,16,24,32,40,80 Or when using in combination with objdump option --visualize-jumps: ... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80 Note that the instruction descriptions add about 128 KB to s390-opc.o: s390-opc.o without instruction descriptions: 216368 bytes s390-opc.o with instruction descriptions : 348432 bytes binutils/ * NEWS: Mention new s390-specific disassembler option "insndesc". include/ * opcode/s390.h (struct s390_opcode): Add field to hold instruction description. opcodes/ * s390-mkopc.c: Copy instruction description from s390-opc.txt into generated operation code table s390-opc.tab. * s390-opc.c (s390_opformats): Provide NULL as description in .insn pseudo-mnemonics opcode table. * s390-dis.c: Add s390-specific disassembler option "insndesc" and optionally print the instruction description as comment in the disassembly when it is specified. gas/ * testsuite/gas/s390/s390.exp: Add new test disassembly test case "zarch-insndesc". * testsuite/gas/s390/zarch-insndesc.s: New test case for s390- specific disassembler option "insndesc". * testsuite/gas/s390/zarch-insndesc.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo6-0/+20
This patch add support for FEAT_ITE "Instrumentation Extension" adding the "trcit" instruction. This is enabled by the +ite march flag.
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo3-2/+13
This patch add support for FEAT_ECBHB "Exploitative control using branch history information" adding the "clrbhb" instruction. AFAIU the same alias was originally added as "clearbhb" before the architecture was finalized (Mandatory v8.9-a/v9.4-a; Optional v8.0-a+/v9.0-a+).
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo6-0/+25
This patch add supports for FEAT_SPECRES2 "Enhanced speculation restriction instructions" adding the "cosp" instruction. This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+. It is enabled by the +predres2 march flag.
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang3-231/+30
Since AVX10.1/256 will also allow 64 bit mask register, we will remove the restriction for size of the mask register in AVX10. gas/ChangeLog: * config/tc-i386.c (VSZ128, VSZ256, VSZ512): New. (VEX_check_encoding): Remove opcode_modifier check for vsz. * testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask registers since they are not needed. * testsuite/gas/i386/avx10-vsz.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Remove Vsz. * i386-opc.h: Ditto. * i386-opc.tbl: Remove kvsz. * i386-tbl.h: Regenerated.
2023-12-18LoongArch: Add call36 and tail36 pseudo instructions for medium code modelmengqinggang2-2/+10
For tail36, it is necessary to explicitly indicate the temporary register. Therefore, the compiler and users will know that the tail will use a register. call36 func pcalau18i $ra, %call36(func) jirl $ra, $ra, 0; tail36 $t0, func pcalau18i $t0, %call36(func) jirl $zero, $t0, 0;
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang3-1/+26
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
2023-12-15arm: reformat -march option section in gas documentationMatthieu Longo1-110/+129
Hi, This patch contains a reformatting of -march option section in gas documentation. For instance (see https://sourceware.org/binutils/docs-2.41/as.html#ARM-Options), before all the options were on one line: For armv8-a: +crc: Enables CRC32 Extension. +simd: Enables VFP and NEON for Armv8-A. +crypto: Enables Cryptography Extensions for Armv8-A, implies +simd. +sb: Enables Speculation Barrier Instruction for Armv8-A. +predres: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. +nofp: Disables all FPU, NEON and Cryptography Extensions. +nocrypto: Disables Cryptography Extensions. Now, the readability is improved thanks to the itemization of the options: For armv8-a: +crc: Enables CRC32 Extension. +simd: Enables VFP and NEON for Armv8-A. +crypto: Enables Cryptography Extensions for Armv8-A, implies +simd. +sb: Enables Speculation Barrier Instruction for Armv8-A. +predres: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. +nofp: Disables all FPU, NEON and Cryptography Extensions. +nocrypto: Disables Cryptography Extensions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo4-0/+11
Hi, This patch adds support for the Cortex-X3 CPU to binutils. Gas regression testing for aarch64-none-linux-gnu target and found no regressions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
2023-12-15arm: document -march=armv9.[123]-a binutils optionsMatthieu Longo1-0/+3
2023-12-15x86: last-insn recording should be per-subsectionJan Beulich5-0/+77
Otherwise intermediate subsection switches result in inconsistent behavior. Leverage ELF's section change hook to switch state as necessary, limiting overhead to the bare minimum when subsections aren't used.
2023-12-15ELF: reliably invoke md_elf_section_change_hook()Jan Beulich1-11/+18
... after any (sub)section change. While certain existing target hooks only look at now_seg, for a few others it looks as if failing to do so could have caused anomalies if sub-sections were used. In any event a subsequent x86 change is going to require the sub-section to be properly in place at the time the hook is invoked. This primarily means for obj_elf_section() to pass the new subsection into change_section(), for it to be set right away (ahead of invoking the hook). Also adjust obj_elf_ident() to invoke the hook after all section changes. (Note that obj_elf_version(), which also changes sections and then changes them back, has no hook invocation at all so far, so none are added. Presumably there is a reason for this difference in behavior.)
2023-12-15ELF: drop "push" parameter from obj_elf_change_section()Jan Beulich9-24/+34
No caller outside of obj-elf.c cares about the parameter - drop it by introducing an obj-elf.c-internal wrapper. While adding the new function parameter, take the opportunity and change the adjacent boolean one to "bool".
2023-12-15x86: don't needlessly override .bssJan Beulich1-8/+5
ELF, COFF, and Mach-O all have custom handlers for .bss. Don't override those; install a handler only for a.out.
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-4/+4
This reverts commit 1f865bae65db9588f6994c02a92355bfb4e3d955. The specification is going to by updated in a way rendering this change wrong.
2023-12-15x86: fold assembly dialect attributesJan Beulich2-5/+5
Now that ATTSyntax and ATTMnemonic aren't use in combination anymore, fold them and IntelSyntax into a single, enum-like attribute. Note that this shrinks i386_opcode_modifier back to 2 32-bit words (albeit that's not for long, seeing in-flight additions for APX).
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich8-54/+30
As noted in the context of d53e6b98a259 ("x86/Intel: correct disassembly of fsub*/fdiv*") there's no such thing as Intel syntax without Intel mnemonics. Enforce this on the assembler side, and disentangle command line option handling on the disassembler side accordingly. As a result in the opcode table specifying ATTMnemonic|ATTSyntax becomes redundant with just ATTMnemonic. Drop the now meaningless ATTSyntax and remove the then no longer accessible templates.
2023-12-15Arm64: fix build for certain gcc versionsJan Beulich1-3/+3
Some complain (by default) about isalpha shadowing ctype.h's isalpha(). Some also complain about signed/unsigned comparison a few lines later.
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma2-3/+3
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the XTheadFmv extension in T-Head specific is incorrect, and it also has some impact on the implementation of the binutils, so this patch corrects this. For details see: https://github.com/T-head-Semi/thead-extension-spec/pull/34 gas/ChangeLog: * testsuite/gas/riscv/x-thead-fmv.d: Correct test. * testsuite/gas/riscv/x-thead-fmv.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding. (MASK_TH_FMV_HW_X): Likewise. (MATCH_TH_FMV_X_HW): Likewise. (MASK_TH_FMV_X_HW): Likewise. opcodes/ChangeLog: * riscv-opc.c: Correct operands.
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili13-128/+128
Make const_1_mode print $1 in AT&T syntax, otherwise there will be correctness issues when it is extended to support APX NDD, gas/ChangeLog: * testsuite/gas/i386/intel.d: Adjust testcase. * testsuite/gas/i386/lfence-load.d: Ditto. * testsuite/gas/i386/noreg16-data32.d: Ditto. * testsuite/gas/i386/noreg16.d: Ditto. * testsuite/gas/i386/noreg32-data16.d: Ditto. * testsuite/gas/i386/noreg32.d: Ditto. * testsuite/gas/i386/noreg64-data16.d: Ditto. * testsuite/gas/i386/noreg64-rex64.d: Ditto. * testsuite/gas/i386/noreg64.d: Ditto. * testsuite/gas/i386/opcode-suffix.d: Ditto. * testsuite/gas/i386/opcode.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.d: Ditto. * testsuite/gas/i386/x86-64-opcode.d: Ditto. opcodes/ChangeLog: * i386-dis.c (OP_I): Make const_1_mode print $1 in AT&T syntax.
2023-12-13Clean base_reg and assign correct values to regs for input_output_operand (%dx).Cui, Lili1-0/+2
For special processing of input and output operands (%dx), the state of some variables needs to be cleaned. gas/ChangeLog: * config/tc-i386.c (i386_att_operand): Assign values to regs and clean i.base_reg for input output operand (%dx).
2023-12-12Fix whitespace snafu in tc-riscv.cNick Clifton1-5/+5
2023-12-12RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instructionRui Ueyama3-0/+26
Some psABIs define a relaxation to turn a GOT load into a PC-relative address materialization. For example, the AArch64's psABI allows adrp+ldr to be rewritten to nop+adr to eliminate the memory load. This patch is part of the effort to make such optimization possible for RISC-V. For RISC-V, we use the la assembly pseudo instruction to load a symbol address from the GOT. The pseudo instruction is expanded to auipc+ld. If the address loaded by the instruction pair is actually a PC-relative link-time constant, we want the linker to rewrite the instruction pair with auipc+addi. We can't rewrite all existing auipc+ld pairs with auipc+addi in the linker because there might be code that jumps to the middle of the instruction pair. That should be extremely rare, if ever exists, but you can at least in theory write a program in assembly that jumps to the ld instruction of the instruction pair. We need a marker to identify that an auipc+ld can be safely relaxed (i.e. they are emitted for la). This patch is to annotate R_RISCV_GOT_HI20 with R_RISCV_RELAX only when the relocation is emitted for the la pseudo instruction. The linker will use it as a signal that the instruction pair can be safely relaxed. Proposal to the RISC-V psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/397 gas/ * config/tc-riscv.c (source_macro): New static int variable. The identifier of the assembler macro we are expanding, if any. (append_insn): Updated source_macro to tc_fix_data, to record which macro expands, if any. (macro): Record which macro expands into source_macro. Reset source_macro to -1 at the end. (md_apply_fix): Apply R_RISCV_RELAX if pcrel_got_hi is expanded from macro LA/LGA. * config/tc-riscv.h (struct riscv_fix, TC_FIX_TYPE, TC_INIT_FIX_DATA): Defined to record source_macro into fixups for riscv target. * testsuite/gas/riscv/la-variants.d: Updated.
2023-12-12RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'Lifang Xia5-0/+187
In the scenario of generating .ko files, the kernel does not relax the .ko files. However, due to the large amount of relax and local relocation information, this increases the size of the .ko files. In this patch, it will finish the fixup of the local relocations while with `-mno-relax' option. This can reduce the size of the relocation table. The implemntation is based on the code from bfd/elfnn-riscv.c. We probably can move the code to bfd/elfxx-riscv.c, so that can reduce duplicate code, just like what we did for the architecture parser. Besides, maybe not only pcrel_hi/lo12 relocation with local symbols can be resolved at assembler time. Other pc-relative relocation, like branch, may also be able to perform related optimizations. Passed the gcc/binutils regressions of riscv-gnu-toolchain. gas/ * config/tc-riscv.c (riscv_pcrel_hi_reloc): New structure. Record all PC-relative high-part relocation that we have encountered to help us resolve the corresponding low-part relocation later. (riscv_pcrel_hi_fixup_hash): The hash table to record pcrel_hi fixups. (riscv_pcrel_fixup_hash): New function. Likewise. (riscv_pcrel_fixup_eq): Likewise. (riscv_record_pcrel_fixup): Likewise. (md_begin): Init pcrel_hi hash table. (md_apply_fix): For PCREL_HI20 relocation, do fixup and record the pcrel_hi relocs, mark as done while with `-mno-relax'. For PCREL_LO12_I/S relocation, do fixup and mark as done while with `-mno-relax'. (riscv_md_end): New function. Free pcrel_hi hash table. * config/tc-riscv.h (md_end): Define md_end with riscv_md_end. gas/ * testsuite/gas/riscv/fixup-local*: New tests.
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