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AgeCommit message (Expand)AuthorFilesLines
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei6-0/+342
2024-04-09Support {evex} pseudo prefix for decode evex promoted insns without egpr32.Hu, Lin110-0/+1426
2024-04-07Support APX NFCui, Lili8-6/+4179
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu3-18/+0
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu3-0/+18
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili8-162/+7
2024-04-01LoongArch: gas: Ignore .align if it is at the start of a sectionmengqinggang2-0/+19
2024-03-31BFD: Fix the bug of R_LARCH_AGLIN caused by discard sectionmengqinggang1-3/+3
2024-03-28gas: gcfg: fix handling of non-local direct jmps in gcfgIndu Bhagat4-0/+76
2024-03-28x86/SSE2AVX: respect prefixesJan Beulich2-0/+18
2024-03-28gas: sanitize FB- and dollar-label usesJan Beulich1-10/+10
2024-03-28RISC-V: Removed privileged spec 1.9.1 support in assembler.Nelson Chu15-2871/+16
2024-03-22x86: fix Solaris testsuite failuresJan Beulich1-1/+1
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha22-0/+1118
2024-03-19LoongArch: Add relaxation for R_LARCH_CALL36mengqinggang4-146/+157
2024-03-18aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructionsYury Khrustalev9-2/+311
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev7-0/+183
2024-03-18Arm64: check matching operands for predicated B16B16 insnsJan Beulich6-36/+62
2024-03-18Arm64: correct B16B16 indexed bf{mla,mls,mul}Jan Beulich1-18/+18
2024-03-18RISC-V: Tidy smstateen and ssstateen testcases.Nelson Chu4-57/+6
2024-03-15x86/APX: legacy promoted insns can't access %xmm16-%xmm31Jan Beulich8-139/+112
2024-03-13RISC-V: Add -march=help for gasHau Hsu2-0/+120
2024-03-12LoongArch: Scan all illegal operand instructions without interruptionLulu Cai7-2/+263
2024-03-12LoongArch: Fix gas and ld test casesLulu Cai2-0/+6
2024-03-11x86: KeyLocker insn interaction with -msse-check / .sse_checkJan Beulich5-2/+47
2024-03-08RISC-V: Support Zabha extension.Jiawei3-0/+235
2024-03-06LoongArch: Fix some test cases for TLS transition and relaxLulu Cai10-46/+41
2024-03-05LoongArch: Add gas testsuit for LA32 relocationsLulu Cai2-0/+136
2024-03-05LoongArch: Add gas testsuit for LA64 relocationsLulu Cai2-0/+253
2024-03-05LoongArch: Add gas testsuit for LA32 int/float instructionsLulu Cai4-0/+609
2024-03-05LoongArch: Add gas testsuit for LA64 int/float instructionsLulu Cai4-0/+1192
2024-03-05LoongArch: Add gas testsuit for lsx/lasx instructionsLulu Cai4-0/+2938
2024-03-05LoongArch: Add gas testsuit for lbt/lvz instructionsLulu Cai4-0/+382
2024-03-05LoongArch: Add gas testsuit for alias instructionsLulu Cai4-0/+60
2024-03-01s390: Be more verbose about missing operand typeJens Remus2-17/+17
2024-03-01s390: Provide operand number in assembler warning and error messagesJens Remus5-132/+132
2024-03-01s390: Allow to explicitly omit base register operand in assemblyJens Remus8-162/+109
2024-03-01s390: Print base register 0 as "0" in disassemblyJens Remus2-35/+35
2024-03-01s390: Warn when register name type does not match operandJens Remus9-22/+70
2024-03-01s390: Add test case for disassembler option warn-areg-zeroJens Remus3-0/+182
2024-03-01s390: Add test cases for base/index register 0Jens Remus5-0/+394
2024-03-01s390: Assemble processor specific test cases for their processorJens Remus1-2/+2
2024-03-01s390: Correct setting of highgprs flag in ELF outputJens Remus9-0/+135
2024-03-01s390: Do not erroneously use base operand value for length operandJens Remus5-0/+92
2024-03-01s390: Lower severity of assembler syntax errors from fatal to errorJens Remus1-1/+1
2024-03-01x86/APX: honor -mevexwig= for byte-size insnsJan Beulich2-0/+162
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich2-0/+48
2024-03-01x86/APX: correct .insn opcode space determination when REX2 is neededJan Beulich3-0/+64
2024-03-01x86/APX: respect {vex}/{vex3}Jan Beulich2-94/+111
2024-02-29aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions.Srinath Parvathaneni3-49/+49
generated by cgit v1.1 at 2024-08-16 09:18:47 +0000