aboutsummaryrefslogtreecommitdiff
path: root/gas/doc
AgeCommit message (Collapse)AuthorFilesLines
2025-01-08Support Intel AMX-FP8Liwei Xu1-1/+2
In this patch, we will support AMX-FP8 feature. Since in the foreseeable future, only AMX-MOVRS will also use VEX_MAP5, we currently will not add a table of 256 entries and handle just like MAP7. gas/ChangeLog: * config/tc-i386.c: Add amx_fp8. * doc/c-i386.texi: Document .amx_fp8. * testsuite/gas/i386/x86-64.exp: Run AMX-FP8 tests. * testsuite/gas/i386/x86-64-amx-fp8-bad.d: New test. * testsuite/gas/i386/x86-64-amx-fp8-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0): New. (X86_64_VEX_MAP5_FD): Ditto. (VEX_LEN_MAP5_FD_X86_64): Ditto. (VEX_W_MAP5_FD_X86_64_L_0):Ditto. (prefix_table): Add PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0. (x86_64_table): Add X86_64_VEX_MAP5_FD. (vex_len_table): Add VEX_LEN_MAP5_FD_X86_64. (vex_w_table): Add VEX_W_MAP5_FD_X86_64_L_0. * i386-gen.c: Add CPU_AMX_FP8_FLAGS and CPU_ANY_AMX_FP8_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: Add cpuamx_fp8. * i386-opc.tbl: Add AMX_FP8 instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-02gas: Revert PR 32391 related commits to fix 3 regressionsH.J. Lu1-59/+1
9f2e3c21f65 Fix the handling or arguments and macro pseudo-variables inside nested assembler macros. introduced 3 regressions of PR gas/32484, PR gas/32486 and PR gas/32487. Revert all PR 32391 related commits and add tests for PR gas/32484, PR gas/32486, PR gas/32487. PR gas/32484 PR gas/32486 PR gas/32487 * testsuite/gas/macros/macros.exp: Run nesting1, nesting2 and nesting3. * testsuite/gas/macros/nesting1.d: New file. * testsuite/gas/macros/nesting1.s: Likewise. * testsuite/gas/macros/nesting2.d: Likewise. * testsuite/gas/macros/nesting2.s: Likewise. * testsuite/gas/macros/nesting3.d: Likewise. * testsuite/gas/macros/nesting3.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-01-02Support Intel AMX-TF32Haochen Jiang1-1/+3
In this patch, we will support AMX-TF32. It is a simple ISA comparing to the previous ones, so there is no special handling. gas/ChangeLog: * config/tc-i386.c: Add amx_tf32. * doc/c-i386.texi: Document .amx_tf32. * testsuite/gas/i386/x86-64.exp: Run AMX-TF32 tests. * testsuite/gas/i386/x86-64-amx-tf32-bad.d: New test. * testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F3848_X86_64_W_0_L_0): New. (X86_64_VEX_0F3848): Ditto. (VEX_LEN_0F3848_X86_64_W_0): Ditto. (VEX_W_0F3848_X86_64): Ditto. (prefix_table): Add PREFIX_VEX_0F3848_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F3848. (vex_len_table): Add VEX_LEN_0F3848_X86_64_W_0. (vex_w_table): Add VEX_W_0F3848_X86_64. * i386-gen.c (isa_dependencies): Add AMX_TF32. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TF32): New. (i386_cpu_flags): Add cpuamx_tf32. * i386-opc.tbl: Add AMX-TF32 instructions. * i386-tbl.h: Regenerated.
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang1-1/+2
In this patch, we will support AMX-TRANSPOSE. Since AMX-TRANSPOSE will be used with other CPUIDs very often, we put it into CPU_FLAGS_COMMON. To implement TMM pair, we reused ImplicitGroup and adjust the condition in process_operands for the instructions. APX_F extension is also handled in this patch, where it extends T2RPNTLVW[Z0,Z1][,T1] to EVEX.128.NP/66.0F38.W0 6E/6F !(11):rrr:100 with NF=0. Also, TTDPFP16PS should base on AMX_FP16, not AMX_BF16 in ISE055. It would be fixed in ISE056. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_transpose. (_is_cpu): Ditto. (process_operands): Adjust the condition for AMX-TRANSPOSE. * doc/c-i386.texi: Document .amx_transpose. * testsuite/gas/i386/x86-64.exp: Run AMX-TRANSPOSE tests. * testsuite/gas/i386/x86-64-amx-transpose-bad.d: New test. * testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_VEX_0F386E_X86_64_W_0): New. (MOD_VEX_0F386F_X86_64_W_0): Ditto. (PREFIX_VEX_0F385F_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386B_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0): Ditto. (PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0): Ditto. (X86_64_VEX_0F385F): Ditto. (X86_64_VEX_0F386B): Ditto. (X86_64_VEX_0F386E): Ditto. (X86_64_VEX_0F386F): Ditto. (VEX_LEN_0F385F_X86_64_W_0): Ditto. (VEX_LEN_0F386B_X86_64_W_0): Ditto. (VEX_LEN_0F386E_X86_64_W_0_M_0): Ditto. (VEX_LEN_0F386F_X86_64_W_0_M_0): Ditto. (VEX_W_0F385F_X86_64): Ditto. (VEX_W_0F386B_X86_64): Ditto. (VEX_W_0F386E_X86_64): Ditto. (VEX_W_0F386F_X86_64): Ditto. (mod_table): Add MOD_VEX_0F386E_X86_64_W_0, MOD_VEX_0F386F_X86_64_W_0. (prefix_table): Add PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0, PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0. Add new instructions for PREFIX_VEX_0F386C_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F385F, X86_64_VEX_0F386B, X86_64_VEX_0F386E, X86_64_VEX_0F386F. (vex_len_table): Add VEX_LEN_0F385F_X86_64_W_0, VEX_LEN_0F386B_X86_64_W_0, VEX_LEN_0F386E_X86_64_W_0_M_0, VEX_LEN_0F386F_X86_64_W_0_M_0. (vex_w_table): Add VEX_W_0F385F_X86_64, VEX_W_0F386B_X86_64, VEX_W_0F386E_X86_64, VEX_W_0F386F_X86_64. * i386-gen.c (cpu_flag_init): Add AMX_TRANSPOSE. (cpu_flags): Add CpuAMX_TRANSPOSE. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TRANSPOSE): New. (i386_cpu): Add cpuamx_transpose. * i386-opc.tbl: Add AMX-TRANSPOSE instructions. * i386-tbl.h: Regenerated. Co-authored-by: Hu, Lin1 <lin1.hu@intel.com>
2025-01-01Update year range in copyright notice of binutils filesAlan Modra64-66/+66
2024-12-19Fix the handling or arguments and macro pseudo-variables inside nested ↵Nick Clifton1-1/+59
assembler macros. PR 32391
2024-12-17gas: add new command line options to control diagnostic informational messagesMatthieu Longo1-0/+34
gas currently emits informational messages for context information along warnings. In the context of system register tests in AArch64 backend, these messages pollute the tests when checking for error message patterns in stderr output. This patch aims at providing two new flags while preserving the existing behavior if none of the options is provided. * --info, similar to the existing --warn flag to enable diagnostic informational messages (default behavior). * --no-info, similar to the existing --no-warn flag to disable diagnostic informational messages. It also adds the flags to the existing documentation, and command manual.
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore4-300/+0
The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
2024-11-19Support x86 Intel MSR_IMMHu, Lin11-1/+2
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
2024-11-18ELF: SHF_STRINGS isn't really tied to SHF_MERGEJan Beulich1-9/+10
It's not overly useful without it, but the spec doesn't name any dependency between the two. People may want to use it for purely informational purposes, for example. Adjust, in particular, entity size processing to be engaged if either flag is set, as mandated by the spec.
2024-10-31gas/doc/riscv: Fixed misaligned instruction tableNelson Chu1-42/+42
gas/ * doc/c-riscv.texi: Fixed misaligned instruction table.
2024-10-29gas: constify md_{short,long}opts and md_longopts_sizeJan Beulich1-1/+1
First of all make the declarations globally visible, such that producer and consumer actually share them. For the latter two simply add const (as PPC already had it,), while for the former achieve the effect by converting to an array: There's no need for the extra level of indirection.
2024-10-29RISC-V: Update the doc to match ISA manualKito Cheng1-36/+36
ISA manual use funct* rather than func*[1] (e.g. funct7 rather than func7), and I realized that may something I typo at beginning when I write the patch for `.insn` support...:P [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc1-2/+4
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-10s390: Add arch15 instructionsAndreas Krebbel2-4/+5
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-09-21x86: Add tls check in gasCui, Lili1-0/+10
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-09s390: Document syntax to omit base register operandJens Remus1-2/+3
Document the s390-specific assembler syntax introduced by commit aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") to omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). While at it document the alternative syntax to omit the index register operand X in D(X,B) by coding D(,B) instead of D(B). gas/ * doc/c-s390.texi (s390 Operands): Document syntax to omit base register operand. Fixes: aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang1-1/+5
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-09RISC-V: PR32014, .option directives shuoldn't affect elf attribute.Nelson Chu1-1/+6
The .option arch/rvc/norvc/push/pop directives can only take effect for a small/large specific code region, so they are not file-level architecture setting. They should only affect the mapping symbols only rather than the file-level elf architecture attribute. Otherwise, the elf architecture attribute will appear to missing some extensions when -flto merges files with different .option architecture settings. gas/ PR 32014 * config/tc-riscv.c (file_arch_str): New const char *, rather than the arch_str in the riscv_rps_as.subset_list, it's file-level so only be affected by .attribute arch directive. (riscv_reset_subsets_list_arch_str): Renamed to riscv_set_arch_str, and also can handle both file_arch_str and arch_str in subset_list, just give the pointer address as the input. (riscv_set_arch): Called by -march and .attribute arch, so set both file_arch_str and arch_str in subset_list. (s_riscv_option): Updated .option arch/rvc/norvc/push/pop that only set the arch_str in subset_list. (riscv_write_out_attrs): Output elf architecture attribute according to file_arch_str. Freed file_arch_str. * doc/c-riscv.texi: Added destrbution that .option directives shouldn't affect the elf attribute settings. * testsuite/gas/riscv/option-arch.s: From option-arch-01/02/03 merged. * testsuite/gas/riscv/option-arch-dis.d: Likewise, for dis-assembler. * testsuite/gas/riscv/option-arch-attr.d: Likewise, to check readelf -A.
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett1-6/+11
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
2024-07-31gas/doc: adjust an @xrefJan Beulich1-1/+1
Old doc tools warn about there not being a . or , following; satisfy those tools by shortening the line and adding a full stop.
2024-07-19gas: consistently drop trailing whitespace when scrubbingJan Beulich1-3/+3
From especially the checks for the two separator forms it appears to follow that the construct being touched is about trailing whitespace. In such a case, considering that for many targets ordinary and line comment chars overlap, take into account that line comment chars override ordinary ones in lex[] (logic elsewhere in do_scrub_chars() actually depends on that ordering, and also accounts for this overriding). Plus of course IS_NEWLINE() would better also be consulted. Note also that the DOUBLESLASH_LINE_COMMENTS change should generally have no effect just yet; it's a prereq for a later change but better fits here. Leave respective comments as well, and update documentation to correct which comment form is actually replaced by a single blank (i.e. neither the ones starting with what {,tc_}comment_chars[] has nor the ones starting with what line_comment_chars[] has).
2024-07-19MIPS/GAS: Handle --trap command-line option dynamicallyMaciej W. Rozycki1-4/+6
We have an ISA check for the '--trap' command-line option that reports its incompatibility with the MIPS I architecture. It doesn't prevent trap instructions from being enabled though, so when attempt is made to emit one in an expansion of one of the division or multiplication macros an assertion failure triggers: .../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages: .../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1 .../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero .../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064. Please report this bug. The same assertion failure triggers without an earlier error message when the initial ISA is compatible with the '--trap', however at the time an attempt is made to emit a trap instruction from a division or multiplication macro the ISA has been changed by a '.set' pseudo-op to an incompatible one. With the way the situations are mishandled it seems unlikely that anyone relies on the current semantics and a sane approach is to decide on the fly according to the currently selected ISA as to whether to emit trap or breakpoint instructions in the case where '--trap' has been used. Change our code to do so then and clarify that in the manual, which is not explicit about how '--trap' is handled with a changing ISA. Mention the change in NEWS too since it's a applies to a user option.
2024-07-18gas: minor reformatting in command line help and docMatthieu Longo1-12/+15
- help message: add a comma between the short and long option - as doc: - brief summary of how to invoke gas: separate [-w] [-x] on a new line as those two options have nothing to do with the warning options. - reordering of the warning options to have the same order as the listing. - no-warn option description: change an "and" to a "or", as it is either the short or long option to use, but not both at the same time. - remove trailing whitespaces.
2024-07-12aarch64: disable feature b16b16Matthieu Longo1-2/+2
Feature b16b16 is currently incomplete and requires re-work. Disable the command line option for b16b16, and mark the associated tests as XFAIL.
2024-07-11base64: Add support for targets with byte size > octet size.Nick Clifton1-1/+6
PR 31964
2024-07-10Add support for a .base64 pseudo-op to gasNick Clifton1-0/+14
PR 31964
2024-07-03gas/doc/riscv: Fixed typo of `.insn cj' formatNelson Chu1-1/+1
gas/ * doc/c-riscv.texi: Fixed typo of `.insn cj' format.
2024-07-03gas/doc/riscv: Fixed syntax of `.option arch' when reseting whole architectureNelson Chu1-2/+2
gas/ * doc/c-riscv.texi: Fixed syntax of `.option arc'h when reseting whole architecture. Don't need the `=' before ISA.
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas1-1/+2
The new -march=armv9.5-a flag enables access to the mandatory cpa, lut and faminmax extensions. Existing test cases for features are extended to verify they work without additional flags.
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti1-0/+4
This includes: - FEAT_SME_F8F32 (+sme-f8f32) - FEAT_SME_F8F16 (+sme-f8f16) The FP16 addition/subtraction instructions originally added by FEAT_SME_F16F16 haven't been added to Binutils yet. They are also required to be enabled if FEAT_SME_F8F16 is present, so they are included in this patch.
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti1-0/+12
This includes all the instructions under the following features: - FEAT_FP8FMA (+fp8fma) - FEAT_FP8DOT4 (+fp8dot4) - FEAT_FP8DOT2 (+fp8dot2) - FEAT_SSVE_FP8FMA (+ssve-fp8fma) - FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4) - FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-0/+2
Introduces instructions for the SME2 lutv2 extension for AArch64. They are documented in the following document: * ARM DDI0602 For both luti4 instructions, we introduced an operand called SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list for parsing but modified that function so that it can accept operands without qualifiers and rejects instructions that have operands with qualifiers but are not supposed to have operands with qualifiers. For disassembly, we modified print_register_list so that it could accept register lists without qualifiers. For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is similar to SME_Ztx4_STRIDED and we could use existing code for parsing, encoding, and disassembly. For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12. This is a ZT0 register with a bit index encoded in [13:12]. It is similar to SME_ZT0_INDEX. We also introduced an iclass named sme_size_12_b so that we can encode size bits [13:12] correctly when only 'b' is allowed as qualifier.
2024-06-18RISC-V: Updated gas/NEWS and gas/doc/c-riscv.texi for vendor extensions.Nelson Chu1-10/+10
gas/ * NEWS: Updated for XCvMem, XCvBi, XCvElw, XSfCease. * doc/c-riscv.texi: Minor typo for XCv* extensions.
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu1-0/+5
Add SiFive cease extension, https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf This aligns LLVM: * https://llvm.org/docs/RISCVUsage.html * https://github.com/llvm/llvm-project/pull/83896 bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'. (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE. (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE. gas/ChangeLog: * doc/c-riscv.texi: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'. * testsuite/gas/riscv/sifive-insns.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask encoding for 'sf.cease'. * opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas1-0/+2
The FEAT_BRBE extension provides two aliases of sys: - brb iall (Invalidates all Branch records in the Branch Record Buffer) - brb inj (Injects the Branch Record held in BRBINFINJ_EL1, BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer) This patch adds: - the feature option "brbe" that must be added for the aliases to be available - a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment when Rt is set to the non default value 0b11111 (it is constrained unpredictable whether the instruction is undefined or behaves as if the Rt field is set to 0b11111). - a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values from bit 5 - support for the two brb aliases above See: - https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
2024-06-10gas: extend \+ support to .reptJan Beulich1-0/+7
PR gas/31752 While not quite as macro-like as .irp / .irpc, this perhaps benefits from supporting \+ even more than those: It allows, where desired, to get away without maintaining an explicit count variable in source code. Keep .rep (and custom per-arch uses of s_rept() / do_repeat()) behavior unaltered.
2024-06-05arm: minor documentation cleanup given removal of FPARichard Earnshaw1-3/+0
The use in the documentation of .save for an FPA instruction is no-longer relevant, so remove it.
2024-06-05arm: remove options to select the FPARichard Earnshaw1-8/+1
Remove the command-line options to choose the FPA (or FPE - an emulated FPA). From this point on it should be impossible to assemble the old FPA instructions.
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVmem as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mem-fail-march.d: New test. * testsuite/gas/riscv/cv-mem-fail-march.l: New test. * testsuite/gas/riscv/cv-mem-fail-march.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-mem-lbpost.d: New test. * testsuite/gas/riscv/cv-mem-lbpost.s: New test. * testsuite/gas/riscv/cv-mem-lbrr.d: New test. * testsuite/gas/riscv/cv-mem-lbrr.s: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lbupost.d: New test. * testsuite/gas/riscv/cv-mem-lbupost.s: New test. * testsuite/gas/riscv/cv-mem-lburr.d: New test. * testsuite/gas/riscv/cv-mem-lburr.s: New test. * testsuite/gas/riscv/cv-mem-lburrpost.d: New test. * testsuite/gas/riscv/cv-mem-lburrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhpost.d: New test. * testsuite/gas/riscv/cv-mem-lhpost.s: New test. * testsuite/gas/riscv/cv-mem-lhrr.d: New test. * testsuite/gas/riscv/cv-mem-lhrr.s: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhupost.d: New test. * testsuite/gas/riscv/cv-mem-lhupost.s: New test. * testsuite/gas/riscv/cv-mem-lhurr.d: New test. * testsuite/gas/riscv/cv-mem-lhurr.s: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.s: New test. * testsuite/gas/riscv/cv-mem-lwpost.d: New test. * testsuite/gas/riscv/cv-mem-lwpost.s: New test. * testsuite/gas/riscv/cv-mem-lwrr.d: New test. * testsuite/gas/riscv/cv-mem-lwrr.s: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.s: New test. * testsuite/gas/riscv/cv-mem-sbpost.d: New test. * testsuite/gas/riscv/cv-mem-sbpost.s: New test. * testsuite/gas/riscv/cv-mem-sbrr.d: New test. * testsuite/gas/riscv/cv-mem-sbrr.s: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-shpost.d: New test. * testsuite/gas/riscv/cv-mem-shpost.s: New test. * testsuite/gas/riscv/cv-mem-shrr.d: New test. * testsuite/gas/riscv/cv-mem-shrr.s: New test. * testsuite/gas/riscv/cv-mem-shrrpost.d: New test. * testsuite/gas/riscv/cv-mem-shrrpost.s: New test. * testsuite/gas/riscv/cv-mem-swpost.d: New test. * testsuite/gas/riscv/cv-mem-swpost.s: New test. * testsuite/gas/riscv/cv-mem-swrr.d: New test. * testsuite/gas/riscv/cv-mem-swrr.s: New test. * testsuite/gas/riscv/cv-mem-swrrpost.d: New test. * testsuite/gas/riscv/cv-mem-swrrpost.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvmem string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVmem. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVmem. (enum riscv_insn_class): Add the XCVmem instruction class. opcodes/ChangeLog: * riscv-opc.c: Add XCVmem instructions.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVelw as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-elw-fail.d: New test. * testsuite/gas/riscv/cv-elw-fail.l: New test. * testsuite/gas/riscv/cv-elw-fail.s: New test. * testsuite/gas/riscv/cv-elw-fail-march.d: New test. * testsuite/gas/riscv/cv-elw-fail-march.l: New test. * testsuite/gas/riscv/cv-elw-fail-march.s: New test. * testsuite/gas/riscv/cv-elw-pass.d: New test. * testsuite/gas/riscv/cv-elw-pass.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvelw string. opcodes/ChangeLog: * riscv-opc.c: (riscv_opcode) Add event load instructions. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction opcode macros. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
2024-05-31gas, aarch64: Fixes in texi and tests following faminmax and lut changessaurabh.jha@arm.com1-8/+8
Making two cleanups that came out of the comments from my previous patches: 1. Fixing `c-aarch64.texi` file so that the AArch64 architecture extensions are ordered alphabetically. 2. Fixing faminmax test cases so that they follow the existing test conventions.
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com1-0/+2
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions needed definition of some new operands. We will first discuss operands for the third operand of the instructions and then discuss a vector register list operand needed for the second operand. The third operands are vectors with bit indices and without type qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 and they have 1 bit, 2 bit, and 3 bit indices respectively. For these new operands, we defined new parsing case branch. The lsb and width of these operands are the same as many existing but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h for these new operands. For the second operand of these instructions, we introduced a new operand called LVn_LUT. This represents a vector register list with stride 1. We defined new inserter and extractor for this new operand and it is encoded in FLD_Rn. We are enforcing the number of registers in the reglist using opcode flag rather than operand flag as this is what other SIMD vector register list operands are doing. The disassembly also uses opcode flag to print the correct number of registers.
2024-05-28Fix typo in assembler documentationNick Clifton1-1/+1
2024-05-28RISC-V: Fix U insn; replace opcode6 with opcode7 in gas/doc/c-riscv.texiJavier Mora1-22/+22
The type U RISC-V instruction format in gas/doc/c-riscv.texi shows the bit arrangement of the simm20 immediate that belongs to the J type; It should be just `simm20[19:0]`. The current behavior of `gas` matches the proposed documentation change. Additionally, the opcode is called `opcode6` despite of having 7 bits. Rename it to `opcode7`. gas/ * doc/c-riscv.texi: Fix U type, and replace opcode6 with opcode7.
2024-05-24gas: adjust handling of quotes for .irpcJan Beulich1-7/+8
The present handling of inner double quotes can lead to very strange diagnostics. Follow one of the two possible interpretations of the doc: @dots{} referring to possibly multiple white space separated @var{values}, each of which may be quoted. The original implementation, prior to 465e5617233f ("PR gas/3856"), hints at the other possible interpretation: When quoted there's only a single @var{values}, with inner quotes taken as ordinary characters. That, however, seems overall less useful to me. While touching the documentation, mirror the (inverse) spelling correction (@section line inconsistent with actual description) to .irp as well.
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+2
2024-05-14arm: update documentation for removal of the Maverick extensionRichard Earnshaw1-7/+4
Finally, update the documentation and add a NEWS item.
generated by cgit v1.1 at 2025-08-03 08:34:17 +0000