| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-07-08 | aarch64: Add support for sve2p1 pmov instruction. | srinath | 1 | -3/+25 |
| 2024-07-05 | x86-64: Fix support for APX NF TLS IE with 2 operands | Lingling Kong | 1 | -3/+2 |
| 2024-07-05 | aarch64: fix build with old glibc | Jan Beulich | 1 | -3/+3 |
| 2024-07-04 | RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issue | Sun Sunny | 1 | -1/+4 |
| 2024-07-04 | RISC-V: hash with segment id and pcrel_hi address while recording pcrel_hi | Lifang Xia | 1 | -7/+17 |
| 2024-07-04 | mve: Fix encoding for vcvt[bt] single-half float conversion instructions | Andre Vieira | 1 | -4/+13 |
| 2024-07-04 | gas: Enhance arch-specific SFrame configuration descriptions | Jens Remus | 4 | -14/+19 |
| 2024-07-04 | x86: Remove unused SFrame CFI RA register variable | Jens Remus | 1 | -1/+0 |
| 2024-07-04 | Support APX CFCMOV | Cui, Lili | 1 | -1/+1 |
| 2024-07-03 | x86-64: Support APX NF TLS IE with 2 operands | Lingling Kong | 1 | -2/+8 |
| 2024-06-28 | aarch64: Add support for Armv9.5-A architecture | Claudio Bantaloukas | 1 | -0/+1 |
| 2024-06-28 | x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms | Jan Beulich | 1 | -1/+16 |
| 2024-06-28 | x86/APX: extend TEST-by-imm7 optimization to CTESTcc | Jan Beulich | 1 | -2/+8 |
| 2024-06-28 | x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHL | Jan Beulich | 1 | -0/+70 |
| 2024-06-28 | x86-64: restrict by-imm31 optimization | Jan Beulich | 1 | -12/+15 |
| 2024-06-28 | x86/APX: optimize certain {nf}-form insns to LEA | Jan Beulich | 1 | -8/+236 |
| 2024-06-28 | x86/APX: optimize {nf}-form rotate-by-width-less-1 | Jan Beulich | 1 | -1/+21 |
| 2024-06-28 | x86/APX: optimize {nf} forms of ADD/SUB with specific immediates | Jan Beulich | 1 | -1/+83 |
| 2024-06-25 | aarch64: Treat operand ADDR_SIMPLE as address with base register | Jens Remus | 1 | -3/+3 |
| 2024-06-25 | aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands. | Srinath Parvathaneni | 1 | -3/+1 |
| 2024-06-25 | aarch64: Fix sve2p1 extq instruction operands. | Srinath Parvathaneni | 1 | -1/+1 |
| 2024-06-24 | aarch64: Add SME FP8 multiplication instructions | Andrew Carlotti | 1 | -0/+11 |
| 2024-06-24 | aarch64: Add FP8 Neon and SVE multiplication instructions | Andrew Carlotti | 1 | -2/+24 |
| 2024-06-24 | aarch64: Add support for virtual features | Andrew Carlotti | 1 | -19/+45 |
| 2024-06-24 | aarch64: Move struct definition towards its usage | Andrew Carlotti | 1 | -8/+8 |
| 2024-06-24 | gas, aarch64: Add SME2 lutv2 extension | saurabh.jha@arm.com | 1 | -4/+88 |
| 2024-06-21 | x86: optimize {,V}PEXTR{D,Q} with immediate of 0 | Jan Beulich | 1 | -0/+38 |
| 2024-06-21 | x86: optimize left-shift-by-1 | Jan Beulich | 1 | -0/+79 |
| 2024-06-21 | x86: %riz, %rip, and %eip don't require REX | Jan Beulich | 1 | -2/+2 |
| 2024-06-21 | x86: don't suppress errors when optimizing | Jan Beulich | 1 | -1/+16 |
| 2024-06-18 | Support APX CCMP and CTEST | Cui, Lili | 1 | -1/+145 |
| 2024-06-18 | LoongArch: add .option directive | Lulu Cai | 1 | -0/+59 |
| 2024-06-12 | aarch64: add Branch Record Buffer extension instructions | Claudio Bantaloukas | 1 | -0/+8 |
| 2024-06-12 | RISC-V: Support S[sm]csrind extension csrs. | Jiawei | 1 | -0/+22 |
| 2024-06-10 | aarch64: warn on unpredictable results for new rcpc3 instructions | Matthieu Longo | 1 | -1/+39 |
| 2024-06-10 | x86/APX: convert ZU to operand constraint | Jan Beulich | 1 | -1/+5 |
| 2024-06-05 | arm: remove FPA instructions from assembler | Richard Earnshaw | 1 | -699/+0 |
| 2024-06-05 | arm: remove options to select the FPA | Richard Earnshaw | 1 | -15/+1 |
| 2024-06-05 | arm: change default FPUs from FPA to none | Richard Earnshaw | 1 | -62/+63 |
| 2024-06-05 | arm: redirect fp constant data directives through a wrapper | Richard Earnshaw | 1 | -5/+20 |
| 2024-06-05 | arm: adjust FPU selection logic | Richard Earnshaw | 1 | -9/+2 |
| 2024-06-05 | arm: default to softvfp on armv6 or later cores | Richard Earnshaw | 1 | -17/+17 |
| 2024-06-05 | arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP | Richard Earnshaw | 5 | -58/+96 |
| 2024-06-05 | RISC-V: Add support for XCVbi extension in CV32E40P | Mary Bennett | 1 | -1/+11 |
| 2024-06-04 | LoongArch: Make align symbol be in same section with alignment directive | mengqinggang | 2 | -1/+65 |
| 2024-05-31 | x86: reduce check_{byte,word,long,qword}_reg() overhead | Jan Beulich | 1 | -4/+15 |
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 1 | -0/+13 |
| 2024-05-29 | x86/Intel: SHLD/SHRD have dual meaning | Jan Beulich | 1 | -2/+5 |
| 2024-05-29 | PR31796, Internal error in write_function_pdata at obj-coff-seh | Alan Modra | 1 | -2/+22 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 1 | -0/+3 |
