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2023-12-29LoongArch: gas: Add support for tls le relax.changjiachen1-0/+32
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu1-0/+20
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu2-5/+19
2023-12-28Support APX NDD optimized encoding.Hu, Lin11-0/+104
2023-12-28Support APX pushp/poppCui, Lili1-1/+2
2023-12-28Support APX Push2/Pop2Mo, Zewei1-0/+44
2023-12-28Support APX NDDkonglin11-17/+45
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-12/+73
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-20/+158
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang1-2/+6
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-1/+13
2023-12-22nios2: fix .text/.data interaction with .previousJan Beulich1-2/+2
2023-12-22hppa/ELF: fix .text/.data interaction with .previousJan Beulich1-4/+15
2023-12-22RISC-V: drop .bss overrideJan Beulich1-10/+0
2023-12-22x86-64: refuse "high" 8-bit regs with .insn and VEX/XOP/EVEX encodingsJan Beulich1-0/+10
2023-12-22x86: properly respect rex/{rex}Jan Beulich1-62/+71
2023-12-22LoongArch: Add support for the third expression of .align for R_LARCH_ALIGNmengqinggang2-8/+16
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo1-0/+1
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo1-0/+1
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-4/+5
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang1-1/+5
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+2
2023-12-15x86: last-insn recording should be per-subsectionJan Beulich2-0/+38
2023-12-15ELF: reliably invoke md_elf_section_change_hook()Jan Beulich1-11/+18
2023-12-15ELF: drop "push" parameter from obj_elf_change_section()Jan Beulich9-24/+34
2023-12-15x86: don't needlessly override .bssJan Beulich1-8/+5
2023-12-15x86: fold assembly dialect attributesJan Beulich2-5/+5
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich2-5/+8
2023-12-15Arm64: fix build for certain gcc versionsJan Beulich1-3/+3
2023-12-13Clean base_reg and assign correct values to regs for input_output_operand (%dx).Cui, Lili1-0/+2
2023-12-12Fix whitespace snafu in tc-riscv.cNick Clifton1-5/+5
2023-12-12RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instructionRui Ueyama2-0/+23
2023-12-12RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'Lifang Xia2-0/+111
2023-12-11RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fixNelson Chu1-1/+1
2023-12-01x86: adjust NOP generation after potential non-insnJan Beulich2-1/+13
2023-12-01x86: i386_cons_align() badly affects diagnosticsJan Beulich1-12/+1
2023-12-01x86: suppress optimization after potential non-insnJan Beulich1-0/+5
2023-12-01x86: last-insn recording should be per-sectionJan Beulich2-58/+64
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+68
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi1-0/+3
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi1-2/+2
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen1-2/+4
2023-11-24x86: shrink opcode sets tableJan Beulich2-130/+130
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich1-6/+14
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-16/+5
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich1-3/+3
2023-11-23s390: Add missing extended mnemonicsJens Remus1-4/+8
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-0/+4
2023-11-22LoongArch: fix internal error when as handling unsupported modifier.Lulu Cai1-1/+5
2023-11-21bpf: Fixed register parsing disambiguating with possible symbol.Cupertino Miranda1-0/+4
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