riscv-gnu-toolchain/binutils.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2025-01-01	Update year range in copyright notice of binutils files	Alan Modra	2	-2/+2

2024-01-04	Update year range in copyright notice of binutils files	Alan Modra	2	-2/+2
	Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out /po/.pot which we don't update frequently.
2023-12-05	Add basic support for RISC-V 64-bit EFI objects	Andreas Schwab	2	-0/+47
	This adds a new PEI target pei-riscv64-little. Only objdump and objcopy are supported. bfd: * .gitignore: Add pe-riscv64igen.c. * Makefile.am (BFD64_BACKENDS): Add pei-riscv64.lo, pe-riscv64igen.lo. (BFD64_BACKENDS_CFILES): Add pei-riscv64.c. (BUILD_CFILES): Add pe-riscv64igen.c. (pe-riscv64igen.c): New rule. * Makefile.in: Regenerate. * bfd.c (bfd_get_sign_extend_vma): Add pei-riscv64-little. * coff-riscv64.c: New file. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags) (coff_write_object_contents): Add riscv64 (riscv64_pei_vec) support. * config.bfd (targ_selvecs): Add riscv64_pei_vec to all riscv* targets. * configure.ac: Handle riscv64_pei_vec. * configure: Regenerate. * libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE) (GET_OPTHDR_SIZE_OF_STACK_RESERVE) (PUT_OPTHDR_SIZE_OF_STACK_RESERVE) (GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT) (GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE) (GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT) (GET_PDATA_ENTRY, _bfd_XX_bfd_copy_private_bfd_data_common) (_bfd_XX_bfd_copy_private_section_data) (_bfd_XX_get_symbol_info, _bfd_XX_only_swap_filehdr_out) (_bfd_XX_print_private_bfd_data_common) (_bfd_XXi_final_link_postscript, _bfd_XXi_only_swap_filehdr_out) (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out) (_bfd_XXi_swap_aux_in, _bfd_XXi_swap_aux_out) (_bfd_XXi_swap_lineno_in, _bfd_XXi_swap_lineno_out) (_bfd_XXi_swap_scnhdr_out, _bfd_XXi_swap_sym_in) (_bfd_XXi_swap_sym_out, _bfd_XXi_swap_debugdir_in) (_bfd_XXi_swap_debugdir_out, _bfd_XXi_write_codeview_record) (_bfd_XXi_slurp_codeview_record) [COFF_WITH_peRiscV64]: Define. (_bfd_peRiscV64_print_ce_compressed_pdata): Declare. * peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out) (_bfd_XXi_swap_scnhdr_out, pe_print_pdata) (_bfd_XX_print_private_bfd_data_common) (_bfd_XX_bfd_copy_private_section_data) (_bfd_XXi_final_link_postscript): Support COFF_WITH_peRiscV64. * pei-riscv64.c: New file. * peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd) (pe_ILF_object_p): Support COFF_WITH_peRiscV64. (jtab): Add dummy entry that traps. * targets.c (_bfd_target_vector): Add riscv64_pei_vec. binutils: * testsuite/binutils-all/riscv/pei-riscv64.d: New. * testsuite/binutils-all/riscv/pei-riscv64.s: New. include: * coff/riscv64.h: New file. * coff/pe.h (IMAGE_FILE_MACHINE_RISCV32) (IMAGE_FILE_MACHINE_RISCV64): Define.
2023-02-03	RISC-V: don't disassemble unrecognized insns as .byte	Jan Beulich	1	-3/+3
	Insn width granularity being 16 bits, producing byte granular output isn't very useful. With there being a way to specific otherwise unknown insns to the assembler, use that same representation (to be precise: its <length>,<encoding> flavor) for disassembly.
2023-01-01	Update year range in copyright notice of binutils files	Alan Modra	2	-2/+2
	The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-01-02	Update year range in copyright notice of binutils files	Alan Modra	2	-2/+2
	The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out /po/.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-09-20	riscv: print .2byte or .4byte before an unknown instruction encoding	Andrew Burgess	3	-0/+67
	When the RISC-V disassembler encounters an unknown instruction, it currently just prints the value of the bytes, like this: Dump of assembler code for function custom_insn: 0x00010132 <+0>: addi sp,sp,-16 0x00010134 <+2>: sw s0,12(sp) 0x00010136 <+4>: addi s0,sp,16 0x00010138 <+6>: 0x52018b 0x0001013c <+10>: 0x9c45 My proposal, in this patch, is to change the behaviour to this: Dump of assembler code for function custom_insn: 0x00010132 <+0>: addi sp,sp,-16 0x00010134 <+2>: sw s0,12(sp) 0x00010136 <+4>: addi s0,sp,16 0x00010138 <+6>: .4byte 0x52018b 0x0001013c <+10>: .2byte 0x9c45 Adding the .4byte and .2byte opcodes. The benefit that I see here is that in the patched version of the tools, the disassembler output can be fed back into the assembler and it should assemble to the same binary format. Before the patch, the disassembler output is invalid assembly. I've started a RISC-V specific test file under binutils so that I can add a test for this change. binutils/ChangeLog: * testsuite/binutils-all/riscv/riscv.exp: New file. * testsuite/binutils-all/riscv/unknown.d: New file. * testsuite/binutils-all/riscv/unknown.s: New file. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode before an unknown instruction, '%d' is replaced with the instruction length.