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Some tests started passing with commit 3a83f0342e54. However,
supporting a changed ld output format is not so simple, and the change
to the loongarch_elf_hash_table macro needs further changes to the
rest of the code. It is true that some uses of
loongarch_elf_hash_table do not need to check the type of the hash
table, but others like loongarch_elf_relax_section do need to check.
bfd_relax_section is called in lang_size_sections using the input bfd,
not the output bfd. If the input bfd may be of different type to the
output, then the hash table type must be checked before accessing
elements of the hash table. This patch corrects
loongarch_elf_relax_section. I haven't checked all the uses of the
hash table throughout the loongarch backend.
bfd/
* elfnn-loongarch.c (loongarch_elf_relax_section): Don't relax
unless the hash table is loongarch_elf_link_hash_table.
Move variable declarations. Formatting.
ld/
* testsuite/ld-elf/pr21884.d: Don't xfail loongarach.
* testsuite/ld-unique/pr21529.d: Likewise.
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Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/march-help.l: Add xcvbitmanip.
* testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test.
* testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test.
* testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test.
* testsuite/gas/riscv/x-cv-bitmanip.d: New Test.
* testsuite/gas/riscv/x-cv-bitmanip.s: New Test.
include/opcode/ChangeLog:
* riscv-opc.h: Add corresponding MATCH and MASK macros for
XCVbitmanip.
* riscv.h: Add corresponding EXTRACT and ENCODE macros for
XCVbitmanip.
(enum riscv_insn_class): Add the XCVbitmanip instruction class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`.
* riscv-opc.c: Add XCvBitmanip instructions.
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This implements the Zcmop (Compressed Zimop) extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>
The Zcmop extension requires the Zca extension.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zcmop.d: New test.
* testsuite/gas/riscv/zcmop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop.
(MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7,
MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define.
(MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7,
MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP.
opcodes/ChangeLog:
* riscv-opc.c: Add Zcmop instructions.
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This implements the Zimop (May-Be-Operations) extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zimop.d: New test.
* testsuite/gas/riscv/zimop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zimop.
(MATCH_MOP_R_0, MATCH_MOP_R_1, MATCH_MOP_R_2, MATCH_MOP_R_3,
MATCH_MOP_R_4, MATCH_MOP_R_5, MATCH_MOP_R_6, MATCH_MOP_R_7,
MATCH_MOP_R_8, MATCH_MOP_R_9, MATCH_MOP_R_10, MATCH_MOP_R_11,
MATCH_MOP_R_12, MATCH_MOP_R_13, MATCH_MOP_R_14, MATCH_MOP_R_15,
MATCH_MOP_R_16, MATCH_MOP_R_17, MATCH_MOP_R_18, MATCH_MOP_R_19,
MATCH_MOP_R_20, MATCH_MOP_R_21, MATCH_MOP_R_22, MATCH_MOP_R_23,
MATCH_MOP_R_24, MATCH_MOP_R_25, MATCH_MOP_R_26, MATCH_MOP_R_27,
MATCH_MOP_R_28, MATCH_MOP_R_29, MATCH_MOP_R_30, MATCH_MOP_R_31,
MATCH_MOP_RR_0, MATCH_MOP_RR_1, MATCH_MOP_RR_2, MATCH_MOP_RR_3,
MATCH_MOP_RR_4, MATCH_MOP_RR_5, MATCH_MOP_RR_6, MATCH_MOP_RR_7): Define.
(MASK_MOP_R_0, MASK_MOP_R_1, MASK_MOP_R_2, MASK_MOP_R_3, MASK_MOP_R_4,
MASK_MOP_R_5, MASK_MOP_R_6, MASK_MOP_R_7, MASK_MOP_R_8, MASK_MOP_R_9,
MASK_MOP_R_10, MASK_MOP_R_11, MASK_MOP_R_12, MASK_MOP_R_13,
MASK_MOP_R_14, MASK_MOP_R_15, MASK_MOP_R_16, MASK_MOP_R_17,
MASK_MOP_R_18, MASK_MOP_R_19, MASK_MOP_R_20, MASK_MOP_R_21,
MASK_MOP_R_22, MASK_MOP_R_23, MASK_MOP_R_24, MASK_MOP_R_25,
MASK_MOP_R_26, MASK_MOP_R_27, MASK_MOP_R_28, MASK_MOP_R_29,
MASK_MOP_R_30, MASK_MOP_R_31, MASK_MOP_RR_0, MASK_MOP_RR_1,
MASK_MOP_RR_2, MASK_MOP_RR_3, MASK_MOP_RR_4, MASK_MOP_RR_5,
MASK_MOP_RR_6, MASK_MOP_RR_7): Ditto.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP.
opcodes/ChangeLog:
* riscv-opc.c: Add Zimop instructions.
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In binary output format, loongarch_elf_hash_table return NULL and result
in segment fault.
When ld output binary file, it seems that elf related functions should
not be called. But loongarch_elf_relax_section be called and
loongarch_elf_hash_table cause segment fault.
Just redefined loongarch_elf_hash_table and always return
link_info->hash.
The tests of binutils, glibc and gcc is ok.
0 loongarch_elf_relax_section ()
1 0x000055555557ab28 in lang_size_sections_1 ()
2 0x000055555557a16c in lang_size_sections_1 ()
3 0x000055555557b0a8 in one_lang_size_sections_pass ()
4 0x000055555557b478 in lang_size_sections ()
5 0x000055555557e65c in lang_relax_sections ()
6 0x000055555559f9c8 in ldelf_map_segments ()
7 0x000055555559783c in gldelf64loongarch_after_allocation ()
8 0x000055555558dac0 in ldemul_after_allocation ()
9 0x000055555557f6c0 in lang_process ()
10 0x0000555555585314 in main ()
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Change TLS transition error messages from
a-argp-help.o(.text+0x12f): relocation R_X86_64_GOTTPOFF against `a' must be used in ADD or MOV onlyld: final link failed: bad value
to
a-argp-help.o(.text+0x12f): relocation R_X86_64_GOTTPOFF against `a' must be used in ADD or MOV only
ld: final link failed: bad value
PR ld/32017
* elfxx-x86.c (_bfd_x86_elf_link_report_tls_transition_error):
Add missing newlines.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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Provide detailed TLS transition errors when unsupported instructions are
used. Treat R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_6_GOTTPOFF as
R_X86_64_GOTTPOFF when performing TLS transition.
bfd/
PR ld/32017
* elf32-i386.c (elf_i386_check_tls_transition): Return different
enums for different errors.
(elf_i386_tls_transition): Change argument from r_symndx to sym.
Call _bfd_x86_elf_link_report_tls_transition_error to report TLS
transition errors.
(elf_i386_scan_relocs): Pass isym instead of r_symndx to
elf_i386_tls_transition.
(elf_i386_relocate_section): Pass sym instead of r_symndx to
elf_i386_tls_transition.
* elf64-x86-64.c (elf_x86_64_check_tls_transition): Return
different enums for different errors.
(elf_x86_64_tls_transition): Change argument from r_symndx to sym.
Treat R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_6_GOTTPOFF as
R_X86_64_GOTTPOFF. Call
_bfd_x86_elf_link_report_tls_transition_error to report TLS
transition errors.
(elf_x86_64_scan_relocs): Pass isym instead of r_symndx to
elf_x86_64_tls_transition.
(elf_x86_64_relocate_section): Pass sym instead of r_symndx to
elf_x86_64_tls_transition.
* elfxx-x86.c (_bfd_x86_elf_link_report_tls_transition_error): New.
* elfxx-x86.h (elf_x86_tls_error_type): Likewise.
(_bfd_x86_elf_link_report_tls_transition_error): Likewise.
ld/
PR ld/32017
* testsuite/ld-i386/i386.exp: Run tlsgdesc1 and tlsgdesc2.
* testsuite/ld-i386/tlsie2.d: Updated.
* testsuite/ld-i386/tlsie3.d: Likewise.
* testsuite/ld-i386/tlsie4.d: Likewise.
* testsuite/ld-i386/tlsie5.d: Likewise.
* testsuite/ld-x86-64/tlsie2.d: Likewise.
* testsuite/ld-x86-64/tlsie3.d: Likewise.
* testsuite/ld-i386/tlsgdesc1.d: New file.
* testsuite/ld-i386/tlsgdesc1.s: Likewise.
* testsuite/ld-i386/tlsgdesc2.d: Likewise.
* testsuite/ld-i386/tlsgdesc2.s: Likewise.
* testsuite/ld-x86-64/tlsdesc3.d: Likewise.
* testsuite/ld-x86-64/tlsdesc3.s: Likewise.
* testsuite/ld-x86-64/tlsdesc4.d: Likewise.
* testsuite/ld-x86-64/tlsdesc4.s: Likewise.
* testsuite/ld-x86-64/tlsie5.d: Likewise.
* testsuite/ld-x86-64/tlsie5.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run tlsie5, tlsdesc3 and
tlsdesc4.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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bfd/
PR 32001
* elfxx-riscv.c (riscv_update_subset1): Fixed the untranslated
"internal:" prefix for error message.
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PR 31953
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The option only makes sense for RELA relative relocs where the
addend is present, not for RELR relative relocs.
Fixes bug 31924.
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Commit d125f9675372b1ae01ceb1893c06ccb27bc7bf22 introduced a bug
in handling relocations for data. The R_PARISC_DIR32 relocation
operates on 32-bit data and not instructions. The HOWTO table
needs to be used to determine the format of relocations that apply
to data. The R_PARISC_SEGBASE relocation is another special case
as it only changes segment base.
This was noticed in Debian cmor package build.
2024-07-14 John David Anglin <danglin@gcc.gnu.org>
bfd/ChangeLog:
* elf32-hppa.c (final_link_relocate): Use HOWTO table to
determine reload format for relocations that apply to data.
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This complements and reuses logic from Andreas Krebbel's commit
896a639babe2 ("s390: Avoid reloc overflows on undefined weak symbols").
Replace relative long addressing instructions of weak symbols, which
will definitely resolve to zero, with either a load address of 0 or a
a trapping insn.
This prevents the PLT32DBL relocation from overflowing in case the
binary will be loaded at 4GB or more.
bfd/
* elf64-s390.c (elf_s390_relocate_section): Replace
instructions using undefined weak symbols with relative
addressing to avoid relocation overflows.
ld/
* testsuite/ld-s390/s390.exp: Add new test.
* testsuite/ld-s390/weakundef-2.s: New test.
* testsuite/ld-s390/weakundef-2.dd: Likewise.
Reported-by: Alexander Gordeev <agordeev@linux.ibm.com>
Suggested-by: Ilya Leoshkevich <iii@linux.ibm.com>
Suggested-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Branch Relative on Count High (brcth) is a conditional branch relative
instruction. It is not guaranteed that it only appears within loops
that sooner or later will take the branch. It may very well be used to
check a condition that will prevent the branch from ever being taken.
bfd/
* elf64-s390.c (elf_s390_relocate_section): Do not replace brcth
referencing undefined weak symbol with a trap.
ld/
* testsuite/ld-s390/weakundef-1.s: Update test case accordingly.
* testsuite/ld-s390/weakundef-1.dd: Likewise.
Fixes: 896a639babe2 ("s390: Avoid reloc overflows on undefined weak symbols")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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RISC-V Profiles document defines number of "extensions" that indicate
certain platform properties/capabilities just like 'Zkt' extension from the
RISC-V cryptography extensions.
This commit defines 20 platform property/capability extensions as defined
in the RISC-V Profiles documentation.
The only exception: 'Ssstateen' extension is defined separately because it
defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension.
This is based on the ratified version of RISC-V Profiles:
<https://github.com/riscv/riscv-profiles/releases/tag/v1.0>
[Definition]
"Main memory regions":
Main memory regions (in contrast to I/O or vacant memory regions) with
both the cacheability and coherence PMAs.
[New Unprivileged Extensions]
1. 'Ziccif'
"Main memory regions" support instruction fetch and any instruction
fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN)
are atomic.
2. 'Ziccrse'
"Main memory regions" provide the eventual success guarantee for
LR/SC sequence (RsrvEventual).
3. 'Ziccamoa'
"Main memory regions" support all currently-defined AMO operations
including swap, logical and arithmetic operations (AMOArithmetic).
4. 'Za64rs'
For LR/SC instructions, reservation sets are contiguous, naturally
aligned and at most 64-bytes in size.
5. 'Za128rs'
Likewise, but reservation sets are at most 128-bytes in size.
6. 'Zicclsm'
Misaligned loads / stores to "main memory regions" are supported.
Those include both regular scalar and vector accesses but does not
include AMOs and other specialized forms of memory accesses.
7. 'Zic64b'
Cache blocks are (exactly) 64-bytes in size and naturally aligned.
[New Privileged Extensions]
1. 'Svbare'
"satp" mode Bare is supported.
2. 'Svade'
Page-fault exceptions are raised when a page is accessed when A bit is
clear, or written when D bit is clear.
3. 'Ssccptr'
"Main memory regions" support hardware page-table reads.
4. 'Sstvecd'
"stvec" mode Direct is supported. When "stvec" mode is Direct,
"stvec.BASE" is capable of holding any valid 4-byte aligned address.
5. 'Sstvala'
"stval" is always written with a nonzero value whenever possible as
specified in the Privileged Architecture documentation
(version 20211203: see section 4.1.9).
6. 'Sscounterenw'
For any "hpmcounter" that is not read-only zero, the corresponding bit
in "scounteren" is writable.
7. 'Ssu64xl'
"sstatus.UXL" is capable of holding the value 0b10
(UXLEN==64 is supported).
8. 'Shcounterenw'
Similar to 'Sscounterenw' but the same rule applies to "hcounteren".
9. 'Shvstvala'
Similar to 'Sstvala' but the same rule applies to "vstval".
10. 'Shtvala'
"htval" is written with the faulting guest physical address as long as
permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala').
11. 'Shvstvecd'
Similar to 'Sstvecd' but the same rule applies to "vstvec".
12. 'Shvsatpa'
All translation modes supported in "satp" are also supported in "vsatp".
13. 'Shgatpa'
For each supported virtual memory scheme SvNN supported in "satp", the
corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare
is also supported.
[Implications]
(Due to reservation set size constraints)
- 'Za64rs' -> 'Za128rs'
(Due to the fact that a privileged "extension" directly refers a CSR)
- 'Svbare' -> 'Zicsr'
- 'Sstvecd' -> 'Zicsr'
- 'Sstvala' -> 'Zicsr'
- 'Sscounterenw' -> 'Zicsr'
- 'Ssu64xl' -> 'Zicsr'
(Due to the fact that a privileged "extension" indirectly depends on CSRs)
- 'Svade' -> 'Zicsr'
(Due to the fact that a privileged "extension" is a hypervisor property)
- 'Shcounterenw' -> 'H'
- 'Shvstvala' -> 'H'
- 'Shtvala' -> 'H'
- 'Shvstvecd' -> 'H'
- 'Shvsatpa' -> 'H'
- 'Shgatpa' -> 'H'
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Updated for property
and capability extensions.
(riscv_supported_std_z_ext): Added zic64b, ziccamoa, ziccif, zicclsm,
ziccrse, za64rs and za128rs extensions.
(riscv_supported_std_s_ext): Added shcounterenw, shgatpa, shtvala,
shvsatpa, shvstvala, shvstvecd, ssccptr, sscounterenw, sstvala,
sstvecd, ssu64xlm svade and svbare extensions.
gas/
* testsuite/gas/riscv/imply.d: Updated for property and capability
extensions.
* testsuite/gas/riscv/imply.s: Likewise.
* testsuite/gas/riscv/march-help.l: Likewse.
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The absolute symbol should be resolved to const when link to dso or exe.
Alloc dynamic relocs will cause extra space and R_LARCH_NONE finally.
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