| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
The need for this has disappeared with dc12032bca08 ("Remove m68k-aout
and m68k-coff support"); avoid the unnecessary indirection.
Sadly, with ld/pe-dll.c using the wrapper, the removal requires moving
the declaration out of libcoff.h, to properly export the underlying BFD
function.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Avoid implementation defined behaviour right shift of negative values,
and undefined behaviour left shift of negative values. While this
change might give different results in the top bit of a bfd_vma
(rightshift is 1), that doesn't matter as only the bottom 8 bits of
the relocation are used.
* elf32-nds32.c (nds32_elf_do_9_pcrel_reloc): Calculate relocation
using a bfd_vma type.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Add instruction `mnret' support
Ref:
https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc
https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi
bfd/ChangeLog:
* elfxx-riscv.c: Add new Smrnmi instruction class handling
gas/ChangeLog:
* testsuite/gas/riscv/smrnmi.s: New test for mnret
* testsuite/gas/riscv/rmrnmi.d: Likewise
include/ChangeLog:
* opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET
* opcode/riscv.h: Add new instruction class
opcodes/ChangeLog:
* riscv-opc.c: Add `mnret' instruction
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
According to the spec[1], imply zicsr for ssnpm, smnpm and smmpm.
[1] https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc
bfd/ChangeLog:
* elfxx-riscv.c: imply zicsr.
|
|
|
|
|
|
|
|
|
|
- Adding Ssnpm, Smnpm, Smmpm, Sspm, and Supm
- No new CSR added
- Pointer masking only applies to RV64
- Ref: https://github.com/riscv/riscv-j-extension/releases/download/pointer-masking-ratified/pointer-masking-ratified.pdf
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
|
|
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds the additional extension "XTheadVdot" based on the
"V" extension, and it provides four 8-bit multiply and add with
32-bit instructions for the "v" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([2]).
Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com>
[1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot
[2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support
for "XTheadVdot" extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Likewise.
* testsuite/gas/riscv/march-help.l: Likewise.
* testsuite/gas/riscv/x-thead-vdot.d: New test.
* testsuite/gas/riscv/x-thead-vdot.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New.
* opcode/riscv.h (enum riscv_insn_class): Add insn class for
XTheadVdot.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
|
|
Since we now always generate $x+isa for now, these would increase the
dis-assemble time by parsing the same architecture string repeatedly. We
already have `arch_str' field into `subset_list' to record the current
architecture stirng, but it's only useful for assembler, since dis-assembler
and linker don't need it before. Now for dis-assembler, we just need to
update the `arch_str' after parsing the architecture stirng, and then avoid
parsing repeatedly if the strings are the same.
|
|
The string returned from riscv_arch_str is allocated by xmalloc, so once we
called it multiple times, we should keep the newest one for the output elf
architecture attribute, but free the remaining unused strings.
|
|
The riscv_update_subset1 returning wrong boolean value if the
riscv_parse_check_conflicts isn't called, though the current return value
doesn't really useful.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
This patch avoids generating PT_LOAD segments that trip a bug in
glibc's loader.
PR 25237
PR 32763
* elf.c (assign_file_positions_for_load_sections): Don't put
p_offset zero for empty PT_LOAD.
|
|
align_pagesize was used for two things, reducing p->p_align from
maxpagesize to the bed->p_align value (section alignment permitting),
and increasing p->p_align above maxpagesize if section alignment
required that. This patch untangles those two, making align_pagesize
only do the former. p->p_align is set directly for the latter. I've
made that change to p->p_align only when D_PAGED to keep things
consistent with other early assignments to p->p_align. p->p_align is
set later according to section alignment when not D_PAGED.
I've also moved the place where align_pagesize adjusts p->p_align to
be with other code setting p->p_align. That seemed better to me than
leaving it until the last possible moment. Note that it isn't
necessary to have this adjustment done inside a test for a PT_LOAD
header, since we never set align_pagesize non-zero outside a PT_LOAD
test.
* elf.c (assign_file_positions_for_load_sections): Clear
align_pagesize whenever we have a section alignment more than
bed->p_align. Set p->p_align rather than align_pagesize
when section alignment exceeds maxpagesize. Assign p->p_align
from align_pagesize earlier.
|
|
No functional changes here, just preparation for the next patch.
* elf.c (assign_file_positions_for_load_sections): Replace
p_align_p and p_align with align_pagesize. Revise comments
on code handling bed->p_align.
|
|
The loop did set cookie->rel to the i-th relocation twice. At the
beginning using the loop counter. At the end by incrementing. One
approach is sufficient.
Change cookie to pointer-to-const, replace cookie->rel by rel,
initialize before the loop and increment at the end, and merge the
two assertions (for cookie->rel) into one.
While at it change sec to pointer-to-const.
bfd/
* elf-sframe.c (sframe_decoder_init_func_bfdinfo): Cleanup use
of relocation cookie.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
|
|
|
|
bfd/
PR 32772
* elfnn-riscv.c (riscv_elf_relocate_section): Fixed segfault caused by
the accidental removal of `h != NULL' when handling a call to an
undefined weak function.
|
|
|
|
This function has a misleading parameter "contents", which usually
means an entire section contents is passed. However in this case the
actual sections contents plus one is passed, leading to miscalculating
the end of the buffer.
* elf-attrs.c (bfd_elf_parse_attr_section_v1): Delete hdr and
contents param. Add p and p_end as params.
(_bfd_elf_parse_attributes): Adjust to suit.
|
|
|
|
I got an request about the undefined behaviors, considering the following case,
$ cat test.c
void main ()
{
foo();
}
$ cat lib.h
void foo(void);
$ riscv64-unknown-linux-gnu-gcc test.c
riscv64-unknown-linux-gnu/bin/ld: /tmp/ccRO8fJl.o: in function `main':
test.c:(.text+0x8): undefined reference to `foo'
collect2: error: ld returned 1 exit status
$ riscv64-unknown-linux-gnu-gcc test.c -Wl,--unresolved-symbols=ignore-in-object-files
$ qemu-riscv64 a.out
Segmentation fault (core dumped)
Testing with x86 and aarch64, they won't get the segfault since they go plt
for the undefined foo symbol. So, after applying this patch, I can get the
following too,
$ qemu-riscv64 a.out
a.out: symbol lookup error: a.out: undefined symbol: foo
The change of this patch should only affect the call behavior, which refer
to an undefined (weak) symbol, when building an dynamic executable. I think
the pic/pie behavior won't be affected as usual.
|
|
|
