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| author | Jin Ma <jinma@linux.alibaba.com> | 2025-03-17 14:07:35 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-03-18 12:27:26 +0800 |
| commit | 66b81b40dcf1fe5739c6c8138b242e47ebab0c8a (patch) | |
| tree | b86d4fd2f21e213b095eecf596637b7b47dc6234 /bfd | |
| parent | e4c9f0e6c3a665c0a711dc6bf74e37dfc370e28c (diff) | |
| download | binutils-66b81b40dcf1fe5739c6c8138b242e47ebab0c8a.zip binutils-66b81b40dcf1fe5739c6c8138b242e47ebab0c8a.tar.gz binutils-66b81b40dcf1fe5739c6c8138b242e47ebab0c8a.tar.bz2 | |
RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds the additional extension "XTheadVdot" based on the
"V" extension, and it provides four 8-bit multiply and add with
32-bit instructions for the "v" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([2]).
Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com>
[1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot
[2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support
for "XTheadVdot" extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Likewise.
* testsuite/gas/riscv/march-help.l: Likewise.
* testsuite/gas/riscv/x-thead-vdot.d: New test.
* testsuite/gas/riscv/x-thead-vdot.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New.
* opcode/riscv.h (enum riscv_insn_class): Add insn class for
XTheadVdot.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 72610dc..a2f67bc 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1507,6 +1507,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadvdot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2806,6 +2807,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadsync"); case INSN_CLASS_XTHEADVECTOR: return riscv_subset_supports (rps, "xtheadvector"); + case INSN_CLASS_XTHEADVDOT: + return riscv_subset_supports (rps, "xtheadvdot"); case INSN_CLASS_XTHEADZVAMO: return riscv_subset_supports (rps, "xtheadzvamo"); case INSN_CLASS_XVENTANACONDOPS: @@ -3111,6 +3114,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadsync"; case INSN_CLASS_XTHEADVECTOR: return "xtheadvector"; + case INSN_CLASS_XTHEADVDOT: + return "xtheadvdot"; case INSN_CLASS_XTHEADZVAMO: return "xtheadzvamo"; case INSN_CLASS_XSFCEASE: |