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2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton1-1520/+1644
2023-07-04Automatic date update in version.inGDB Administrator1-1/+1
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton4-1515/+1642
2023-07-03RISC-V: Zvkh[a,b]: Remove individual instruction classChristoph Müllner1-8/+2
Currently we have three instruction classes defined for Zvkh[a,b]: - INSN_CLASS_ZVKNHA - INSN_CLASS_ZVKNHB - INSN_CLASS_ZVKNHA_OR_ZVKNHB The encodings of all instructions in Zvknh[a,b] are identical. Therefore, we don't need the individual instruction classes and can remove them. This patch also adds the missing support of the combined instruction class in riscv_multi_subset_supports_ext(). Fixes: 62edb233ef5 ("RISC-V: Add support for the Zvknh[a,b] ISA extensions") Reported-By: Nelson Chu <nelson@rivosinc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-03Add markers for the 2.41 branchNick Clifton1-0/+4
2023-07-03Automatic date update in version.inGDB Administrator1-1/+1
2023-07-02Automatic date update in version.inGDB Administrator1-1/+1
2023-07-01RISC-V: Add support for the Zvksc ISA extensionNathan Huckleberry1-0/+3
Zvksc is part of the vector crypto extensions. Zvksc is shorthand for the following set of extensions: - Zvks - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvksc extension. gas/ChangeLog: * testsuite/gas/riscv/zvksc.d: New test. * testsuite/gas/riscv/zvksc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknc ISA extensionNathan Huckleberry1-0/+3
Zvknc is part of the vector crypto extensions. Zvknc is shorthand for the following set of extensxions: - Zvkn - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvknc extension. gas/ChangeLog: * testsuite/gas/riscv/zvknc.d: New test. * testsuite/gas/riscv/zvknc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksg ISA extensionNathan Huckleberry1-0/+3
Zvksg is part of the vector crypto extensions. Zvksg is shorthand for the following set of extensions: - Zvks - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvksg extension. gas/ChangeLog: * testsuite/gas/riscv/zvksg.d: New test. * testsuite/gas/riscv/zvksg.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvks ISA extensionChristoph Müllner1-0/+4
Zvks is part of the vector crypto extensions. Zvks is shorthand for the following set of extensions: - Zvksed - Zvksh - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvks extension. gas/ChangeLog: * testsuite/gas/riscv/zvks.d: New test. * testsuite/gas/riscv/zvks.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkng ISA extensionNathan Huckleberry1-0/+3
Zvkng is part of the vector crypto extensions. Zvkng is shorthand for the following set of extensions: - Zvkn - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvkng extension. gas/ChangeLog: * testsuite/gas/riscv/zvkng.d: New test. * testsuite/gas/riscv/zvkng.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Allow nested implications for extensionsNathan Huckleberry1-7/+22
Certain extensions require two levels of implications. For example, zvkng implies zvkn and zvkn implies zvkned. Enabling zvkng should also enable zvkned. This patch fixes this behavior. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_add_implicit_subsets): Allow nested implications for extensions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkn ISA extensionChristoph Müllner1-0/+5
Zvkn is part of the vector crypto extensions. Zvkn is shorthand for the following set of extensions: - Zvkned - Zvknhb - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvkn extension. gas/ChangeLog: * testsuite/gas/riscv/zvkn.d: New test. * testsuite/gas/riscv/zvkn.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner1-0/+5
Zvksh is part of the vector crypto extensions. This extension adds the following instructions: - vsm3me.vv - vsm3c.vi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksh. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksh.d: New test. * testsuite/gas/riscv/zvksh.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM3C_VI): New. (MASK_VSM3C_VI): New. (MATCH_VSM3ME_VV): New. (MASK_VSM3ME_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksh. opcodes/ChangeLog: * riscv-opc.c: Add Zvksh instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner1-0/+5
Zvksed is part of the vector crypto extensions. This extension adds the following instructions: - vsm4k.vi - vsm4r.[vv,vs] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksed. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksed.d: New test. * testsuite/gas/riscv/zvksed.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM4K_VI): New. (MASK_VSM4K_VI): New. (MATCH_VSM4R_VS): New. (MASK_VSM4R_VS): New. (MATCH_VSM4R_VV): New. (MASK_VSM4R_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksed. opcodes/ChangeLog: * riscv-opc.c: Add Zvksed instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner1-0/+13
Zvknh[a,b] are parts of the vector crypto extensions. This extension adds the following instructions: - vsha2ms.vv - vsha2c[hl].vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvknh[a,b]. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvknha.d: New test. * testsuite/gas/riscv/zvknha_zvknhb.s: New test. * testsuite/gas/riscv/zvknhb.d: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New. (MASK_VSHA2CH_VV): New. (MATCH_VSHA2CL_VV): New. (MASK_VSHA2CL_VV): New. (MATCH_VSHA2MS_VV): New. (MASK_VSHA2MS_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvknh[a,b]. opcodes/ChangeLog: * riscv-opc.c: Add Zvknh[a,b] instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner1-0/+5
Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkned. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkned.d: New test. * testsuite/gas/riscv/zvkned.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VAESDF_VS): New. (MASK_VAESDF_VS): New. (MATCH_VAESDF_VV): New. (MASK_VAESDF_VV): New. (MATCH_VAESDM_VS): New. (MASK_VAESDM_VS): New. (MATCH_VAESDM_VV): New. (MASK_VAESDM_VV): New. (MATCH_VAESEF_VS): New. (MASK_VAESEF_VS): New. (MATCH_VAESEF_VV): New. (MASK_VAESEF_VV): New. (MATCH_VAESEM_VS): New. (MASK_VAESEM_VS): New. (MATCH_VAESEM_VV): New. (MASK_VAESEM_VV): New. (MATCH_VAESKF1_VI): New. (MASK_VAESKF1_VI): New. (MATCH_VAESKF2_VI): New. (MASK_VAESKF2_VI): New. (MATCH_VAESZ_VS): New. (MASK_VAESZ_VS): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkned. opcodes/ChangeLog: * riscv-opc.c: Add Zvkned instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner1-0/+5
Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkg. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkg.d: New test. * testsuite/gas/riscv/zvkg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VGHSH_VV): New. (MASK_VGHSH_VV): New. (MATCH_VGMUL_VV): New. (MASK_VGMUL_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkg. opcodes/ChangeLog: * riscv-opc.c: Add Zvkg instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry1-0/+5
Zvbc is part of the crypto vector extensions. This extension adds the following instructions: - vclmul.[vv,vx] - vclmulh.[vv,vx] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbc. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvbc.d: New test. * testsuite/gas/riscv/zvbc.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VCLMUL_VV): New. (MASK_VCLMUL_VV): New. (MATCH_VCLMUL_VX): New. (MASK_VCLMUL_VX): New. (MATCH_VCLMULH_VV): New. (MASK_VCLMULH_VV): New. (MATCH_VCLMULH_VX): New. (MASK_VCLMULH_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvbc. opcodes/ChangeLog: * riscv-opc.c: Add Zvbc instruction. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+5
Zvbb is part of the vector crypto extensions. This extension adds the following instructions: - vandn.[vv,vx] - vbrev.v - vbrev8.v - vrev8.v - vclz.v - vctz.v - vcpop.v - vrol.[vv,vx] - vror.[vv,vx,vi] - vwsll.[vv,vx,vi] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbb. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format string directive. (riscv_ip): Likewise. * testsuite/gas/riscv/zvbb.d: New test. * testsuite/gas/riscv/zvbb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VANDN_VV): New. (MASK_VANDN_VV): New. (MATCH_VANDN_VX): New. (MASK_VANDN_VX): New. (MATCH_VBREV8_V): New. (MASK_VBREV8_V): New. (MATCH_VBREV_V): New. (MASK_VBREV_V): New. (MATCH_VCLZ_V): New. (MASK_VCLZ_V): New. (MATCH_VCPOP_V): New. (MASK_VCPOP_V): New. (MATCH_VCTZ_V): New. (MASK_VCTZ_V): New. (MATCH_VREV8_V): New. (MASK_VREV8_V): New. (MATCH_VROL_VV): New. (MASK_VROL_VV): New. (MATCH_VROL_VX): New. (MASK_VROL_VX): New. (MATCH_VROR_VI): New. (MASK_VROR_VI): New. (MATCH_VROR_VV): New. (MASK_VROR_VV): New. (MATCH_VROR_VX): New. (MASK_VROR_VX): New. (MATCH_VWSLL_VI): New. (MASK_VWSLL_VI): New. (MATCH_VWSLL_VV): New. (MASK_VWSLL_VV): New. (MATCH_VWSLL_VX): New. (MASK_VWSLL_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New. (ENCODE_RVV_VI_UIMM6): New. (enum riscv_insn_class): Add instruction class for Zvbb. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add 'l' as new format string directive. * riscv-opc.c: Add Zvbb instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01Automatic date update in version.inGDB Administrator1-1/+1
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+39
This patch adds support for the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of FP registers in case XLEN < FLEN * fleq/fltq (quiet comparison instructions) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) This patch is based on an earlier version from Tsukasa OI: https://sourceware.org/pipermail/binutils/2022-September/122939.html Most significant change to that commit is the switch from the rs1-field value to the actual floating-point value in the last operand of the fli* instructions. Everything that strtof() can parse is accepted and the '%a' printf specifier is used to output hex floating-point literals in the disassembly. The Zfa specification is frozen (and has passed public review). It is available as a chapter in "The RISC-V Instruction Set Manual: Volume 1": https://github.com/riscv/riscv-isa-manual/releases bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for 'Zfa' extension. (riscv_multi_subset_supports_ext): Likewise. (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. gas/ChangeLog: * config/tc-riscv.c (flt_lookup): New helper to lookup a float value in an array. (validate_riscv_insn): Add 'Wfv' as new format string directive. (riscv_ip): Likewise. * doc/c-riscv.texi: Add floating-point chapter and describe limiations of the Zfa FP literal parsing. * testsuite/gas/riscv/zfa-32.d: New test. * testsuite/gas/riscv/zfa-32.s: New test. * testsuite/gas/riscv/zfa-64.d: New test. * testsuite/gas/riscv/zfa-64.s: New test. * testsuite/gas/riscv/zfa-fail.d: New test. * testsuite/gas/riscv/zfa-fail.l: New test. * testsuite/gas/riscv/zfa-fail.s: New test. * testsuite/gas/riscv/zfa.d: New test. * testsuite/gas/riscv/zfa.s: New test. * testsuite/gas/riscv/zfa.s: New test. * opcode/riscv-opc.h (MATCH_FLI_H): New. (MASK_FLI_H): New. (MATCH_FMINM_H): New. (MASK_FMINM_H): New. (MATCH_FMAXM_H): New. (MASK_FMAXM_H): New. (MATCH_FROUND_H): New. (MASK_FROUND_H): New. (MATCH_FROUNDNX_H): New. (MASK_FROUNDNX_H): New. (MATCH_FLTQ_H): New. (MASK_FLTQ_H): New. (MATCH_FLEQ_H): New. (MASK_FLEQ_H): New. (MATCH_FLI_S): New. (MASK_FLI_S): New. (MATCH_FMINM_S): New. (MASK_FMINM_S): New. (MATCH_FMAXM_S): New. (MASK_FMAXM_S): New. (MATCH_FROUND_S): New. (MASK_FROUND_S): New. (MATCH_FROUNDNX_S): New. (MASK_FROUNDNX_S): New. (MATCH_FLTQ_S): New. (MASK_FLTQ_S): New. (MATCH_FLEQ_S): New. (MASK_FLEQ_S): New. (MATCH_FLI_D): New. (MASK_FLI_D): New. (MATCH_FMINM_D): New. (MASK_FMINM_D): New. (MATCH_FMAXM_D): New. (MASK_FMAXM_D): New. (MATCH_FROUND_D): New. (MASK_FROUND_D): New. (MATCH_FROUNDNX_D): New. (MASK_FROUNDNX_D): New. (MATCH_FLTQ_D): New. (MASK_FLTQ_D): New. (MATCH_FLEQ_D): New. (MASK_FLEQ_D): New. (MATCH_FLI_Q): New. (MASK_FLI_Q): New. (MATCH_FMINM_Q): New. (MASK_FMINM_Q): New. (MATCH_FMAXM_Q): New. (MASK_FMAXM_Q): New. (MATCH_FROUND_Q): New. (MASK_FROUND_Q): New. (MATCH_FROUNDNX_Q): New. (MASK_FROUNDNX_Q): New. (MATCH_FLTQ_Q): New. (MASK_FLTQ_Q): New. (MATCH_FLEQ_Q): New. (MASK_FLEQ_Q): New. (MATCH_FCVTMOD_W_D): New. (MASK_FCVTMOD_W_D): New. (MATCH_FMVH_X_D): New. (MASK_FMVH_X_D): New. (MATCH_FMVH_X_Q): New. (MASK_FMVH_X_Q): New. (MATCH_FMVP_D_X): New. (MASK_FMVP_D_X): New. (MATCH_FMVP_Q_X): New. (MASK_FMVP_Q_X): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction classes for the Zfa extension. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add support for new format string directive 'Wfv'. * riscv-opc.c: Add Zfa instructions. Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-30Fix used-before-initialized warnings when compiling elf.c with Clang-16.Nick Clifton1-2/+4
2023-06-30Automatic date update in version.inGDB Administrator1-1/+1
2023-06-29sframe: bfd: gas: ld: format bump to SFrame version 2Indu Bhagat2-19/+37
SFrame version 2 encodes the size of repetitive insn block explicitly in the format. Add information in the SFrame FDE to convey the size of the block of repeating instructions. This information is used only for SFrame FDEs of type SFRAME_FDE_TYPE_PCMASK. Introduce two extra bytes for padding: this ensures that the memory accesses to the members of the SFrame Frame Descriptor Entry (FDE) are naturally aligned. gas generates SFrame section with version SFRAME_VERSION_2 by default. libsframe provides two new APIs to: - get an SFrame FDE data from the decoder context, and - add an SFrame FDE to the encoder context. The additional argument (for rep_block_size) is useful for SFrame FDEs where FDE type is SFRAME_FDE_TYPE_PCMASK. The linker will generate the output SFrame sections in the SFRAME_VERSION_2 format. If the input sections offered to the linker are not all in the SFRAME_VERSION_2 format, the linker issues an error to the user. objdump/readelf will show the following message to the user if .sframe section in SFRAME_VERSION_1 format is seen: "No further information can be displayed. SFrame version not supported." In other words, like the rest of the binutils, only the current SFrame format version, i.e., SFRAME_VERSION_2 is supported by the textual dump facilities. bfd/ * elf-sframe.c (_bfd_elf_merge_section_sframe): Generate an output SFrame section with version SFRAME_VERSION_2. Also, error out if the SFrame sections do not all have SFRAME_VERSION_2. * elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Generate SFrame section for plt entries with version SFRAME_VERSION_2. gas/ * gen-sframe.c (sframe_set_version): Update to SFRAME_VERSION_2. (output_sframe): Likewise. gas/testsuite/ * gas/cfi-sframe/cfi-sframe-aarch64-1.d: Use SFRAME_VERSION_2. * gas/cfi-sframe/cfi-sframe-aarch64-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-1.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-3.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-4.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-5.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-6.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-7.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-8.d: Likewise. * gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise. * gas/cfi-sframe/common-empty-1.d: Likewise. * gas/cfi-sframe/common-empty-2.d: Likewise. * gas/cfi-sframe/common-empty-3.d: Likewise. ld/testsuite/ * ld-aarch64/sframe-simple-1.d: Adjust for SFRAME_VERSION_2. * ld-x86-64/sframe-plt-1.d: Likewise. * ld-x86-64/sframe-simple-1.d: Likewise. libsframe/ * libsframe.ver: Add the new APIs. * sframe.c (sframe_decoder_get_funcdesc_v2): New definition. (sframe_encoder_add_funcdesc_v2): Likewise. (sframe_header_sanity_check_p): Include SFRAME_VERSION_2. (sframe_fre_check_range_p): Get rep_block_size info from SFrame FDE. * sframe-dump.c (dump_sframe_header): Add support for SFRAME_VERSION_2. (dump_sframe): Inform user if SFrame section in SFRAME_VERSION_1 format is seen. libsframe/testsuite/ * libsframe.decode/DATA-BE: Regenerated data file. * libsframe.decode/DATA1: Likewise. * libsframe.decode/DATA2: Likewise. * libsframe.find/plt-findfre-1.c: Use new API in the testcase. include/ * sframe.h: Add member to encode size of the code block of repeating instructions. Add 2 bytes of padding. * sframe-api.h (sframe_decoder_get_funcdesc_v2): New declaration. (sframe_encoder_add_funcdesc_v2): Likewise.
2023-06-29bfd: Improve nm and objdump without section headerH.J. Lu4-65/+746
When there is no section header in an executable or shared library, we reconstruct dynamic symbol table from the PT_DYNAMIC segment, which contains DT_HASH/DT_GNU_HASH/DT_MIPS_XHASH, DT_STRTAB, DT_SYMTAB, DT_STRSZ, and DT_SYMENT entries, to improve nm and objdump. For DT_HASH, the number of dynamic symbol table entries equals the number of chains. For DT_GNU_HASH/DT_MIPS_XHASH, only defined symbols with non-STB_LOCAL indings are in hash table. Since DT_GNU_HASH/DT_MIPS_XHASH place all symbols with STB_LOCAL binding before symbols with other bindings and all undefined symbols defined ones in dynamic symbol table, the highest symbol index in DT_GNU_HASH/DT_MIPS_XHASH is the highest dynamic symbol table index. We can also get symbol version from DT_VERSYM, DT_VERDEF and DT_VERNEED entries. dt_symtab, dt_versym, dt_verdef, dt_verneed, dt_symtab_count, dt_verdef_count, dt_verneed_count and dt_strtab are added to elf_obj_tdata to store dynamic symbol table information. PR ld/25617 * elf-bfd.h (elf_obj_tdata): Add dt_symtab, dt_verdef, dt_verneed, dt_symtab_count, dt_verdef_count, dt_verneed_count and dt_strtab. (elf_use_dt_symtab_p): New. (_bfd_elf_get_dynamic_symbols): Likewise. (_bfd_elf_get_section_from_dynamic_symbol): Likewise. * elf.c (bfd_elf_get_elf_syms): Use dynamic symbol table if neeeded. (_bfd_elf_get_dynamic_symtab_upper_bound): Likewise. (_bfd_elf_slurp_version_tables): Likewise. (offset_from_vma): New function. (get_hash_table_data): Likewise. (_bfd_elf_get_dynamic_symbols): Likewise. (_bfd_elf_get_section_from_dynamic_symbol): Likewise. (_bfd_elf_get_symbol_version_name): Likewise. * elfcode.h (elf_object_p): Call _bfd_elf_get_dynamic_symbols to reconstruct dynamic symbol table from PT_DYNAMIC segment if there is no section header. (elf_slurp_symbol_table): Use dynamic symbol table if neeeded. Don't free isymbuf when dynamic symbol table is used. * elflink.c (elf_link_is_defined_archive_symbol): Return wrong format error when dynamic symbol table is used. (elf_link_add_object_symbols): Likewise.
2023-06-29ELF: Discard non-alloc sections without section headerH.J. Lu1-3/+10
Discard non-alloc sections when section headers are stripped. bfd/ PR ld/25617 * elf.c (_bfd_elf_assign_file_positions_for_non_load): Skip non-load sections without section header. (_bfd_elf_write_object_contents): Don't set the sh_name field without section header. Write out the .shstrtab section only if its sh_offset field isn't -1. binutils/ PR ld/25617 * objcopy.c (is_strip_section_1): Remove non-alloc sections for --strip-section-headers. ld/ PR ld/25617 * ldlang.c (lang_discard_section_p): Discard non-alloc sections if we are stripping section headers.
2023-06-29ELF: Strip section header in ELF objectsKaylee Blake4-14/+38
Section header isn't mandatory on ELF executable nor shared library. This patch adds a new linker option, -z nosectionheader, to omit ELF section header, a new objcopy and strip option, --strip-section-headers, to remove ELF section headers. bfd/ 2023-06-06 H.J. Lu <hongjiu.lu@intel.com> Kaylee Blake <klkblake@gmail.com> PR ld/25617 * bfd.c (BFD_NO_SECTION_HEADER): New. (BFD_FLAGS_SAVED): Add BFD_NO_SECTION_HEADER. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. * elfcode.h (elf_swap_ehdr_out): Omit section header with BFD_NO_SECTION_HEADER. (elf_write_shdrs_and_ehdr): Likewise. * elfxx-target.h (TARGET_BIG_SYM): Add BFD_NO_SECTION_HEADER to object_flags. (TARGET_LITTLE_SYM): Likewise. * bfd-in2.h: Regenerated. binutils/ 2023-06-06 H.J. Lu <hongjiu.lu@intel.com> PR ld/25617 * NEWS: Mention --strip-section-headers for objcopy and strip. * objcopy.c (strip_section_headers): New. (command_line_switch): Add OPTION_STRIP_SECTION_HEADERS. (strip_options): Add --strip-section-headers. (copy_options): Likewise. (copy_usage): Add --strip-section-headers. (strip_usage): Likewise. (copy_object): Handle --strip-section-headers for ELF files. (strip_main): Handle OPTION_STRIP_SECTION_HEADERS. (copy_main): Likewise. * doc/binutils.texi: Document --strip-section-headers for objcopy and strip. ld/ 2023-06-06 H.J. Lu <hongjiu.lu@intel.com> Kaylee Blake <klkblake@gmail.com> PR ld/25617 * NEWS: Mention -z nosectionheader. * emultempl/elf.em: Support -z sectionheader and -z nosectionheader. * ld.h (ld_config_type): Add no_section_header. * ld.texi: Document -z sectionheader and -z nosectionheader. * ldlang.c (ldlang_open_output): Handle config.no_section_header. * lexsup.c (parse_args): Enable --strip-all with -z nosectionheader. Disallow -r with -z nosectionheader. (elf_static_list_options): Add -z sectionheader and -z nosectionheader.
2023-06-29Automatic date update in version.inGDB Administrator1-1/+1
2023-06-28LoongArch: Add R_LARCH_64_PCREL relocation supportmengqinggang5-0/+24
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared to emit R_LARCH_64_PCREL. The LoongArch ABI at here: https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc bfd/ChangeLog: * bfd-in2.h (not): Add R_LARCH_64_PCREL * elfnn-loongarch.c (perform_relocation): Likewise. * elfxx-loongarch.c: Likewise. * libbfd.h: Likewise. * reloc.c: Likewise. gas/ChangeLog: * config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper): (md_apply_fix): Add R_LARCH_64_PCREL. * testsuite/gas/loongarch/64_pcrel.d: New test. * testsuite/gas/loongarch/64_pcrel.s: New test. include/ChangeLog: * elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL. ld/ChangeLog: * testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. * testsuite/ld-loongarch-elf/64_pcrel.d: New test. * testsuite/ld-loongarch-elf/64_pcrel.s: New test.
2023-06-28Automatic date update in version.inGDB Administrator1-1/+1
2023-06-27libsframe: bfd: use uint32_t for return type of get_num_fidx APIsIndu Bhagat1-3/+3
Keep the data types usage in libsframe look consistent. bfd/ * elf-sframe.c (_bfd_elf_merge_section_sframe): Use uint32_t type alias. * libsframe/sframe.c (sframe_decoder_get_funcdesc_at_index): Likewise. (sframe_decoder_get_num_fidx): Likewise. (sframe_encoder_get_num_fidx): Likewise. include/ * sframe-api.h (sframe_decoder_get_num_fidx): Likewise. (sframe_encoder_get_num_fidx): Likewise.
2023-06-27libsframe: use uint8_t instead of unsigned char for abi_archIndu Bhagat1-1/+1
Use uint8_t consistently for identifying ABI/arch in SFrame format. bfd/ * elf-sframe.c (_bfd_elf_merge_section_sframe): libsframe/ * sframe-dump.c (is_sframe_abi_arch_aarch64): Use uint8_t for local variable. * sframe.c (sframe_decoder_get_abi_arch): Update return type to uint8_t. (sframe_encoder_get_abi_arch): Likewise. include/ * sframe-api.h (sframe_decoder_get_abi_arch): Likewise. (sframe_encoder_get_abi_arch): Likewise.
2023-06-27libsframe: bfd: use uint32_t for return type of sframe_calc_fre_typeIndu Bhagat1-1/+1
Use uint32_t type alias consistently for all APIs in libsframe. bfd/ * elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Adjust for the changed return type. libsframe/ * sframe.c (sframe_calc_fre_type): Use uint32_t for return type. include/ * sframe-api.h (sframe_calc_fre_type): Likewise.
2023-06-27 RISC-V: Support Zicond extensionPhilipp Tomsich1-0/+5
This implements the Zicond (conditional integer operations) extension, as of version 1.0-rc2. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf for the proposed specification and usage details. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Recognize INSN_CLASS_ZICOND. (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND. gas/ChangeLog: * testsuite/gas/riscv/zicond.d: New test. * testsuite/gas/riscv/zicond.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define. (MASK_CZERO_EQZ): Define. (MATCH_CZERO_NEZ): Define, (MASK_CZERO_NEZ): Define. (DECLARE_INSN): Add czero.eqz and czero.nez. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICOND. opcodes/ChangeLog: * riscv-opc.c: Add czero.eqz and czero.nez. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-06-27Automatic date update in version.inGDB Administrator1-1/+1
2023-06-26Automatic date update in version.inGDB Administrator1-1/+1
2023-06-25Automatic date update in version.inGDB Administrator1-1/+1
2023-06-24Automatic date update in version.inGDB Administrator1-1/+1
2023-06-23Automatic date update in version.inGDB Administrator1-1/+1
2023-06-22Automatic date update in version.inGDB Administrator1-1/+1
2023-06-21x86: Free the symbol buffer and the relocation buffer after useH.J. Lu1-14/+28
When --no-keep-memory is used, the symbol buffer and the relocation buffer aren't cached. When packing relative relocations, we may allocate a new symbol buffer and a new relocation buffer for each eligible section in an object file. If there are many sections, memory may be exhausted. In this case, we should free the symbol buffer and the relocation buffer after use. If symbol buffer entries are used to track relative relocations against local symbols for later use, the symbol buffer should be cached. PR ld/30566 * elfxx-x86.c (elf_x86_relative_reloc_record_add): Add an argument to inform caller if the symbol buffer should be kept. (_bfd_x86_elf_link_relax_section): Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. Free the symbol buffer and the relocation buffer after use. Cache the symbol buffer if it is used.
2023-06-21elf32_arm_get_synthetic_symtab memory leakAlan Modra1-15/+10
ARM get_synthetic_symtab reads .plt and caches that data. Caching the data doesn't make a lot of sense since get_synthetic_symtab is only called once per bfd, and the memory might be put to better use. It also leaks on closing the bfd. * elf32-arm.c (elf32_arm_get_synthetic_symtab): Don't cache plt contents. Free plt data before returning.
2023-06-21macho-o.c don't leak strtabAlan Modra1-0/+2
* mach-o.c (bfd_mach_o_write_symtab_content): Free strtab on success path.
2023-06-21Automatic date update in version.inGDB Administrator1-1/+1
2023-06-20Don't segfault in mips reloc special_functionsAlan Modra4-13/+30
A symbol defined in a section from a shared library will have a NULL section->output_section during linking. * elf32-mips.c (gprel32_with_gp): Don't segfault on NULL symbol->section->output_section. * elf64-mips.c (mips_elf64_gprel32_reloc): Likewise. * elfn32-mips.c (mips_elf_gprel16_reloc): Likewise. (mips_elf_literal_reloc, mips_elf_gprel32_reloc): Likewise. (gprel32_with_gp, mips16_gprel_reloc): Likewise. * elfxx-mips.c (_bfd_mips_elf_gprel16_with_gp): Likewise. (_bfd_mips_elf_generic_reloc): Likewise.
2023-06-20Automatic date update in version.inGDB Administrator1-1/+1
2023-06-19Fix illegal memory access implementing relocs in a fuzzed x86_64 object file.Nick Clifton2-0/+21
PR 30560 * elf64-x86-64.c (elf_x86_64_relocate_section): Add more checks for a valid relocation offset.
2023-06-19Automatic date update in version.inGDB Administrator1-1/+1
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