RISC-V: Add support for the Zvbb ISA extension

Zvbb is part of the vector crypto extensions.

This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvbb.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format
	string directive.
	(riscv_ip): Likewise.
	* testsuite/gas/riscv/zvbb.d: New test.
	* testsuite/gas/riscv/zvbb.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VANDN_VV): New.
	(MASK_VANDN_VV): New.
	(MATCH_VANDN_VX): New.
	(MASK_VANDN_VX): New.
	(MATCH_VBREV8_V): New.
	(MASK_VBREV8_V): New.
	(MATCH_VBREV_V): New.
	(MASK_VBREV_V): New.
	(MATCH_VCLZ_V): New.
	(MASK_VCLZ_V): New.
	(MATCH_VCPOP_V): New.
	(MASK_VCPOP_V): New.
	(MATCH_VCTZ_V): New.
	(MASK_VCTZ_V): New.
	(MATCH_VREV8_V): New.
	(MASK_VREV8_V): New.
	(MATCH_VROL_VV): New.
	(MASK_VROL_VV): New.
	(MATCH_VROL_VX): New.
	(MASK_VROL_VX): New.
	(MATCH_VROR_VI): New.
	(MASK_VROR_VI): New.
	(MATCH_VROR_VV): New.
	(MASK_VROR_VV): New.
	(MATCH_VROR_VX): New.
	(MASK_VROR_VX): New.
	(MATCH_VWSLL_VI): New.
	(MASK_VWSLL_VI): New.
	(MATCH_VWSLL_VV): New.
	(MASK_VWSLL_VV): New.
	(MATCH_VWSLL_VX): New.
	(MASK_VWSLL_VX): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.
	(ENCODE_RVV_VI_UIMM6): New.
	(enum riscv_insn_class): Add instruction class for Zvbb.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add 'l' as new format string
	directive.
	* riscv-opc.c: Add Zvbb instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

1 files changed, 5 insertions, 0 deletions

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 497709e..21a4dc8 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1262,6 +1262,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64x",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2427,6 +2428,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve64d")
 	      || riscv_subset_supports (rps, "zve64f")
 	      || riscv_subset_supports (rps, "zve32f"));
+    case INSN_CLASS_ZVBB:
+      return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2615,6 +2618,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64x' or `zve32x");
     case INSN_CLASS_ZVEF:
       return _("v' or `zve64d' or `zve64f' or `zve32f");
+    case INSN_CLASS_ZVBB:
+      return _("zvbb");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H: