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-rw-r--r--sim/testsuite/riscv/m-ext.s18
1 files changed, 18 insertions, 0 deletions
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 0000000..b80bd14
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# Check that the RV32M instructions run without any faults.
+# mach: riscv
+
+.include "testutils.inc"
+
+ start
+
+ .option arch, +m
+ mul x0, x1, x2
+ mulh x0, x1, x2
+ mulhu x0, x1, x2
+ mulhsu x0, x1, x2
+ div x0, x1, x2
+ divu x0, x1, x2
+ rem x0, x1, x2
+ remu x0, x1, x2
+
+ pass