diff options
Diffstat (limited to 'sim/testsuite/riscv')
-rw-r--r-- | sim/testsuite/riscv/allinsn.exp | 2 | ||||
-rw-r--r-- | sim/testsuite/riscv/c-ext.s | 95 | ||||
-rw-r--r-- | sim/testsuite/riscv/jalr.s | 2 | ||||
-rw-r--r-- | sim/testsuite/riscv/m-ext.s | 2 | ||||
-rw-r--r-- | sim/testsuite/riscv/pass.s | 2 |
5 files changed, 99 insertions, 4 deletions
diff --git a/sim/testsuite/riscv/allinsn.exp b/sim/testsuite/riscv/allinsn.exp index 972edf4..9d45403 100644 --- a/sim/testsuite/riscv/allinsn.exp +++ b/sim/testsuite/riscv/allinsn.exp @@ -3,7 +3,7 @@ sim_init # all machines -set all_machs "riscv" +set all_machs "riscv32 riscv64" foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { # If we're only testing specific files and this isn't one of them, skip it. diff --git a/sim/testsuite/riscv/c-ext.s b/sim/testsuite/riscv/c-ext.s new file mode 100644 index 0000000..ad6e7b2 --- /dev/null +++ b/sim/testsuite/riscv/c-ext.s @@ -0,0 +1,95 @@ +# Basic Tests for C extension. +# mach: riscv32 riscv64 +# sim(riscv32): --model RV32IC +# sim(riscv64): --model RV64IC +# ld(riscv32): -m elf32lriscv +# ld(riscv64): -m elf64lriscv +# as(riscv32): -march=rv32ic +# as(riscv64): -march=rv64ic + +.include "testutils.inc" + + .data + .align 4 +_data: + .word 1234 + .word 0 + + start + la a0, _data + + # Test load-store instructions. + c.lw a1,0(a0) + c.sw a1,4(a0) + c.lw a2,4(a0) + + li a5,1234 + bne a1,a5,test_fail + bne a2,a5,test_fail + + # Test basic arithmetic. + c.li a0,0 + c.li a1,1 + c.addi a0,1 + c.addi a0,-1 + c.add a0,a1 + c.sub a0,a1 + + li a5,1 + bne a0,x0,test_fail + bne a1,a5,test_fail + + # Test logical operations. + c.li a0,7 + c.li a1,7 + c.li a2,4 + c.li a3,3 + c.li a4,3 + c.andi a0,3 + c.and a1,a0 + c.or a2,a3 + c.xor a4,a4 + + li a5,3 + bne a0,a5,test_fail + bne a1,a5,test_fail + bne a4,x0,test_fail + li a5,7 + bne a2,a5,test_fail + + # Test shift operations. + c.li a0,4 + c.li a1,4 + c.slli a0,1 + c.srli a1,1 + + li a5,8 + bne a0,a5,test_fail + li a5,2 + bne a1,a5,test_fail + + # Test jump instruction. + c.j 1f + + j test_fail +1: + la a0,2f + + # Test jump register instruction. + c.jr a0 + + j test_fail + +2: + # Test branch instruction. + c.li a0,1 + c.beqz a0,test_fail + c.li a0,0 + c.bnez a0,test_fail + +test_pass: + pass + fail + +test_fail: + fail diff --git a/sim/testsuite/riscv/jalr.s b/sim/testsuite/riscv/jalr.s index daccf4f..294f485 100644 --- a/sim/testsuite/riscv/jalr.s +++ b/sim/testsuite/riscv/jalr.s @@ -1,5 +1,5 @@ # Basic jalr tests. -# mach: riscv +# mach: riscv32 riscv64 .include "testutils.inc" diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s index b80bd14..4247156 100644 --- a/sim/testsuite/riscv/m-ext.s +++ b/sim/testsuite/riscv/m-ext.s @@ -1,5 +1,5 @@ # Check that the RV32M instructions run without any faults. -# mach: riscv +# mach: riscv32 riscv64 .include "testutils.inc" diff --git a/sim/testsuite/riscv/pass.s b/sim/testsuite/riscv/pass.s index bd428ca..a188b83 100644 --- a/sim/testsuite/riscv/pass.s +++ b/sim/testsuite/riscv/pass.s @@ -1,5 +1,5 @@ # check that the sim doesn't die immediately. -# mach: riscv +# mach: riscv32 riscv64 .include "testutils.inc" |