diff options
Diffstat (limited to 'sim/testsuite/frv/mqcpxru.cgs')
| -rw-r--r-- | sim/testsuite/frv/mqcpxru.cgs | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/sim/testsuite/frv/mqcpxru.cgs b/sim/testsuite/frv/mqcpxru.cgs new file mode 100644 index 0000000..45e1b35 --- /dev/null +++ b/sim/testsuite/frv/mqcpxru.cgs @@ -0,0 +1,78 @@ +# frv testcase for mqcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxru +mqcpxru: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 3,1,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 1,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 2,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffd,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 4,0x0001,fr10 + set_fr_iimmed 0x8000,1,fr9 ; 17 bit result + set_fr_iimmed 4,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0001ffff,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0x0001,fr9 ; saturation + set_fr_iimmed 0xffff,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr8 ; saturation + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xfffe,0xffff,fr9 ; saturation + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass |