diff options
Diffstat (limited to 'sim/testsuite/frv/mcmpuh.cgs')
| -rw-r--r-- | sim/testsuite/frv/mcmpuh.cgs | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/sim/testsuite/frv/mcmpuh.cgs b/sim/testsuite/frv/mcmpuh.cgs new file mode 100644 index 0000000..a6670b7 --- /dev/null +++ b/sim/testsuite/frv/mcmpuh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpuh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpuh +mcmpuh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass |