diff options
Diffstat (limited to 'sim/testsuite/bfin/c_dsp32shift_ones.s')
| -rw-r--r-- | sim/testsuite/bfin/c_dsp32shift_ones.s | 214 |
1 files changed, 214 insertions, 0 deletions
diff --git a/sim/testsuite/bfin/c_dsp32shift_ones.s b/sim/testsuite/bfin/c_dsp32shift_ones.s new file mode 100644 index 0000000..4097777 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ones.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp +// Spec Reference: dsp32shift ones +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = ONES R0; +R1.L = ONES R0; +R2.L = ONES R0; +R3.L = ONES R0; +R4.L = ONES R0; +R5.L = ONES R0; +R6.L = ONES R0; +R0.L = ONES R0; +CHECKREG r1, 0x34560004; +CHECKREG r0, 0x88880004; +CHECKREG r2, 0x08000004; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08000004; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000004; +CHECKREG r7, 0x08000004; + +imm32 r0, 0x9999d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.L = ONES R1; +R7.L = ONES R1; +R2.L = ONES R1; +R3.L = ONES R1; +R4.L = ONES R1; +R5.L = ONES R1; +R6.L = ONES R1; +R1.L = ONES R1; +CHECKREG r0, 0x99990001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + + +imm32 r0, 0xaaaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = ONES R2; +R1.L = ONES R2; +R7.L = ONES R2; +R3.L = ONES R2; +R4.L = ONES R2; +R5.L = ONES R2; +R6.L = ONES R2; +R2.L = ONES R2; +CHECKREG r0, 0xAAAA000C; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0xAAAA000C; +CHECKREG r3, 0x0000000C; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x0000000C; +CHECKREG r6, 0x0000000C; +CHECKREG r7, 0x0000000C; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ONES R3; +R1.L = ONES R3; +R2.L = ONES R3; +R7.L = ONES R3; +R4.L = ONES R3; +R5.L = ONES R3; +R6.L = ONES R3; +R3.L = ONES R3; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x0000000D; +CHECKREG r2, 0x0000000D; +CHECKREG r3, 0xBBBB000D; +CHECKREG r4, 0x0000000D; +CHECKREG r5, 0x0000000D; +CHECKREG r6, 0x0000000D; +CHECKREG r7, 0x0000000D; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ONES R4; +R1.L = ONES R4; +R2.L = ONES R4; +R3.L = ONES R4; +R7.L = ONES R4; +R5.L = ONES R4; +R6.L = ONES R4; +R4.L = ONES R4; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x00010008; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030008; +CHECKREG r4, 0xCCCC0008; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x00060008; +CHECKREG r7, 0x00070008; + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xaddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ONES R5; +R1.L = ONES R5; +R2.L = ONES R5; +R3.L = ONES R5; +R4.L = ONES R5; +R7.L = ONES R5; +R6.L = ONES R5; +R5.L = ONES R5; +CHECKREG r0, 0xA001000B; +CHECKREG r1, 0xA001000B; +CHECKREG r2, 0xA002000B; +CHECKREG r3, 0xA003000B; +CHECKREG r4, 0xA004000B; +CHECKREG r5, 0xADDD000B; +CHECKREG r6, 0xA006000B; +CHECKREG r7, 0xA007000B; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = ONES R6; +R1.L = ONES R6; +R2.L = ONES R6; +R3.L = ONES R6; +R4.L = ONES R6; +R5.L = ONES R6; +R7.L = ONES R6; +R6.L = ONES R6; +CHECKREG r0, 0xB001000C; +CHECKREG r1, 0xB001000C; +CHECKREG r2, 0xB002000C; +CHECKREG r3, 0xB003000C; +CHECKREG r4, 0xB004000C; +CHECKREG r5, 0xB005000C; +CHECKREG r6, 0xEEEE000C; +CHECKREG r7, 0xB007000C; + +imm32 r0, 0xd0010001; +imm32 r1, 0xd0010002; +imm32 r2, 0xd0020003; +imm32 r3, 0xd0030014; +imm32 r4, 0xd0040005; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060007; +imm32 r7, 0xffff0000; +R0.L = ONES R7; +R1.L = ONES R7; +R2.L = ONES R7; +R3.L = ONES R7; +R4.L = ONES R7; +R5.L = ONES R7; +R6.L = ONES R7; +R7.L = ONES R7; + +CHECKREG r0, 0xD0010010; +CHECKREG r1, 0xD0010010; +CHECKREG r2, 0xD0020010; +CHECKREG r3, 0xD0030010; +CHECKREG r4, 0xD0040010; +CHECKREG r5, 0xD0050010; +CHECKREG r6, 0xD0060010; +CHECKREG r7, 0xFFFF0010; + +pass |