4 files changed, 52 insertions, 0 deletions
diff --git a/sim/or1k/cpu.c b/sim/or1k/cpu.c
index c75e2a0..14e43cc 100644
--- a/sim/or1k/cpu.c
+++ b/sim/or1k/cpu.c
@@ -1100,6 +1100,38 @@ or1k32bf_h_sys_esr15_set (SIM_CPU *current_cpu, USI newval)
   SET_H_SYS_ESR15 (newval);
 }
 
+/* Get the value of h-sys-coreid.  */
+
+USI
+or1k32bf_h_sys_coreid_get (SIM_CPU *current_cpu)
+{
+  return GET_H_SYS_COREID ();
+}
+
+/* Set a value for h-sys-coreid.  */
+
+void
+or1k32bf_h_sys_coreid_set (SIM_CPU *current_cpu, USI newval)
+{
+  SET_H_SYS_COREID (newval);
+}
+
+/* Get the value of h-sys-numcores.  */
+
+USI
+or1k32bf_h_sys_numcores_get (SIM_CPU *current_cpu)
+{
+  return GET_H_SYS_NUMCORES ();
+}
+
+/* Set a value for h-sys-numcores.  */
+
+void
+or1k32bf_h_sys_numcores_set (SIM_CPU *current_cpu, USI newval)
+{
+  SET_H_SYS_NUMCORES (newval);
+}
+
 /* Get the value of h-sys-gpr0.  */
 
 USI
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
index 7f8a340..ab2c062 100644
--- a/sim/or1k/cpu.h
+++ b/sim/or1k/cpu.h
@@ -408,6 +408,16 @@ SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR14), (x));\
 do { \
 SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR15), (x));\
 ;} while (0)
+#define GET_H_SYS_COREID() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_COREID))
+#define SET_H_SYS_COREID(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_COREID), (x));\
+;} while (0)
+#define GET_H_SYS_NUMCORES() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_NUMCORES))
+#define SET_H_SYS_NUMCORES(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_NUMCORES), (x));\
+;} while (0)
 #define GET_H_SYS_GPR0() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))
 #define SET_H_SYS_GPR0(x) \
 do { \
@@ -3379,6 +3389,10 @@ USI or1k32bf_h_sys_esr14_get (SIM_CPU *);
 void or1k32bf_h_sys_esr14_set (SIM_CPU *, USI);
 USI or1k32bf_h_sys_esr15_get (SIM_CPU *);
 void or1k32bf_h_sys_esr15_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_coreid_get (SIM_CPU *);
+void or1k32bf_h_sys_coreid_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_numcores_get (SIM_CPU *);
+void or1k32bf_h_sys_numcores_set (SIM_CPU *, USI);
 USI or1k32bf_h_sys_gpr0_get (SIM_CPU *);
 void or1k32bf_h_sys_gpr0_set (SIM_CPU *, USI);
 USI or1k32bf_h_sys_gpr1_get (SIM_CPU *);
diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c
index 2d1f7f8..73ab6f0 100644
--- a/sim/or1k/or1k.c
+++ b/sim/or1k/or1k.c
@@ -206,6 +206,10 @@ or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
 
   /* Clear the floating point control status register.  */
   SET_H_SYS_FPCSR (0);
+
+  /* Set this as the one and only core.  */
+  SET_H_SYS_NUMCORES (1);
+  SET_H_SYS_COREID (0);
 }
 
 void
diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c
index 753bfff..d1113ac 100644
--- a/sim/or1k/traps.c
+++ b/sim/or1k/traps.c
@@ -224,6 +224,8 @@ or1k32bf_mfspr (sim_cpu *current_cpu, USI addr)
     case SPR_ADDR (SYS, PPC):
     case SPR_ADDR (SYS, FPCSR):
     case SPR_ADDR (SYS, EPCR0):
+    case SPR_ADDR (SYS, COREID):
+    case SPR_ADDR (SYS, NUMCORES):
     case SPR_ADDR (MAC, MACLO):
     case SPR_ADDR (MAC, MACHI):
       break;