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-rw-r--r--opcodes/ChangeLog117
-rw-r--r--opcodes/Makefile.am5
-rw-r--r--opcodes/Makefile.in5
-rw-r--r--opcodes/arc-dis.c1364
-rw-r--r--opcodes/arc-dis.h80
-rw-r--r--opcodes/arc-ext.c259
-rw-r--r--opcodes/arc-ext.h62
-rw-r--r--opcodes/arc-opc.c1488
-rwxr-xr-xopcodes/configure2
-rw-r--r--opcodes/configure.in2
-rw-r--r--opcodes/disassemble.c3
-rw-r--r--opcodes/po/POTFILES.in1
-rw-r--r--opcodes/po/opcodes.pot36
13 files changed, 2736 insertions, 688 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1d6aaa6..9612b66 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,4 +1,19 @@
-Wed Jan 10 15:13:21 MET 2001 Jan Hubicka <jh@suse.cz>
+2001-01-11 Peter Targett <peter.targett@arccores.com>
+
+ * configure.in: Add arc-ext.lo for bfd_arc_arch selection.
+ * Makefile.am (C_FILES): Add arc-ext.c.
+ (ALL_MACHINES) Add arc-ext.lo.
+ (INCLUDES) Add opcode directory to list.
+ New dependency entry for arc-ext.lo.
+ * disassemble.c (disassembler): Correct call to
+ arc_get_disassembler.
+ * arc-opc.c: New update for ARC, including full base
+ instructions for ARC variants.
+ * arc-dis.h, arc-dis.c: New update for ARC, including
+ extensibility functionality.
+ * arc-ext.h, arc-ext.c: New files for handling extensibility.
+
+2001-01-10 Jan Hubicka <jh@suse.cz>
* i386-dis.c (PREGRP15 - PREGRP24): New.
(dis386_twobyt): Add SSE2 instructions.
@@ -29,7 +44,7 @@ Wed Jan 10 15:13:21 MET 2001 Jan Hubicka <jh@suse.cz>
* cgen-dis.in (print_insn_normal): Ditto.
* cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
-Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
+2001-01-05 Jan Hubicka <jh@suse.cz>
* i386-dis.c: Add x86_64 support.
(rex): New static variable.
@@ -249,7 +264,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* m32r-desc.h: Regenerate.
* m32r-ibld.c: Regenerate.
-2000-10-05 Jim Wilson <wilson@cygnus.com>
+2000-10-05 Jim Wilson <wilson@redhat.com>
* ia64-ic.tbl: Update from Intel.
* ia64-asmtab.c: Regenerate.
@@ -273,7 +288,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
New.
* disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
-2000-09-22 Jim Wilson <wilson@cygnus.com>
+2000-09-22 Jim Wilson <wilson@redhat.com>
* ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
gt, ge, ngt, and nge.
@@ -342,7 +357,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
instructions. Added extended mnemonic mftbl as defined in the
405GP manual for all PPCs.
-2000-08-28 Jim Wilson <wilson@cygnus.com>
+2000-08-28 Jim Wilson <wilson@redhat.com>
* ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
call. Change last goto to use failed instead of done.
@@ -388,7 +403,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* z8k-dis.c: Fix formatting.
-2000-08-16 Jim Wilson <wilson@cygnus.com>
+2000-08-16 Jim Wilson <wilson@redhat.com>
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
@@ -398,16 +413,16 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
-2000-08-15 Jim Wilson <wilson@cygnus.com>
+2000-08-15 Jim Wilson <wilson@redhat.com>
* ia64-ic.tbl: Add missing entries.
-2000-08-08 Jason Eckhardt <jle@cygnus.com>
+2000-08-08 Jason Eckhardt <jle@redhat.com>
* i860-dis.c (print_br_address): Change third argument from int
to long.
-2000-08-07 Richard Henderson <rth@cygnus.com>
+2000-08-07 Richard Henderson <rth@redhat.com>
* ia64-dis.c (print_insn_ia64): Get byte skip count correct
for MLI templates. Handle IA64_OPND_TGT64.
@@ -417,7 +432,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
* cgen.sh: Likewise.
-2000-08-02 Jim Wilson <wilson@cygnus.com>
+2000-08-02 Jim Wilson <wilson@redhat.com>
* ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
@@ -454,7 +469,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
ATTRIBUTE_UNUSED.
(cgen_parse_keyword): Ditto.
-2000-07-22 Jason Eckhardt <jle@cygnus.com>
+2000-07-22 Jason Eckhardt <jle@redhat.com>
* i860-dis.c: New file.
(print_insn_i860): New function.
@@ -494,7 +509,7 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
* sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
Reported by Bill Clarke <llib@computer.org>.
-2000-07-09 Geoffrey Keating <geoffk@cygnus.com>
+2000-07-09 Geoffrey Keating <geoffk@redhat.com>
* ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
Patch by Randall J Fisher <rfisher@ecn.purdue.edu>.
@@ -574,11 +589,11 @@ Fri Jan 5 11:31:07 MET 2001 Jan Hubicka <jh@suse.cz>
(bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
correctly.
-Fri Jun 9 21:49:02 2000 Denis Chertykov <denisc@overta.ru>
+2000-06-09 Denis Chertykov <denisc@overta.ru>
* avr-dis.c (avr_operand): Bugfix for jmp/call address.
-Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
+2000-06-07 Denis Chertykov <denisc@overta.ru>
* avr-dis.c: completely rewritten.
@@ -593,12 +608,12 @@ Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
(bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
correctly. Fix a typo.
-2000-05-31 Nick Clifton <nickc@cygnus.com>
+2000-05-31 Nick Clifton <nickc@redhat.com>
* opintl.h (_(String)): Explain why dgettext is used instead of
gettext.
-2000-05-30 Nick Clifton <nickc@cygnus.com>
+2000-05-30 Nick Clifton <nickc@redhat.com>
* opintl.h (gettext, dgettext, dcgettext, textdomain,
bindtextdomain): Replace defines with those from intl/libgettext.h
@@ -609,21 +624,21 @@ Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
* Makefile.am: Update dependencies with "make dep-am"
* Makefile.in: Regenerate.
-Thu May 25 22:53:20 2000 Alexandre Oliva <aoliva@cygnus.com>
+2000-05-25 Alexandre Oliva <aoliva@redhat.com>
* m10300-dis.c (disassemble): Don't assume 32-bit longs when
sign-extending operands.
-Mon May 15 15:18:07 2000 Donald Lindsay <dlindsay@cygnus.com>
+2000-05-15 Donald Lindsay <dlindsay@redhat.com>
* d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
except brf's.
-2000-05-21 Nick Clifton <nickc@cygnus.com>
+2000-05-21 Nick Clifton <nickc@redhat.com>
* Makefile.am (LIBIBERTY): Define.
-Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
+2000-05-19 Diego Novillo <dnovillo@redhat.com>
* mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
(STD_REGISTER_NAMES): New name for REGISTER_NAMES.
@@ -639,7 +654,7 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
* m32r-desc.h: Ditto.
-2000-05-15 Nick Clifton <nickc@cygnus.com>
+2000-05-15 Nick Clifton <nickc@redhat.com>
* arm-opc.h: Use upper case for flasg in MSR and MRS
instructions. Allow any bit to be set in the field_mask of
@@ -658,7 +673,7 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
target addresses for 'jal' and 'j'.
-2000-05-10 Geoff Keating <geoffk@cygnus.com>
+2000-05-10 Geoff Keating <geoffk@redhat.com>
* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
also available in common mode when powerpc syntax is being used.
@@ -668,7 +683,7 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
* m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
(dummy_print_address): Ditto.
-2000-05-04 Timothy Wall <twall@cygnus.com>
+2000-05-04 Timothy Wall <twall@redhat.com>
* tic54x-opc.c: New.
* tic54x-dis.c: New.
@@ -692,18 +707,18 @@ Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
(print_insn_little_powerpc): Likewise.
(print_insn_powerpc): Prepend 'v' when printing vector registers.
-Mon Apr 24 15:21:35 2000 Clinton Popetz <cpopetz@cygnus.com>
+2000-04-24 Clinton Popetz <cpopetz@redhat.com>
* configure.in: Add bfd_powerpc_64_arch.
* disassemble.c (disassembler): Use print_insn_big_powerpc for
64 bit code.
-2000-04-24 Nick Clifton <nickc@cygnus.com>
+2000-04-24 Nick Clifton <nickc@redhat.com>
* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
field.
-Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
+2000-04-23 Denis Chertykov <denisc@overta.ru>
* avr-dis.c (reg_fmul_d): New. Extract destination register from
FMUL instruction.
@@ -715,7 +730,7 @@ Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
(print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
-2000-04-22 Timothy Wall <twall@cygnus.com>
+2000-04-22 Timothy Wall <twall@redhat.com>
* ia64-gen.c (general): Add an ordered table of primary
opcode names, as well as priority fields to disassembly data
@@ -732,17 +747,17 @@ Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
* ia64-opc-b.c: Use more abbreviations.
* ia64-asmtab.c: Regenerate.
-Fri Apr 21 16:03:39 2000 Jason Eckhardt <jle@cygnus.com>
+2000-04-21 Jason Eckhardt <jle@redhat.com>
* hppa-dis.c (extract_16): New function.
(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
new operand types l,y,&,fe,fE,fx.
-Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
- David Mosberger <davidm@hpl.hp.com>
- Timothy Wall <twall@cygnus.com>
- Bob Manson <manson@charmed.cygnus.com>
- Jim Wilson <wilson@cygnus.com>
+2000-04-21 Richard Henderson <rth@redhat.com>
+ David Mosberger <davidm@hpl.hp.com>
+ Timothy Wall <twall@redhat.com>
+ Bob Manson <manson@charmed.cygnus.com>
+ Jim Wilson <wilson@redhat.com>
* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
@@ -761,7 +776,7 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
ia64-war.tbl, ia64-waw.tbl): New files.
-2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
+2000-04-20 Alexandre Oliva <aoliva@redhat.com>
* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
(disassemble): Use them.
@@ -785,21 +800,21 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove
ansidecl.h as sysdep.h includes it.
-Fri Apr 7 15:56:57 2000 Andrew Cagney <cagney@b1.cygnus.com>
+2000-04-7 Andrew Cagney <cagney@b1.redhat.com>
* configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add
--enable-build-warnings option.
* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
* Makefile.in, configure: Re-generate.
-Wed Apr 5 22:28:18 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-04-05 J"orn Rennecke <amylaar@redhat.com>
* sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
stc GBR,@-<REG_N> is available for arch_sh1_up.
Group parallel processing insn with identical mnemonics together.
Make three-operand psha / pshl come first.
-Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-04-05 J"orn Rennecke <amylaar@redhat.co.uk>
* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
@@ -832,7 +847,7 @@ Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
the parameter ATTRIBUTE_UNUSED.
* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
-2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
+2000-04-01 Alexandre Oliva <aoliva@redhat.com>
* m10300-opc.c: SP-based offsets are always unsigned.
@@ -841,7 +856,7 @@ Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
[branch always] instead of "undefined".
-2000-03-27 Nick Clifton <nickc@cygnus.com>
+2000-03-27 Nick Clifton <nickc@redhat.com>
* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
short instructions, from end of list of long instructions.
@@ -868,11 +883,11 @@ Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* disassemble.c: Likewise.
* configure: Regenerate.
-Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-03-06 J"oern Rennecke <amylaar@redhat.com>
* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
-2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-03-02 J"orn Rennecke <amylaar@redhat.co.uk>
* d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
flag to determine if operand is pc-relative.
@@ -893,7 +908,7 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(SHORT_U, SHORT_A5S): Removed stray alternatives.
(d30v_opcode_table): Use new *r formats.
-2000-02-28 Nick Clifton <nickc@cygnus.com>
+2000-02-28 Nick Clifton <nickc@redhat.com>
* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
'signed_overflow_ok_p'.
@@ -904,13 +919,13 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
name of the libtool directory.
* Makefile.in: Rebuild.
-2000-02-24 Nick Clifton <nickc@cygnus.com>
+2000-02-24 Nick Clifton <nickc@redhat.com>
* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
(cgen_clear_signed_overflow_ok): New function.
(cgen_signed_overflow_ok_p): New function.
-2000-02-23 Andrew Haley <aph@cygnus.com>
+2000-02-23 Andrew Haley <aph@redhat.com>
* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
m32r-ibld.c,m32r-opc.h: Rebuild.
@@ -928,13 +943,13 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* Makefile.in: Regenerate.
* configure: Likewise.
-2000-02-22 Chandra Chavva <cchavva@cygnus.com>
+2000-02-22 Chandra Chavva <cchavva@redhat.com>
* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
procedure.
-2000-02-22 Andrew Haley <aph@cygnus.com>
+2000-02-22 Andrew Haley <aph@redhat.com>
* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
force gp32 to zero.
@@ -951,7 +966,7 @@ Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* dis-buf.c (buffer_read_memory): Change `length' param and all int
vars to unsigned.
-Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk>
* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
(print_insn_ppi): Likewise.
@@ -968,7 +983,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
D_REG_N. Fill in arch field. Add sh-dsp insns.
-2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>
+2000-02-14 Fernando Nasser <fnasser@totem.to.redhat.com>
* arm-dis.c: Change flavor name from atpcs-special to
special-atpcs to prevent name conflict in gdb.
@@ -978,7 +993,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(print_insn_thumb): Use the register name entry from the currently
selected flavor for LR and PC.
-2000-02-10 Nick Clifton <nickc@cygnus.com>
+2000-02-10 Nick Clifton <nickc@redhat.com>
* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
classes.
@@ -989,7 +1004,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
(print_insn_mcore): Add support for little endian targets.
Add support for MULSH and OPSR classes.
-2000-02-07 Nick Clifton <nickc@cygnus.com>
+2000-02-07 Nick Clifton <nickc@redhat.com>
* arm-dis.c (parse_arm_diassembler_option): Rename again.
Previous delat did not take.
@@ -1034,7 +1049,7 @@ Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
* arm-dis.c (printf_insn_thumb): Prevent double dumping
of raw thumb instructions.
-2000-01-20 Nick Clifton <nickc@cygnus.com>
+2000-01-20 Nick Clifton <nickc@redhat.com>
* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 9cf5b1a..e31d9c1 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -40,6 +40,7 @@ CFILES = \
alpha-opc.c \
arc-dis.c \
arc-opc.c \
+ arc-ext.c \
arm-dis.c \
avr-dis.c \
cgen-asm.c \
@@ -121,6 +122,7 @@ ALL_MACHINES = \
alpha-opc.lo \
arc-dis.lo \
arc-opc.lo \
+ arc-ext.lo \
arm-dis.lo \
avr-dis.lo \
cgen-asm.lo \
@@ -342,9 +344,10 @@ arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/arc.h \
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
- $(INCDIR)/elf/reloc-macros.h opintl.h
+ $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/arc.h opintl.h
+arc-ext.lo: $(BFD_H) $(INCDIR)/libiberty.h arc-ext.h
arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index f7a0feb..e406027 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -151,6 +151,7 @@ CFILES = \
alpha-opc.c \
arc-dis.c \
arc-opc.c \
+ arc-ext.c \
arm-dis.c \
avr-dis.c \
cgen-asm.c \
@@ -233,6 +234,7 @@ ALL_MACHINES = \
alpha-opc.lo \
arc-dis.lo \
arc-opc.lo \
+ arc-ext.lo \
arm-dis.lo \
avr-dis.lo \
cgen-asm.lo \
@@ -852,9 +854,10 @@ arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/arc.h \
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
- $(INCDIR)/elf/reloc-macros.h opintl.h
+ $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/arc.h opintl.h
+arc-ext.lo: $(BFD_H) $(INCDIR)/libiberty.h arc-ext.h
arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 03f1379..3920006 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1,268 +1,1220 @@
/* Instruction printing code for the ARC.
- Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1994, 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-#include "sysdep.h"
+#include <ansidecl.h>
+#include <libiberty.h>
#include "dis-asm.h"
#include "opcode/arc.h"
#include "elf-bfd.h"
#include "elf/arc.h"
+#include <string.h>
#include "opintl.h"
-static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *));
+#include <ctype.h>
+#include <stdarg.h>
+#include "arc-dis.h"
+#include "arc-ext.h"
-static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int));
+#ifndef dbg
+#define dbg (0)
+#endif
-/* Print one instruction from PC on INFO->STREAM.
- Return the size of the instruction (4 or 8 for the ARC). */
+#define BIT(word,n) ((word) & (1 << n))
+#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
+#define OPCODE(word) (BITS ((word), 27, 31))
+#define FIELDA(word) (BITS ((word), 21, 26))
+#define FIELDB(word) (BITS ((word), 15, 20))
+#define FIELDC(word) (BITS ((word), 9, 14))
-static int
-print_insn (pc, info, mach, big_p)
- bfd_vma pc;
- disassemble_info *info;
- int mach;
- int big_p;
+/* FIELD D is signed in all of its uses, so we make sure argument is
+ treated as signed for bit shifting purposes: */
+#define FIELDD(word) (BITS (((signed int)word), 0, 8))
+
+#define PUT_NEXT_WORD_IN(a) \
+ do \
+ { \
+ if (is_limm == 1 && !NEXT_WORD (1)) \
+ mwerror (state, _("Illegal limm reference in last instruction!\n")); \
+ a = state->words[1]; \
+ } \
+ while (0)
+
+#define CHECK_FLAG_COND_NULLIFY() \
+ do \
+ { \
+ if (is_shimm == 0) \
+ { \
+ flag = BIT (state->words[0], 8); \
+ state->nullifyMode = BITS (state->words[0], 5, 6); \
+ cond = BITS (state->words[0], 0, 4); \
+ } \
+ } \
+ while (0)
+
+#define CHECK_COND() \
+ do \
+ { \
+ if (is_shimm == 0) \
+ cond = BITS (state->words[0], 0, 4); \
+ } \
+ while (0)
+
+#define CHECK_FIELD(field) \
+ do \
+ { \
+ if (field == 62) \
+ { \
+ is_limm++; \
+ field##isReg = 0; \
+ PUT_NEXT_WORD_IN (field); \
+ limm_value = field; \
+ } \
+ else if (field > 60) \
+ { \
+ field##isReg = 0; \
+ is_shimm++; \
+ flag = (field == 61); \
+ field = FIELDD (state->words[0]); \
+ } \
+ } \
+ while (0)
+
+#define CHECK_FIELD_A() \
+ do \
+ { \
+ fieldA = FIELDA(state->words[0]); \
+ if (fieldA > 60) \
+ { \
+ fieldAisReg = 0; \
+ fieldA = 0; \
+ } \
+ } \
+ while (0)
+
+#define CHECK_FIELD_B() \
+ do \
+ { \
+ fieldB = FIELDB (state->words[0]); \
+ CHECK_FIELD (fieldB); \
+ } \
+ while (0)
+
+#define CHECK_FIELD_C() \
+ do \
+ { \
+ fieldC = FIELDC (state->words[0]); \
+ CHECK_FIELD (fieldC); \
+ } \
+ while (0)
+
+#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
+#define IS_REG(x) (field##x##isReg)
+#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
+#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
+#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
+#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
+#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
+#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
+#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
+#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
+ (IS_REG (x) ? cb1"%r"ca1 : \
+ usesAuxReg ? cb"%a"ca : \
+ IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
+#define WRITE_FORMAT_RB() strcat (formatString, "]")
+#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
+#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
+
+#define NEXT_WORD(x) (offset += 4, state->words[x])
+
+#define add_target(x) (state->targets[state->tcnt++] = (x))
+
+static char comment_prefix[] = "\t; ";
+
+static const char *
+core_reg_name (state, val)
+ struct arcDisState * state;
+ int val;
{
- const struct arc_opcode *opcode;
- bfd_byte buffer[4];
- void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
- int status;
- /* First element is insn, second element is limm (if present). */
- arc_insn insn[2];
- int got_limm_p = 0;
- static int initialized = 0;
- static int current_mach = 0;
+ if (state->coreRegName)
+ return (*state->coreRegName)(state->_this, val);
+ return 0;
+}
- if (!initialized || mach != current_mach)
- {
- initialized = 1;
- current_mach = arc_get_opcode_mach (mach, big_p);
- arc_opcode_init_tables (current_mach);
- }
+static const char *
+aux_reg_name (state, val)
+ struct arcDisState * state;
+ int val;
+{
+ if (state->auxRegName)
+ return (*state->auxRegName)(state->_this, val);
+ return 0;
+}
- status = (*info->read_memory_func) (pc, buffer, 4, info);
- if (status != 0)
+static const char *
+cond_code_name (state, val)
+ struct arcDisState * state;
+ int val;
+{
+ if (state->condCodeName)
+ return (*state->condCodeName)(state->_this, val);
+ return 0;
+}
+
+static const char *
+instruction_name (state, op1, op2, flags)
+ struct arcDisState * state;
+ int op1;
+ int op2;
+ int * flags;
+{
+ if (state->instName)
+ return (*state->instName)(state->_this, op1, op2, flags);
+ return 0;
+}
+
+static void
+mwerror (state, msg)
+ struct arcDisState * state;
+ const char * msg;
+{
+ if (state->err != 0)
+ (*state->err)(state->_this, (msg));
+}
+
+static const char *
+post_address (state, addr)
+ struct arcDisState * state;
+ int addr;
+{
+ static char id[3 * ARRAY_SIZE (state->addresses)];
+ int j, i = state->acnt;
+
+ if (i < ((int) ARRAY_SIZE (state->addresses)))
{
- (*info->memory_error_func) (status, pc, info);
- return -1;
+ state->addresses[i] = addr;
+ ++state->acnt;
+ j = i*3;
+ id[j+0] = '@';
+ id[j+1] = '0'+i;
+ id[j+2] = 0;
+
+ return id + j;
}
- if (big_p)
- insn[0] = bfd_getb32 (buffer);
- else
- insn[0] = bfd_getl32 (buffer);
+ return "";
+}
- (*func) (stream, "%08lx\t", insn[0]);
+static void
+my_sprintf (
+ struct arcDisState * state,
+ char * buf,
+ const char * format,
+ ...)
+{
+ char *bp;
+ const char *p;
+ int size, leading_zero, regMap[2];
+ long auxNum;
+ va_list ap;
+
+ va_start (ap, format);
+
+ bp = buf;
+ *bp = 0;
+ p = format;
+ auxNum = -1;
+ regMap[0] = 0;
+ regMap[1] = 0;
+
+ while (1)
+ switch (*p++)
+ {
+ case 0:
+ goto DOCOMM; /* (return) */
+ default:
+ *bp++ = p[-1];
+ break;
+ case '%':
+ size = 0;
+ leading_zero = 0;
+ RETRY: ;
+ switch (*p++)
+ {
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ {
+ /* size. */
+ size = p[-1] - '0';
+ if (size == 0)
+ leading_zero = 1; /* e.g. %08x */
+ while (*p >= '0' && *p <= '9')
+ {
+ size = size * 10 + *p - '0';
+ p++;
+ }
+ goto RETRY;
+ }
+#define inc_bp() bp = bp + strlen (bp)
- /* The instructions are stored in lists hashed by the insn code
- (though we needn't care how they're hashed). */
+ case 'h':
+ {
+ unsigned u = va_arg (ap, int);
- opcode = arc_opcode_lookup_dis (insn[0]);
- for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_DIS (opcode))
- {
- char *syn;
- int mods,invalid;
- long value;
- const struct arc_operand *operand;
- const struct arc_operand_value *opval;
-
- /* Basic bit mask must be correct. */
- if ((insn[0] & opcode->mask) != opcode->value)
- continue;
-
- /* Supported by this cpu? */
- if (! arc_opcode_supported (opcode))
- continue;
-
- /* Make two passes over the operands. First see if any of them
- have extraction functions, and, if they do, make sure the
- instruction is valid. */
-
- arc_opcode_init_extract ();
- invalid = 0;
-
- /* ??? Granted, this is slower than the `ppc' way. Maybe when this is
- done it'll be clear what the right way to do this is. */
- /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets
- printed first, but we don't know how to print it until we've processed
- the regs. Since we're scanning all the args before printing the insn
- anyways, it's actually quite easy. */
-
- for (syn = opcode->syntax; *syn; ++syn)
- {
- int c;
+ /* Hex. We can change the format to 0x%08x in
+ one place, here, if we wish.
+ We add underscores for easy reading. */
+ if (u > 65536)
+ sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
+ else
+ sprintf (bp, "0x%x", u);
+ inc_bp ();
+ }
+ break;
+ case 'X': case 'x':
+ {
+ int val = va_arg (ap, int);
- if (*syn != '%' || *++syn == '%')
- continue;
- mods = 0;
- c = *syn;
- while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags))
+ if (size != 0)
+ if (leading_zero)
+ sprintf (bp, "%0*x", size, val);
+ else
+ sprintf (bp, "%*x", size, val);
+ else
+ sprintf (bp, "%x", val);
+ inc_bp ();
+ }
+ break;
+ case 'd':
{
- mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS;
- ++syn;
- c = *syn;
+ int val = va_arg (ap, int);
+
+ if (size != 0)
+ sprintf (bp, "%*d", size, val);
+ else
+ sprintf (bp, "%d", val);
+ inc_bp ();
}
- operand = arc_operands + arc_operand_map[c];
- if (operand->extract)
- (*operand->extract) (insn, operand, mods,
- (const struct arc_operand_value **) NULL,
- &invalid);
- }
- if (invalid)
- continue;
+ break;
+ case 'r':
+ {
+ /* Register. */
+ int val = va_arg (ap, int);
+
+#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
+ regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
+
+ switch (val)
+ {
+ REG2NAME (26, "gp");
+ REG2NAME (27, "fp");
+ REG2NAME (28, "sp");
+ REG2NAME (29, "ilink1");
+ REG2NAME (30, "ilink2");
+ REG2NAME (31, "blink");
+ REG2NAME (60, "lp_count");
+ default:
+ {
+ const char * ext;
+
+ ext = core_reg_name (state, val);
+ if (ext)
+ sprintf (bp, "%s", ext);
+ else
+ sprintf (bp,"r%d",val);
+ }
+ break;
+ }
+ inc_bp ();
+ } break;
+
+ case 'a':
+ {
+ /* Aux Register. */
+ int val = va_arg (ap, int);
- /* The instruction is valid. */
+#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
- /* If we have an insn with a limm, fetch it now. Scanning the insns
- twice lets us do this. */
- if (arc_opcode_limm_p (NULL))
- {
- status = (*info->read_memory_func) (pc + 4, buffer, 4, info);
- if (status != 0)
+ switch (val)
+ {
+ AUXREG2NAME (0x0, "status");
+ AUXREG2NAME (0x1, "semaphore");
+ AUXREG2NAME (0x2, "lp_start");
+ AUXREG2NAME (0x3, "lp_end");
+ AUXREG2NAME (0x4, "identity");
+ AUXREG2NAME (0x5, "debug");
+ default:
+ {
+ const char *ext;
+
+ ext = aux_reg_name (state, val);
+ if (ext)
+ sprintf (bp, "%s", ext);
+ else
+ my_sprintf (state, bp, "%h", val);
+ }
+ break;
+ }
+ inc_bp ();
+ }
+ break;
+
+ case 's':
{
- (*info->memory_error_func) (status, pc, info);
- return -1;
+ sprintf (bp, "%s", va_arg (ap, char *));
+ inc_bp ();
}
- if (big_p)
- insn[1] = bfd_getb32 (buffer);
+ break;
+
+ default:
+ fprintf (stderr, "?? format %c\n", p[-1]);
+ break;
+ }
+ }
+
+ DOCOMM: *bp = 0;
+}
+
+static void
+write_comments_(state, shimm, is_limm, limm_value)
+ struct arcDisState * state;
+ int shimm;
+ int is_limm;
+ long limm_value;
+{
+ if (state->commentBuffer != 0)
+ {
+ int i;
+
+ if (is_limm)
+ {
+ const char *name = post_address (state, limm_value + shimm);
+
+ if (*name != 0)
+ WRITE_COMMENT (name);
+ }
+ for (i = 0; i < state->commNum; i++)
+ {
+ if (i == 0)
+ strcpy (state->commentBuffer, comment_prefix);
else
- insn[1] = bfd_getl32 (buffer);
- got_limm_p = 1;
+ strcat (state->commentBuffer, ", ");
+ strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer));
}
+ }
+}
- for (syn = opcode->syntax; *syn; ++syn)
- {
- int c;
+#define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
+#define write_comments() write_comments2(0)
+
+static const char *condName[] = {
+ /* 0..15. */
+ "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
+ "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
+};
+
+static void
+write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
+ struct arcDisState * state;
+ const char * instrName;
+ int cond;
+ int condCodeIsPartOfName;
+ int flag;
+ int signExtend;
+ int addrWriteBack;
+ int directMem;
+{
+ strcpy (state->instrBuffer, instrName);
+
+ if (cond > 0)
+ {
+ const char *cc = 0;
+
+ if (!condCodeIsPartOfName)
+ strcat (state->instrBuffer, ".");
+
+ if (cond < 16)
+ cc = condName[cond];
+ else
+ cc = cond_code_name (state, cond);
+
+ if (!cc)
+ cc = "???";
+
+ strcat (state->instrBuffer, cc);
+ }
+
+ if (flag)
+ strcat (state->instrBuffer, ".f");
+
+ switch (state->nullifyMode)
+ {
+ case BR_exec_always:
+ strcat (state->instrBuffer, ".d");
+ break;
+ case BR_exec_when_jump:
+ strcat (state->instrBuffer, ".jd");
+ break;
+ }
+
+ if (signExtend)
+ strcat (state->instrBuffer, ".x");
+
+ if (addrWriteBack)
+ strcat (state->instrBuffer, ".a");
+
+ if (directMem)
+ strcat (state->instrBuffer, ".di");
+}
+
+#define write_instr_name() \
+ do \
+ { \
+ write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
+ flag, signExtend, addrWriteBack, directMem); \
+ formatString[0] = '\0'; \
+ } \
+ while (0)
+
+enum {
+ op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
+ op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
+ op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
+ op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
+};
+
+extern disassemble_info tm_print_insn_info;
- if (*syn != '%' || *++syn == '%')
+static int
+dsmOneArcInst (addr, state)
+ bfd_vma addr;
+ struct arcDisState * state;
+{
+ int condCodeIsPartOfName = 0;
+ int decodingClass;
+ const char * instrName;
+ int repeatsOp = 0;
+ int fieldAisReg = 1;
+ int fieldBisReg = 1;
+ int fieldCisReg = 1;
+ int fieldA;
+ int fieldB;
+ int fieldC = 0;
+ int flag = 0;
+ int cond = 0;
+ int is_shimm = 0;
+ int is_limm = 0;
+ long limm_value = 0;
+ int signExtend = 0;
+ int addrWriteBack = 0;
+ int directMem = 0;
+ int is_linked = 0;
+ int offset = 0;
+ int usesAuxReg = 0;
+ int flags;
+ int ignoreFirstOpd;
+ char formatString[60];
+
+ state->instructionLen = 4;
+ state->nullifyMode = BR_exec_when_no_jump;
+ state->opWidth = 12;
+ state->isBranch = 0;
+
+ state->_mem_load = 0;
+ state->_ea_present = 0;
+ state->_load_len = 0;
+ state->ea_reg1 = no_reg;
+ state->ea_reg2 = no_reg;
+ state->_offset = 0;
+
+ if (! NEXT_WORD (0))
+ return 0;
+
+ state->_opcode = OPCODE (state->words[0]);
+ instrName = 0;
+ decodingClass = 0; /* default! */
+ repeatsOp = 0;
+ condCodeIsPartOfName=0;
+ state->commNum = 0;
+ state->tcnt = 0;
+ state->acnt = 0;
+ state->flow = noflow;
+ ignoreFirstOpd = 0;
+
+ if (state->commentBuffer)
+ state->commentBuffer[0] = '\0';
+
+ switch (state->_opcode)
+ {
+ case op_LD0:
+ switch (BITS (state->words[0],1,2))
+ {
+ case 0:
+ instrName = "ld";
+ state->_load_len = 4;
+ break;
+ case 1:
+ instrName = "ldb";
+ state->_load_len = 1;
+ break;
+ case 2:
+ instrName = "ldw";
+ state->_load_len = 2;
+ break;
+ default:
+ instrName = "??? (0[3])";
+ state->flow = invalid_instr;
+ break;
+ }
+ decodingClass = 5;
+ break;
+
+ case op_LD1:
+ if (BIT (state->words[0],13))
+ {
+ instrName = "lr";
+ decodingClass = 10;
+ }
+ else
+ {
+ switch (BITS (state->words[0],10,11))
{
- (*func) (stream, "%c", *syn);
- continue;
+ case 0:
+ instrName = "ld";
+ state->_load_len = 4;
+ break;
+ case 1:
+ instrName = "ldb";
+ state->_load_len = 1;
+ break;
+ case 2:
+ instrName = "ldw";
+ state->_load_len = 2;
+ break;
+ default:
+ instrName = "??? (1[3])";
+ state->flow = invalid_instr;
+ break;
}
-
- /* We have an operand. Fetch any special modifiers. */
- mods = 0;
- c = *syn;
- while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags))
+ decodingClass = 6;
+ }
+ break;
+
+ case op_ST:
+ if (BIT (state->words[0],25))
+ {
+ instrName = "sr";
+ decodingClass = 8;
+ }
+ else
+ {
+ switch (BITS (state->words[0],22,23))
+ {
+ case 0:
+ instrName = "st";
+ break;
+ case 1:
+ instrName = "stb";
+ break;
+ case 2:
+ instrName = "stw";
+ break;
+ default:
+ instrName = "??? (2[3])";
+ state->flow = invalid_instr;
+ break;
+ }
+ decodingClass = 7;
+ }
+ break;
+
+ case op_3:
+ decodingClass = 1; /* default for opcode 3... */
+ switch (FIELDC (state->words[0]))
+ {
+ case 0:
+ instrName = "flag";
+ decodingClass = 2;
+ break;
+ case 1:
+ instrName = "asr";
+ break;
+ case 2:
+ instrName = "lsr";
+ break;
+ case 3:
+ instrName = "ror";
+ break;
+ case 4:
+ instrName = "rrc";
+ break;
+ case 5:
+ instrName = "sexb";
+ break;
+ case 6:
+ instrName = "sexw";
+ break;
+ case 7:
+ instrName = "extb";
+ break;
+ case 8:
+ instrName = "extw";
+ break;
+ case 0x3f:
+ {
+ decodingClass = 9;
+ switch( FIELDD (state->words[0]) )
+ {
+ case 0:
+ instrName = "brk";
+ break;
+ case 1:
+ instrName = "sleep";
+ break;
+ case 2:
+ instrName = "swi";
+ break;
+ default:
+ instrName = "???";
+ state->flow=invalid_instr;
+ break;
+ }
+ }
+ break;
+
+ /* ARC Extension Library Instructions
+ NOTE: We assume that extension codes are these instrs. */
+ default:
+ instrName = instruction_name (state,
+ state->_opcode,
+ FIELDC (state->words[0]),
+ & flags);
+ if (!instrName)
{
- mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS;
- ++syn;
- c = *syn;
+ instrName = "???";
+ state->flow = invalid_instr;
}
- operand = arc_operands + arc_operand_map[c];
+ if (flags & IGNORE_FIRST_OPD)
+ ignoreFirstOpd = 1;
+ break;
+ }
+ break;
- /* Extract the value from the instruction. */
- opval = NULL;
- if (operand->extract)
+ case op_BC:
+ instrName = "b";
+ case op_BLC:
+ if (!instrName)
+ instrName = "bl";
+ case op_LPC:
+ if (!instrName)
+ instrName = "lp";
+ case op_JC:
+ if (!instrName)
+ {
+ if (BITS (state->words[0],9,9))
{
- value = (*operand->extract) (insn, operand, mods,
- &opval, (int *) NULL);
+ instrName = "jl";
+ is_linked = 1;
}
- else
+ else
{
- value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & (1 << (operand->bits - 1))))
- value -= 1 << operand->bits;
-
- /* If this is a suffix operand, set `opval'. */
- if (operand->flags & ARC_OPERAND_SUFFIX)
- opval = arc_opcode_lookup_suffix (operand, value);
+ instrName = "j";
+ is_linked = 0;
}
+ }
+ condCodeIsPartOfName = 1;
+ decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
+ state->isBranch = 1;
+ break;
+
+ case op_ADD:
+ case op_ADC:
+ case op_AND:
+ repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
+ decodingClass = 0;
- /* Print the operand as directed by the flags. */
- if (operand->flags & ARC_OPERAND_FAKE)
- ; /* nothing to do (??? at least not yet) */
- else if (operand->flags & ARC_OPERAND_SUFFIX)
- {
- /* Default suffixes aren't printed. Fortunately, they all have
- zero values. Also, zero values for boolean suffixes are
- represented by the absence of text. */
+ switch (state->_opcode)
+ {
+ case op_ADD:
+ instrName = (repeatsOp ? "asl" : "add");
+ break;
+ case op_ADC:
+ instrName = (repeatsOp ? "rlc" : "adc");
+ break;
+ case op_AND:
+ instrName = (repeatsOp ? "mov" : "and");
+ break;
+ }
+ break;
+
+ case op_SUB: instrName = "sub";
+ break;
+ case op_SBC: instrName = "sbc";
+ break;
+ case op_OR: instrName = "or";
+ break;
+ case op_BIC: instrName = "bic";
+ break;
- if (value != 0)
- {
- /* ??? OPVAL should have a value. If it doesn't just cope
- as we want disassembly to be reasonably robust.
- Also remember that several condition code values (16-31)
- aren't defined yet. For these cases just print the
- number suitably decorated. */
- if (opval)
- (*func) (stream, "%s%s",
- mods & ARC_MOD_DOT ? "." : "",
- opval->name);
- else
- (*func) (stream, "%s%c%d",
- mods & ARC_MOD_DOT ? "." : "",
- operand->fmt, value);
- }
+ case op_XOR:
+ if (state->words[0] == 0x7fffffff)
+ {
+ /* nop encoded as xor -1, -1, -1 */
+ instrName = "nop";
+ decodingClass = 9;
+ }
+ else
+ instrName = "xor";
+ break;
+
+ default:
+ instrName = instruction_name (state,state->_opcode,0,&flags);
+ /* if (instrName) printf("FLAGS=0x%x\n", flags); */
+ if (!instrName)
+ {
+ instrName = "???";
+ state->flow=invalid_instr;
+ }
+ if (flags & IGNORE_FIRST_OPD)
+ ignoreFirstOpd = 1;
+ break;
+ }
+
+ fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
+ flag = cond = is_shimm = is_limm = 0;
+ state->nullifyMode = BR_exec_when_no_jump; /* 0 */
+ signExtend = addrWriteBack = directMem = 0;
+ usesAuxReg = 0;
+
+ switch (decodingClass)
+ {
+ case 0:
+ CHECK_FIELD_A ();
+ CHECK_FIELD_B ();
+ if (!repeatsOp)
+ CHECK_FIELD_C ();
+ CHECK_FLAG_COND_NULLIFY ();
+
+ write_instr_name ();
+ if (!ignoreFirstOpd)
+ {
+ WRITE_FORMAT_x (A);
+ WRITE_FORMAT_COMMA_x (B);
+ if (!repeatsOp)
+ WRITE_FORMAT_COMMA_x (C);
+ WRITE_NOP_COMMENT ();
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+ }
+ else
+ {
+ WRITE_FORMAT_x (B);
+ if (!repeatsOp)
+ WRITE_FORMAT_COMMA_x (C);
+ my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC);
+ }
+ write_comments ();
+ break;
+
+ case 1:
+ CHECK_FIELD_A ();
+ CHECK_FIELD_B ();
+ CHECK_FLAG_COND_NULLIFY ();
+
+ write_instr_name ();
+ if (!ignoreFirstOpd)
+ {
+ WRITE_FORMAT_x (A);
+ WRITE_FORMAT_COMMA_x (B);
+ WRITE_NOP_COMMENT ();
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
+ }
+ else
+ {
+ WRITE_FORMAT_x (B);
+ my_sprintf (state, state->operandBuffer, formatString, fieldB);
+ }
+ write_comments ();
+ break;
+
+ case 2:
+ CHECK_FIELD_B ();
+ CHECK_FLAG_COND_NULLIFY ();
+ flag = 0; /* this is the FLAG instruction -- it's redundant */
+
+ write_instr_name ();
+ WRITE_FORMAT_x (B);
+ my_sprintf (state, state->operandBuffer, formatString, fieldB);
+ write_comments ();
+ break;
+
+ case 3:
+ fieldA = BITS (state->words[0],7,26) << 2;
+ fieldA = (fieldA << 10) >> 10; /* make it signed */
+ fieldA += addr + 4;
+ CHECK_FLAG_COND_NULLIFY ();
+ flag = 0;
+
+ write_instr_name ();
+ /* This address could be a label we know. Convert it. */
+ if (state->_opcode != op_LPC /* LP */)
+ {
+ add_target (fieldA); /* For debugger. */
+ state->flow = state->_opcode == op_BLC /* BL */
+ ? direct_call
+ : direct_jump;
+ /* indirect calls are achieved by "lr blink,[status];
+ lr dest<- func addr; j [dest]" */
+ }
+
+ strcat (formatString, "%s"); /* address/label name */
+ my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA));
+ write_comments ();
+ break;
+
+ case 4:
+ /* For op_JC -- jump to address specified.
+ Also covers jump and link--bit 9 of the instr. word
+ selects whether linked, thus "is_linked" is set above. */
+ fieldA = 0;
+ CHECK_FIELD_B ();
+ CHECK_FLAG_COND_NULLIFY ();
+
+ if (!fieldBisReg)
+ {
+ fieldAisReg = 0;
+ fieldA = (fieldB >> 25) & 0x7F; /* flags */
+ fieldB = (fieldB & 0xFFFFFF) << 2;
+ state->flow = is_linked ? direct_call : direct_jump;
+ add_target (fieldB);
+ /* screwy JLcc requires .jd mode to execute correctly
+ * but we pretend it is .nd (no delay slot). */
+ if (is_linked && state->nullifyMode == BR_exec_when_jump)
+ state->nullifyMode = BR_exec_when_no_jump;
+ }
+ else
+ {
+ state->flow = is_linked ? indirect_call : indirect_jump;
+ /* We should also treat this as indirect call if NOT linked
+ * but the preceding instruction was a "lr blink,[status]"
+ * and we have a delay slot with "add blink,blink,2".
+ * For now we can't detect such. */
+ state->register_for_indirect_jump = fieldB;
+ }
+
+ write_instr_name ();
+ strcat (formatString,
+ IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
+ if (fieldA != 0)
+ {
+ fieldAisReg = 0;
+ WRITE_FORMAT_COMMA_x (A);
+ }
+ if (IS_REG (B))
+ my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
+ else
+ my_sprintf (state, state->operandBuffer, formatString,
+ post_address (state, fieldB), fieldA);
+ write_comments ();
+ break;
+
+ case 5:
+ /* LD instruction.
+ B and C can be regs, or one (both?) can be limm. */
+ CHECK_FIELD_A ();
+ CHECK_FIELD_B ();
+ CHECK_FIELD_C ();
+ if (dbg)
+ printf ("5:b reg %d %d c reg %d %d \n",
+ fieldBisReg,fieldB,fieldCisReg,fieldC);
+ state->_offset = 0;
+ state->_ea_present = 1;
+ if (fieldBisReg)
+ state->ea_reg1 = fieldB;
+ else
+ state->_offset += fieldB;
+ if (fieldCisReg)
+ state->ea_reg2 = fieldC;
+ else
+ state->_offset += fieldC;
+ state->_mem_load = 1;
+
+ directMem = BIT (state->words[0],5);
+ addrWriteBack = BIT (state->words[0],3);
+ signExtend = BIT (state->words[0],0);
+
+ write_instr_name ();
+ WRITE_FORMAT_x_COMMA_LB(A);
+ if (fieldBisReg || fieldB != 0)
+ WRITE_FORMAT_x_COMMA (B);
+ else
+ fieldB = fieldC;
+
+ WRITE_FORMAT_x_RB (C);
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+ write_comments ();
+ break;
+
+ case 6:
+ /* LD instruction. */
+ CHECK_FIELD_B ();
+ CHECK_FIELD_A ();
+ fieldC = FIELDD (state->words[0]);
+
+ if (dbg)
+ printf ("6:b reg %d %d c 0x%x \n",
+ fieldBisReg, fieldB, fieldC);
+ state->_ea_present = 1;
+ state->_offset = fieldC;
+ state->_mem_load = 1;
+ if (fieldBisReg)
+ state->ea_reg1 = fieldB;
+ /* field B is either a shimm (same as fieldC) or limm (different!)
+ Say ea is not present, so only one of us will do the name lookup. */
+ else
+ state->_offset += fieldB, state->_ea_present = 0;
+
+ directMem = BIT (state->words[0],14);
+ addrWriteBack = BIT (state->words[0],12);
+ signExtend = BIT (state->words[0],9);
+
+ write_instr_name ();
+ WRITE_FORMAT_x_COMMA_LB (A);
+ if (!fieldBisReg)
+ {
+ fieldB = state->_offset;
+ WRITE_FORMAT_x_RB (B);
+ }
+ else
+ {
+ WRITE_FORMAT_x (B);
+ if (fieldC != 0 && !BIT (state->words[0],13))
+ {
+ fieldCisReg = 0;
+ WRITE_FORMAT_COMMA_x_RB (C);
}
- else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH)
- (*info->print_address_func) (pc + 4 + value, info);
- /* ??? Not all cases of this are currently caught. */
- else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH)
- (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
- else if (operand->flags & ARC_OPERAND_ADDRESS)
- (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
- else if (opval)
- /* Note that this case catches both normal and auxiliary regs. */
- (*func) (stream, "%s", opval->name);
else
- (*func) (stream, "%ld", value);
+ WRITE_FORMAT_RB ();
}
-
- /* We have found and printed an instruction; return. */
- return got_limm_p ? 8 : 4;
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+ write_comments ();
+ break;
+
+ case 7:
+ /* ST instruction. */
+ CHECK_FIELD_B();
+ CHECK_FIELD_C();
+ fieldA = FIELDD(state->words[0]); /* shimm */
+
+ /* [B,A offset] */
+ if (dbg) printf("7:b reg %d %x off %x\n",
+ fieldBisReg,fieldB,fieldA);
+ state->_ea_present = 1;
+ state->_offset = fieldA;
+ if (fieldBisReg)
+ state->ea_reg1 = fieldB;
+ /* field B is either a shimm (same as fieldA) or limm (different!)
+ Say ea is not present, so only one of us will do the name lookup.
+ (for is_limm we do the name translation here). */
+ else
+ state->_offset += fieldB, state->_ea_present = 0;
+
+ directMem = BIT(state->words[0],26);
+ addrWriteBack = BIT(state->words[0],24);
+
+ write_instr_name();
+ WRITE_FORMAT_x_COMMA_LB(C);
+
+ if (!fieldBisReg)
+ {
+ fieldB = state->_offset;
+ WRITE_FORMAT_x_RB(B);
+ }
+ else
+ {
+ WRITE_FORMAT_x(B);
+ if (fieldBisReg && fieldA != 0)
+ {
+ fieldAisReg = 0;
+ WRITE_FORMAT_COMMA_x_RB(A);
+ }
+ else
+ WRITE_FORMAT_RB();
+ }
+ my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
+ write_comments2(fieldA);
+ break;
+ case 8:
+ /* SR instruction */
+ CHECK_FIELD_B();
+ CHECK_FIELD_C();
+
+ write_instr_name();
+ WRITE_FORMAT_x_COMMA_LB(C);
+ /* Try to print B as an aux reg if it is not a core reg. */
+ usesAuxReg = 1;
+ WRITE_FORMAT_x(B);
+ WRITE_FORMAT_RB();
+ my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
+ write_comments();
+ break;
+
+ case 9:
+ write_instr_name();
+ state->operandBuffer[0] = '\0';
+ break;
+
+ case 10:
+ /* LR instruction */
+ CHECK_FIELD_A();
+ CHECK_FIELD_B();
+
+ write_instr_name();
+ WRITE_FORMAT_x_COMMA_LB(A);
+ /* Try to print B as an aux reg if it is not a core reg. */
+ usesAuxReg = 1;
+ WRITE_FORMAT_x(B);
+ WRITE_FORMAT_RB();
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
+ write_comments();
+ break;
+
+ case 11:
+ CHECK_COND();
+ write_instr_name();
+ state->operandBuffer[0] = '\0';
+ break;
+
+ default:
+ mwerror (state, "Bad decoding class in ARC disassembler");
+ break;
}
+
+ state->_cond = cond;
+ return state->instructionLen = offset;
+}
+
- (*func) (stream, _("*unknown*"));
- return 4;
+/* Returns the name the user specified core extension register. */
+static const char *
+_coreRegName(arg, regval)
+ void * arg ATTRIBUTE_UNUSED;
+ int regval;
+{
+ return arcExtMap_coreRegName (regval);
}
-/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use.
- This does things a non-standard way (the "standard" way would be to copy
- this code into disassemble.c). Since there are more than a couple of
- variants, hiding all this crud here seems cleaner. */
+/* Returns the name the user specified AUX extension register. */
+static const char *
+_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
+{
+ return arcExtMap_auxRegName(regval);
+}
-disassembler_ftype
-arc_get_disassembler (mach, big_p)
- int mach;
- int big_p;
+
+/* Returns the name the user specified condition code name. */
+static const char *
+_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
{
- switch (mach)
- {
- case bfd_mach_arc_base:
- return big_p ? print_insn_arc_base_big : print_insn_arc_base_little;
- }
- return print_insn_arc_base_little;
+ return arcExtMap_condCodeName(regval);
}
-static int
-print_insn_arc_base_little (pc, info)
- bfd_vma pc;
- disassemble_info *info;
+/* Returns the name the user specified extension instruction. */
+static const char *
+_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
{
- return print_insn (pc, info, bfd_mach_arc_base, 0);
+ return arcExtMap_instName(majop, minop, flags);
}
+/* Decode an instruction returning the size of the instruction
+ in bytes or zero if unrecognized. */
static int
-print_insn_arc_base_big (pc, info)
- bfd_vma pc;
- disassemble_info *info;
+decodeInstr (address, info)
+ bfd_vma address; /* Address of this instruction. */
+ disassemble_info * info;
+{
+ int status;
+ bfd_byte buffer[4];
+ struct arcDisState s; /* ARC Disassembler state */
+ void *stream = info->stream; /* output stream */
+ fprintf_ftype func = info->fprintf_func;
+ int bytes;
+
+ memset (&s, 0, sizeof(struct arcDisState));
+
+ /* read first instruction */
+ status = (*info->read_memory_func) (address, buffer, 4, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, address, info);
+ return 0;
+ }
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ s.words[0] = bfd_getl32(buffer);
+ else
+ s.words[0] = bfd_getb32(buffer);
+ /* always read second word in case of limm */
+
+ /* we ignore the result since last insn may not have a limm */
+ status = (*info->read_memory_func) (address + 4, buffer, 4, info);
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ s.words[1] = bfd_getl32(buffer);
+ else
+ s.words[1] = bfd_getb32(buffer);
+
+ s._this = &s;
+ s.coreRegName = _coreRegName;
+ s.auxRegName = _auxRegName;
+ s.condCodeName = _condCodeName;
+ s.instName = _instName;
+
+ /* disassemble */
+ bytes = dsmOneArcInst(address, (void *)&s);
+
+ /* display the disassembly instruction */
+ (*func) (stream, "%08x ", s.words[0]);
+ (*func) (stream, " ");
+
+ (*func) (stream, "%-10s ", s.instrBuffer);
+
+ if (__TRANSLATION_REQUIRED(s))
+ {
+ bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
+ (*info->print_address_func) ((bfd_vma) addr, info);
+ (*func) (stream, "\n");
+ }
+ else
+ (*func) (stream, "%s",s.operandBuffer);
+ return s.instructionLen;
+}
+
+/* Return the print_insn function to use.
+ Side effect: load (possibly empty) extension section */
+
+disassembler_ftype
+arc_get_disassembler (void *ptr)
{
- return print_insn (pc, info, bfd_mach_arc_base, 1);
+ if (ptr)
+ build_ARC_extmap (ptr);
+ return decodeInstr;
}
diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h
new file mode 100644
index 0000000..992510c
--- /dev/null
+++ b/opcodes/arc-dis.h
@@ -0,0 +1,80 @@
+/* Disassembler structures definitions for the ARC.
+ Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+ Contributed by Doug Evans (dje@cygnus.com).
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef ARCDIS_H
+#define ARCDIS_H
+
+enum
+{
+ BR_exec_when_no_jump,
+ BR_exec_always,
+ BR_exec_when_jump
+};
+
+enum Flow
+{
+ noflow,
+ direct_jump,
+ direct_call,
+ indirect_jump,
+ indirect_call,
+ invalid_instr
+};
+
+enum { no_reg = 99 };
+enum { allOperandsSize = 256 };
+
+struct arcDisState
+{
+ void *_this;
+ int instructionLen;
+ void (*err)(void*, const char*);
+ const char *(*coreRegName)(void*, int);
+ const char *(*auxRegName)(void*, int);
+ const char *(*condCodeName)(void*, int);
+ const char *(*instName)(void*, int, int, int*);
+
+ unsigned char* instruction;
+ unsigned index;
+ const char *comm[6]; /* instr name, cond, NOP, 3 operands */
+ int opWidth;
+ int targets[4];
+ int addresses[4];
+ /* Set as a side-effect of calling the disassembler.
+ Used only by the debugger. */
+ enum Flow flow;
+ int register_for_indirect_jump;
+ int ea_reg1, ea_reg2, _offset;
+ int _cond, _opcode;
+ unsigned long words[2];
+ char *commentBuffer;
+ char instrBuffer[40];
+ char operandBuffer[allOperandsSize];
+ char _ea_present;
+ char _mem_load;
+ char _load_len;
+ char nullifyMode;
+ unsigned char commNum;
+ unsigned char isBranch;
+ unsigned char tcnt;
+ unsigned char acnt;
+};
+
+#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
+
+#endif
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
new file mode 100644
index 0000000..0b10677
--- /dev/null
+++ b/opcodes/arc-ext.c
@@ -0,0 +1,259 @@
+/* ARC target-dependent stuff. Extension structure access functions
+ Copyright (C) 1995, 1997, 2000 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "bfd.h"
+#include "arc-ext.h"
+#include "libiberty.h"
+
+/* Extension structure */
+static struct arcExtMap arc_extension_map;
+
+/* Get the name of an extension instruction. */
+
+const char *
+arcExtMap_instName(int opcode, int minor, int *flags)
+{
+ if (opcode == 3)
+ {
+ /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */
+ if (minor < 0x09 || minor == 0x3f)
+ return 0;
+ else
+ opcode = 0x1f - 0x10 + minor - 0x09 + 1;
+ }
+ else
+ if (opcode < 0x10)
+ return 0;
+ else
+ opcode -= 0x10;
+ if (!arc_extension_map.instructions[opcode])
+ return 0;
+ *flags = arc_extension_map.instructions[opcode]->flags;
+ return arc_extension_map.instructions[opcode]->name;
+}
+
+/* Get the name of an extension core register. */
+
+const char *
+arcExtMap_coreRegName(int value)
+{
+ if (value < 32)
+ return 0;
+ return (const char *) arc_extension_map.coreRegisters[value-32];
+}
+
+/* Get the name of an extension condition code. */
+
+const char *
+arcExtMap_condCodeName(int value)
+{
+ if (value < 16)
+ return 0;
+ return (const char *) arc_extension_map.condCodes[value-16];
+}
+
+/* Get the name of an extension aux register. */
+
+const char *
+arcExtMap_auxRegName(long address)
+{
+ /* walk the list of aux reg names and find the name */
+ struct ExtAuxRegister *r;
+
+ for (r = arc_extension_map.auxRegisters; r; r = r->next) {
+ if (r->address == address)
+ return (const char *) r->name;
+ }
+ return 0;
+}
+
+/* Recursively free auxilliary register strcture pointers until
+ the list is empty. */
+
+static void
+clean_aux_registers(struct ExtAuxRegister *r)
+{
+ if (r -> next)
+ {
+ clean_aux_registers( r->next);
+ free(r -> name);
+ free(r -> next);
+ r ->next = NULL;
+ }
+ else
+ free(r -> name);
+}
+
+/* Free memory that has been allocated for the extensions. */
+
+static void
+cleanup_ext_map(void)
+{
+ struct ExtAuxRegister *r;
+ struct ExtInstruction *insn;
+ int i;
+
+ /* clean aux reg structure */
+ r = arc_extension_map.auxRegisters;
+ if (r)
+ {
+ (clean_aux_registers(r));
+ free(r);
+ }
+
+ /* clean instructions */
+ for (i = 0; i < NUM_EXT_INST; i++)
+ {
+ insn = arc_extension_map.instructions[i];
+ if (insn)
+ free(insn->name);
+ }
+
+ /* clean core reg struct */
+ for (i = 0; i < NUM_EXT_CORE; i++)
+ {
+ if (arc_extension_map.coreRegisters[i])
+ free(arc_extension_map.coreRegisters[i]);
+ }
+
+ for (i = 0; i < NUM_EXT_COND; i++) {
+ if (arc_extension_map.condCodes[i])
+ free(arc_extension_map.condCodes[i]);
+ }
+
+ memset(&arc_extension_map, 0, sizeof(struct arcExtMap));
+}
+
+int
+arcExtMap_add(void *base, unsigned long length)
+{
+ unsigned char *block = base;
+ unsigned char *p = block;
+
+ /* Clean up and reset everything if needed. */
+ cleanup_ext_map();
+
+ while (p && p < (block + length))
+ {
+ /* p[0] == length of record
+ p[1] == type of record
+ For instructions:
+ p[2] = opcode
+ p[3] = minor opcode (if opcode == 3)
+ p[4] = flags
+ p[5]+ = name
+ For core regs and condition codes:
+ p[2] = value
+ p[3]+ = name
+ For aux regs:
+ p[2..5] = value
+ p[6]+ = name
+ (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */
+
+ if (p[0] == 0)
+ return -1;
+
+ switch (p[1])
+ {
+ case EXT_INSTRUCTION:
+ {
+ char opcode = p[2];
+ char minor = p[3];
+ char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
+ struct ExtInstruction * insn =
+ (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
+
+ if (opcode==3)
+ opcode = 0x1f - 0x10 + minor - 0x09 + 1;
+ else
+ opcode -= 0x10;
+ insn -> flags = (char) *(p+4);
+ strcpy(insn_name, (p+5));
+ insn -> name = insn_name;
+ arc_extension_map.instructions[(int) opcode] = insn;
+ }
+ break;
+
+ case EXT_CORE_REGISTER:
+ {
+ char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
+
+ strcpy(core_name, (p+3));
+ arc_extension_map.coreRegisters[p[2]-32] = core_name;
+ }
+ break;
+
+ case EXT_COND_CODE:
+ {
+ char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
+ strcpy(cc_name, (p+3));
+ arc_extension_map.condCodes[p[2]-16] = cc_name;
+ }
+ break;
+
+ case EXT_AUX_REGISTER:
+ {
+ /* trickier -- need to store linked list to these */
+ struct ExtAuxRegister *newAuxRegister =
+ (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
+ char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
+
+ strcpy (aux_name, (p+6));
+ newAuxRegister->name = aux_name;
+ newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5];
+ newAuxRegister->next = arc_extension_map.auxRegisters;
+ arc_extension_map.auxRegisters = newAuxRegister;
+ }
+ break;
+
+ default:
+ return -1;
+
+ }
+ p += p[0]; /* move to next record */
+ }
+
+ return 0;
+}
+
+/* Load hw extension descibed in .extArcMap ELF section. */
+
+void
+build_ARC_extmap (text_bfd)
+ bfd *text_bfd;
+{
+ char *arcExtMap;
+ bfd_size_type count;
+ asection *p;
+
+ for (p = text_bfd->sections; p != NULL; p = p->next)
+ if (!strcmp (p->name, ".arcextmap"))
+ {
+ count = p->_raw_size;
+ arcExtMap = (char *) xmalloc (count);
+ if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
+ {
+ arcExtMap_add ((PTR) arcExtMap, count);
+ break;
+ }
+ free ((PTR) arcExtMap);
+ }
+}
diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
new file mode 100644
index 0000000..aca9213
--- /dev/null
+++ b/opcodes/arc-ext.h
@@ -0,0 +1,62 @@
+/* ARC target-dependent stuff. Extension data structures.
+ Copyright (C) 1995, 1997, 2000 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef ARCEXT_H
+#define ARCEXT_H
+
+enum {EXT_INSTRUCTION = 0};
+enum {EXT_CORE_REGISTER = 1};
+enum {EXT_AUX_REGISTER = 2};
+enum {EXT_COND_CODE = 3};
+
+enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
+enum {NUM_EXT_CORE = 59-32+1};
+enum {NUM_EXT_COND = 0x1f-0x10+1};
+
+struct ExtInstruction
+{
+ char flags;
+ char *name;
+};
+
+struct ExtAuxRegister
+{
+ long address;
+ char *name;
+ struct ExtAuxRegister *next;
+};
+
+struct arcExtMap
+{
+ struct ExtAuxRegister *auxRegisters;
+ struct ExtInstruction *instructions[NUM_EXT_INST];
+ unsigned char *coreRegisters[NUM_EXT_CORE];
+ unsigned char *condCodes[NUM_EXT_COND];
+};
+
+extern int arcExtMap_add(void*, unsigned long);
+extern const char *arcExtMap_coreRegName(int);
+extern const char *arcExtMap_auxRegName(long);
+extern const char *arcExtMap_condCodeName(int);
+extern const char *arcExtMap_instName(int, int, int*);
+extern void build_ARC_extmap(bfd *);
+
+#define IGNORE_FIRST_OPD 1
+
+#endif
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index f17ffc0..12ee62a 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1,5 +1,5 @@
/* Opcode table for the ARC.
- Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1997, 1998, 2000 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This program is free software; you can redistribute it and/or modify
@@ -13,17 +13,12 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
-#include "sysdep.h"
+#include "ansidecl.h"
#include "opcode/arc.h"
-#include "opintl.h"
-
-#ifndef NULL
-#define NULL 0
-#endif
#define INSERT_FN(fn) \
static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
@@ -36,22 +31,43 @@ static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
INSERT_FN (insert_reg);
INSERT_FN (insert_shimmfinish);
INSERT_FN (insert_limmfinish);
-INSERT_FN (insert_shimmoffset);
-INSERT_FN (insert_shimmzero);
+INSERT_FN (insert_offset);
+INSERT_FN (insert_base);
+INSERT_FN (insert_st_syntax);
+INSERT_FN (insert_ld_syntax);
+INSERT_FN (insert_addr_wb);
INSERT_FN (insert_flag);
+INSERT_FN (insert_nullify);
INSERT_FN (insert_flagfinish);
INSERT_FN (insert_cond);
INSERT_FN (insert_forcelimm);
INSERT_FN (insert_reladdr);
INSERT_FN (insert_absaddr);
+INSERT_FN (insert_jumpflags);
INSERT_FN (insert_unopmacro);
EXTRACT_FN (extract_reg);
+EXTRACT_FN (extract_ld_offset);
+EXTRACT_FN (extract_ld_syntax);
+EXTRACT_FN (extract_st_offset);
+EXTRACT_FN (extract_st_syntax);
EXTRACT_FN (extract_flag);
EXTRACT_FN (extract_cond);
EXTRACT_FN (extract_reladdr);
+EXTRACT_FN (extract_jumpflags);
EXTRACT_FN (extract_unopmacro);
+enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
+
+#define OPERANDS 3
+
+enum operand ls_operand[OPERANDS];
+
+#define LS_VALUE 0
+#define LS_DEST 0
+#define LS_BASE 1
+#define LS_OFFSET 2
+
/* Various types of ARC operands, including insn suffixes. */
/* Insn format values:
@@ -61,8 +77,13 @@ EXTRACT_FN (extract_unopmacro);
'c' REGC register C field
'S' SHIMMFINISH finish inserting a shimm value
'L' LIMMFINISH finish inserting a limm value
- 'd' SHIMMOFFSET shimm offset in ld,st insns
- '0' SHIMMZERO 0 shimm value in ld,st insns
+ 'o' OFFSET offset in st insns
+ 'O' OFFSET offset in ld insns
+ '0' SYNTAX_ST_NE enforce store insn syntax, no errors
+ '1' SYNTAX_LD_NE enforce load insn syntax, no errors
+ '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
+ '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
+ 's' BASE base in st insn
'f' FLAG F flag
'F' FLAGFINISH finish inserting the F flag
'G' FLAGINSN insert F flag in "flag" insn
@@ -71,6 +92,7 @@ EXTRACT_FN (extract_unopmacro);
'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
'B' BRANCH branch address (22 bit pc relative)
'J' JUMP jump address (26 bit absolute)
+ 'j' JUMPFLAGS optional high order bits of 'J'
'z' SIZE1 size field in ld a,[b,c]
'Z' SIZE10 size field in ld a,[b,shimm]
'y' SIZE22 size field in st c,[b,shimm]
@@ -92,28 +114,27 @@ EXTRACT_FN (extract_unopmacro);
Fields are:
- CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN
-*/
+ CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */
const struct arc_operand arc_operands[] =
{
-/* place holder (??? not sure if needed) */
+/* place holder (??? not sure if needed). */
#define UNUSED 0
- { 0 },
+ { 0, 0, 0, 0, 0, 0 },
-/* register A or shimm/limm indicator */
+/* register A or shimm/limm indicator. */
#define REGA (UNUSED + 1)
- { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+ { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-/* register B or shimm/limm indicator */
+/* register B or shimm/limm indicator. */
#define REGB (REGA + 1)
- { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+ { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-/* register C or shimm/limm indicator */
+/* register C or shimm/limm indicator. */
#define REGC (REGB + 1)
- { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+ { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-/* fake operand used to insert shimm value into most instructions */
+/* fake operand used to insert shimm value into most instructions. */
#define SHIMMFINISH (REGC + 1)
{ 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
@@ -121,123 +142,141 @@ const struct arc_operand arc_operands[] =
#define LIMMFINISH (SHIMMFINISH + 1)
{ 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
-/* shimm operand when there is no reg indicator (ld,st) */
-#define SHIMMOFFSET (LIMMFINISH + 1)
- { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 },
+/* shimm operand when there is no reg indicator (st). */
+#define ST_OFFSET (LIMMFINISH + 1)
+ { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
+
+/* shimm operand when there is no reg indicator (ld). */
+#define LD_OFFSET (ST_OFFSET + 1)
+ { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
+
+/* operand for base. */
+#define BASE (LD_OFFSET + 1)
+ { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
-/* 0 shimm operand for ld,st insns */
-#define SHIMMZERO (SHIMMOFFSET + 1)
- { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 },
+/* 0 enforce syntax for st insns. */
+#define SYNTAX_ST_NE (BASE + 1)
+ { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
-/* flag update bit (insertion is defered until we know how) */
-#define FLAG (SHIMMZERO + 1)
+/* 1 enforce syntax for ld insns. */
+#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
+ { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
+
+/* 0 enforce syntax for st insns. */
+#define SYNTAX_ST (SYNTAX_LD_NE + 1)
+ { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
+
+/* 0 enforce syntax for ld insns. */
+#define SYNTAX_LD (SYNTAX_ST + 1)
+ { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
+
+/* flag update bit (insertion is defered until we know how). */
+#define FLAG (SYNTAX_LD + 1)
{ 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
-/* fake utility operand to finish 'f' suffix handling */
+/* fake utility operand to finish 'f' suffix handling. */
#define FLAGFINISH (FLAG + 1)
{ 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
-/* fake utility operand to set the 'f' flag for the "flag" insn */
+/* fake utility operand to set the 'f' flag for the "flag" insn. */
#define FLAGINSN (FLAGFINISH + 1)
{ 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
-/* branch delay types */
+/* branch delay types. */
#define DELAY (FLAGINSN + 1)
- { 'n', 2, 5, ARC_OPERAND_SUFFIX },
+ { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
-/* conditions */
+/* conditions. */
#define COND (DELAY + 1)
{ 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
-/* set `cond_p' to 1 to ensure a constant is treated as a limm */
+/* set `cond_p' to 1 to ensure a constant is treated as a limm. */
#define FORCELIMM (COND + 1)
- { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
+ { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
-/* branch address; b, bl, and lp insns */
+/* branch address; b, bl, and lp insns. */
#define BRANCH (FORCELIMM + 1)
- { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
+ { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
/* jump address; j insn (this is basically the same as 'L' except that the
- value is right shifted by 2) */
+ value is right shifted by 2). */
#define JUMP (BRANCH + 1)
- { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
+ { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
+
+/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */
+#define JUMPFLAGS (JUMP + 1)
+ { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
-/* size field, stored in bit 1,2 */
-#define SIZE1 (JUMP + 1)
- { 'z', 2, 1, ARC_OPERAND_SUFFIX },
+/* size field, stored in bit 1,2. */
+#define SIZE1 (JUMPFLAGS + 1)
+ { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
-/* size field, stored in bit 10,11 */
+/* size field, stored in bit 10,11. */
#define SIZE10 (SIZE1 + 1)
- { 'Z', 2, 10, ARC_OPERAND_SUFFIX, },
+ { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
-/* size field, stored in bit 22,23 */
+/* size field, stored in bit 22,23. */
#define SIZE22 (SIZE10 + 1)
- { 'y', 2, 22, ARC_OPERAND_SUFFIX, },
+ { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
-/* sign extend field, stored in bit 0 */
+/* sign extend field, stored in bit 0. */
#define SIGN0 (SIZE22 + 1)
- { 'x', 1, 0, ARC_OPERAND_SUFFIX },
+ { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
-/* sign extend field, stored in bit 9 */
+/* sign extend field, stored in bit 9. */
#define SIGN9 (SIGN0 + 1)
- { 'X', 1, 9, ARC_OPERAND_SUFFIX },
+ { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
-/* address write back, stored in bit 3 */
+/* address write back, stored in bit 3. */
#define ADDRESS3 (SIGN9 + 1)
- { 'w', 1, 3, ARC_OPERAND_SUFFIX },
+ { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-/* address write back, stored in bit 12 */
+/* address write back, stored in bit 12. */
#define ADDRESS12 (ADDRESS3 + 1)
- { 'W', 1, 12, ARC_OPERAND_SUFFIX },
+ { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-/* address write back, stored in bit 24 */
+/* address write back, stored in bit 24. */
#define ADDRESS24 (ADDRESS12 + 1)
- { 'v', 1, 24, ARC_OPERAND_SUFFIX },
+ { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-/* cache bypass, stored in bit 5 */
+/* cache bypass, stored in bit 5. */
#define CACHEBYPASS5 (ADDRESS24 + 1)
- { 'e', 1, 5, ARC_OPERAND_SUFFIX },
+ { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
-/* cache bypass, stored in bit 14 */
+/* cache bypass, stored in bit 14. */
#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
- { 'E', 1, 14, ARC_OPERAND_SUFFIX },
+ { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
-/* cache bypass, stored in bit 26 */
+/* cache bypass, stored in bit 26. */
#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
- { 'D', 1, 26, ARC_OPERAND_SUFFIX },
+ { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
-/* unop macro, used to copy REGB to REGC */
+/* unop macro, used to copy REGB to REGC. */
#define UNOPMACRO (CACHEBYPASS26 + 1)
{ 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
/* '.' modifier ('.' required). */
#define MODDOT (UNOPMACRO + 1)
- { '.', 1, 0, ARC_MOD_DOT },
+ { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
/* Dummy 'r' modifier for the register table.
It's called a "dummy" because there's no point in inserting an 'r' into all
the %a/%b/%c occurrences in the insn table. */
#define REG (MODDOT + 1)
- { 'r', 6, 0, ARC_MOD_REG },
+ { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
/* Known auxiliary register modifier (stored in shimm field). */
#define AUXREG (REG + 1)
- { 'A', 9, 0, ARC_MOD_AUXREG },
+ { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
-/* end of list place holder */
- { 0 }
+/* end of list place holder. */
+ { 0, 0, 0, 0, 0, 0 }
};
/* Given a format letter, yields the index into `arc_operands'.
eg: arc_operand_map['a'] = REGA. */
unsigned char arc_operand_map[256];
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
-
/* ARC instructions.
Longer versions of insns must appear before shorter ones (if gas sees
@@ -246,110 +285,141 @@ unsigned char arc_operand_map[256];
Instructions that are really macros based on other insns must appear
before the real insn so they're chosen when disassembling. Eg: The `mov'
- insn is really the `and' insn.
-
- This table is best viewed on a wide screen (161 columns). I'd prefer to
- keep it this way. The rest of the file, however, should be viewable on an
- 80 column terminal. */
-
-/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
- a more general facility for dealing with macros which could be used if
- we need to. */
-
-/* This table can't be `const' because members `next_asm' and `next_dis' are
- computed at run-time. We could split this into two, but that doesn't seem
- worth it. */
+ insn is really the `and' insn. */
-struct arc_opcode arc_opcodes[] = {
+struct arc_opcode arc_opcodes[] =
+{
+ /* Base case instruction set (core versions 5-8) */
- /* Macros appear first. */
/* "mov" is really an "and". */
- { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
+ { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
/* "asl" is really an "add". */
- { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
/* "lsl" is really an "add". */
- { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
/* "nop" is really an "xor". */
- { "nop", 0xffffffff, 0x7fffffff },
+ { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
/* "rlc" is really an "adc". */
- { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
-
- /* The rest of these needn't be sorted, but it helps to find them if they are. */
- { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
- { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
- { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
- { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
- { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
- { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH },
- { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH },
- { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
- { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
- { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
- /* %Q: force cond_p=1 --> no shimm values */
- /* ??? This insn allows an optional flags spec. */
- { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
- /* Put opcode 1 ld insns first so shimm gets prefered over limm. */
- /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
- { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
- { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
- { "lp%q%.n %B", I(-1), I(6), },
- { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
- { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
- { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
- { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
- { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
- { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
- { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
- { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
- { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
- /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
- { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) },
- { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
- { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
+ { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
+ { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
+ { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
+ { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
+ { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
+ { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 },
+ { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
+ { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
+ { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
+ { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
+ { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
+ { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
+ /* %Q: force cond_p=1 -> no shimm values. This insn allows an
+ optional flags spec. */
+ { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ /* This insn allows an optional flags spec. */
+ { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ /* Put opcode 1 ld insns first so shimm gets prefered over limm.
+ "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
+ { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
+ { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+ { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+ { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
+ { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
+ { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
+ { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
+ { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
+ { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
+ { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
+ { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 },
+ { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
+ { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
+ { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
+ /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
+ { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+ { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+ { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 },
+ { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 }
};
+
const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
const struct arc_operand_value arc_reg_names[] =
{
- /* Sort this so that the first 61 entries are sequential.
- IE: For each i (i<61), arc_reg_names[i].value == i. */
-
- { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG },
- { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG },
- { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG },
- { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG },
- { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG },
- { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG },
- { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG },
- { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG },
- { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG },
- { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG },
- { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG },
- { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG },
- { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG },
- { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG },
- { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG },
- { "lp_count", 60, REG },
-
- /* I'd prefer to output these as "fp" and "sp" by default, but we still need
- to recognize the canonical values. */
- { "r27", 27, REG }, { "r28", 28, REG },
-
- /* Someone may wish to refer to these in this way, and it's probably a
- good idea to reserve them as such anyway. */
- { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
-
- /* Standard auxiliary registers. */
- { "status", 0, AUXREG },
- { "semaphore", 1, AUXREG },
- { "lp_start", 2, AUXREG },
- { "lp_end", 3, AUXREG },
- { "identity", 4, AUXREG },
- { "debug", 5, AUXREG },
+ /* Core register set r0-r63. */
+
+ /* r0-r28 - general purpose registers. */
+ { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
+ { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
+ { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
+ { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
+ { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
+ { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
+ { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
+ { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
+ { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
+ { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
+ /* Maskable interrupt link register. */
+ { "ilink1", 29, REG, 0 },
+ /* Maskable interrupt link register. */
+ { "ilink2", 30, REG, 0 },
+ /* Branch-link register. */
+ { "blink", 31, REG, 0 },
+
+ /* r32-r59 reserved for extensions. */
+ { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
+ { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
+ { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
+ { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
+ { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
+ { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
+ { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
+ { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
+ { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
+ { "r59", 59, REG, 0 },
+
+ /* Loop count register (24 bits). */
+ { "lp_count", 60, REG, ARC_REGISTER_READONLY },
+ /* Short immediate data indicator setting flags. */
+ { "r61", 61, REG, ARC_REGISTER_READONLY },
+ /* Long immediate data indicator setting flags. */
+ { "r62", 62, REG, ARC_REGISTER_READONLY },
+ /* Short immediate data indicator not setting flags. */
+ { "r63", 63, REG, ARC_REGISTER_READONLY },
+
+ /* Small-data base register. */
+ { "gp", 26, REG, 0 },
+ /* Frame pointer. */
+ { "fp", 27, REG, 0 },
+ /* Stack pointer. */
+ { "sp", 28, REG, 0 },
+
+ { "r29", 29, REG, 0 },
+ { "r30", 30, REG, 0 },
+ { "r31", 31, REG, 0 },
+ { "r60", 60, REG, 0 },
+
+ /* Auxiliary register set. */
+
+ /* Auxiliary register address map:
+ 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
+ 0xfffffeff-0x80000000 - customer limm allocation
+ 0x7fffffff-0x00000100 - ARC limm allocation
+ 0x000000ff-0x00000000 - ARC shimm allocation */
+
+ /* Base case auxiliary registers (shimm address). */
+ { "status", 0x00, AUXREG, 0 },
+ { "semaphore", 0x01, AUXREG, 0 },
+ { "lp_start", 0x02, AUXREG, 0 },
+ { "lp_end", 0x03, AUXREG, 0 },
+ { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY },
+ { "debug", 0x05, AUXREG, 0 },
};
-const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
+
+const int arc_reg_names_count =
+ sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
/* The suffix table.
Operands with the same name must be stored together. */
@@ -357,58 +427,64 @@ const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0
const struct arc_operand_value arc_suffixes[] =
{
/* Entry 0 is special, default values aren't printed by the disassembler. */
- { "", 0, -1 },
- { "al", 0, COND },
- { "ra", 0, COND },
- { "eq", 1, COND },
- { "z", 1, COND },
- { "ne", 2, COND },
- { "nz", 2, COND },
- { "p", 3, COND },
- { "pl", 3, COND },
- { "n", 4, COND },
- { "mi", 4, COND },
- { "c", 5, COND },
- { "cs", 5, COND },
- { "lo", 5, COND },
- { "nc", 6, COND },
- { "cc", 6, COND },
- { "hs", 6, COND },
- { "v", 7, COND },
- { "vs", 7, COND },
- { "nv", 8, COND },
- { "vc", 8, COND },
- { "gt", 9, COND },
- { "ge", 10, COND },
- { "lt", 11, COND },
- { "le", 12, COND },
- { "hi", 13, COND },
- { "ls", 14, COND },
- { "pnz", 15, COND },
- { "f", 1, FLAG },
- { "nd", ARC_DELAY_NONE, DELAY },
- { "d", ARC_DELAY_NORMAL, DELAY },
- { "jd", ARC_DELAY_JUMP, DELAY },
-/*{ "b", 7, SIZEEXT },*/
-/*{ "b", 5, SIZESEX },*/
- { "b", 1, SIZE1 },
- { "b", 1, SIZE10 },
- { "b", 1, SIZE22 },
-/*{ "w", 8, SIZEEXT },*/
-/*{ "w", 6, SIZESEX },*/
- { "w", 2, SIZE1 },
- { "w", 2, SIZE10 },
- { "w", 2, SIZE22 },
- { "x", 1, SIGN0 },
- { "x", 1, SIGN9 },
- { "a", 1, ADDRESS3 },
- { "a", 1, ADDRESS12 },
- { "a", 1, ADDRESS24 },
- { "di", 1, CACHEBYPASS5 },
- { "di", 1, CACHEBYPASS14 },
- { "di", 1, CACHEBYPASS26 },
+ { "", 0, -1, 0 },
+
+ /* Base case condition codes. */
+ { "al", 0, COND, 0 },
+ { "ra", 0, COND, 0 },
+ { "eq", 1, COND, 0 },
+ { "z", 1, COND, 0 },
+ { "ne", 2, COND, 0 },
+ { "nz", 2, COND, 0 },
+ { "pl", 3, COND, 0 },
+ { "p", 3, COND, 0 },
+ { "mi", 4, COND, 0 },
+ { "n", 4, COND, 0 },
+ { "cs", 5, COND, 0 },
+ { "c", 5, COND, 0 },
+ { "lo", 5, COND, 0 },
+ { "cc", 6, COND, 0 },
+ { "nc", 6, COND, 0 },
+ { "hs", 6, COND, 0 },
+ { "vs", 7, COND, 0 },
+ { "v", 7, COND, 0 },
+ { "vc", 8, COND, 0 },
+ { "nv", 8, COND, 0 },
+ { "gt", 9, COND, 0 },
+ { "ge", 10, COND, 0 },
+ { "lt", 11, COND, 0 },
+ { "le", 12, COND, 0 },
+ { "hi", 13, COND, 0 },
+ { "ls", 14, COND, 0 },
+ { "pnz", 15, COND, 0 },
+
+ /* Condition codes 16-31 reserved for extensions. */
+
+ { "f", 1, FLAG, 0 },
+
+ { "nd", ARC_DELAY_NONE, DELAY, 0 },
+ { "d", ARC_DELAY_NORMAL, DELAY, 0 },
+ { "jd", ARC_DELAY_JUMP, DELAY, 0 },
+
+ { "b", 1, SIZE1, 0 },
+ { "b", 1, SIZE10, 0 },
+ { "b", 1, SIZE22, 0 },
+ { "w", 2, SIZE1, 0 },
+ { "w", 2, SIZE10, 0 },
+ { "w", 2, SIZE22, 0 },
+ { "x", 1, SIGN0, 0 },
+ { "x", 1, SIGN9, 0 },
+ { "a", 1, ADDRESS3, 0 },
+ { "a", 1, ADDRESS12, 0 },
+ { "a", 1, ADDRESS24, 0 },
+
+ { "di", 1, CACHEBYPASS5, 0 },
+ { "di", 1, CACHEBYPASS14, 0 },
+ { "di", 1, CACHEBYPASS26, 0 },
};
-const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+
+const int arc_suffixes_count =
+ sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
/* Indexed by first letter of opcode. Points to chain of opcodes with same
first letter. */
@@ -429,10 +505,12 @@ arc_get_opcode_mach (bfd_mach, big_p)
int bfd_mach, big_p;
{
static int mach_type_map[] =
- {
- ARC_MACH_BASE
- };
-
+ {
+ ARC_MACH_5,
+ ARC_MACH_6,
+ ARC_MACH_7,
+ ARC_MACH_8
+ };
return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
}
@@ -453,8 +531,6 @@ arc_opcode_init_tables (flags)
/* We may be intentionally called more than once (for example gdb will call
us each time the user switches cpu). These tables only need to be init'd
once though. */
- /* ??? We can remove the need for arc_opcode_supported by taking it into
- account here, but I'm not sure I want to do that yet (if ever). */
if (!init_p)
{
register int i,n;
@@ -490,23 +566,7 @@ int
arc_opcode_supported (opcode)
const struct arc_opcode *opcode;
{
- if (ARC_OPCODE_CPU (opcode->flags) == 0)
- return 1;
- if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
- return 1;
- return 0;
-}
-
-/* Return non-zero if OPVAL is supported on the specified cpu.
- Cpu selection is made when calling `arc_opcode_init_tables'. */
-
-int
-arc_opval_supported (opval)
- const struct arc_operand_value *opval;
-{
- if (ARC_OPVAL_CPU (opval->flags) == 0)
- return 1;
- if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
+ if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
return 1;
return 0;
}
@@ -535,14 +595,26 @@ static int flag_p;
/* Nonzero if we've finished processing the 'f' suffix. */
static int flagshimm_handled_p;
+/* Nonzero if we've seen a 'a' suffix (address writeback). */
+static int addrwb_p;
+
/* Nonzero if we've seen a 'q' suffix (condition code). */
static int cond_p;
+/* Nonzero if we've inserted a nullify condition. */
+static int nullify_p;
+
+/* The value of the a nullify condition we inserted. */
+static int nullify;
+
+/* Nonzero if we've inserted jumpflags. */
+static int jumpflags_p;
+
/* Nonzero if we've inserted a shimm. */
static int shimm_p;
/* The value of the shimm we inserted (each insn only gets one but it can
- appear multiple times. */
+ appear multiple times). */
static int shimm;
/* Nonzero if we've inserted a limm (during assembly) or seen a limm
@@ -560,11 +632,20 @@ static long limm;
void
arc_opcode_init_insert ()
{
+ int i;
+
+ for(i = 0; i < OPERANDS; i++)
+ ls_operand[i] = OP_NONE;
+
flag_p = 0;
flagshimm_handled_p = 0;
cond_p = 0;
+ addrwb_p = 0;
shimm_p = 0;
limm_p = 0;
+ jumpflags_p = 0;
+ nullify_p = 0;
+ nullify = 0; /* the default is important. */
}
/* Called by the assembler to see if the insn has a limm operand.
@@ -572,7 +653,7 @@ arc_opcode_init_insert ()
int
arc_opcode_limm_p (limmp)
- long *limmp;
+ long *limmp;
{
if (limmp)
*limmp = limm;
@@ -586,14 +667,15 @@ arc_opcode_limm_p (limmp)
static arc_insn
insert_reg (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods;
+ const struct arc_operand_value *reg;
+ long value;
+ const char **errmsg;
{
static char buf[100];
+ enum operand op_type = OP_NONE;
if (reg == NULL)
{
@@ -609,16 +691,30 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
we have to use a limm. */
&& (!shimm_p || shimm == value))
{
- int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
- flagshimm_handled_p = 1;
- shimm_p = 1;
- shimm = value;
+ int marker;
+
+ op_type = OP_SHIMM;
+ /* forget about shimm as dest mlm. */
+
+ if('a' != operand->fmt)
+ {
+ shimm_p = 1;
+ shimm = value;
+ flagshimm_handled_p = 1;
+ marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
+ }
+ else
+ {
+ /* don't request flag setting on shimm as dest. */
+ marker = ARC_REG_SHIMM;
+ }
insn |= marker << operand->shift;
- /* insn |= value & 511; - done later */
+ /* insn |= value & 511; - done later. */
}
/* We have to use a limm. If we've already seen one they must match. */
else if (!limm_p || limm == value)
{
+ op_type = OP_LIMM;
limm_p = 1;
limm = value;
insn |= ARC_REG_LIMM << operand->shift;
@@ -626,7 +722,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
}
else
{
- *errmsg = _("unable to fit different valued constants into instruction");
+ *errmsg = "unable to fit different valued constants into instruction";
}
}
else
@@ -636,27 +732,66 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
if (reg->type == AUXREG)
{
if (!(mods & ARC_MOD_AUXREG))
- *errmsg = _("auxiliary register not allowed here");
+ *errmsg = "auxiliary register not allowed here";
else
{
+ if((insn & I(-1)) == I(2)) /* check for use validity. */
+ {
+ if(reg->flags & ARC_REGISTER_READONLY)
+ *errmsg = "attempt to set readonly register";
+ }
+ else
+ {
+ if(reg->flags & ARC_REGISTER_WRITEONLY)
+ *errmsg = "attempt to read writeonly register";
+ }
insn |= ARC_REG_SHIMM << operand->shift;
insn |= reg->value << arc_operands[reg->type].shift;
}
}
else
{
+ /* check for use validity. */
+ if('a' == operand->fmt || ((insn & I(-1)) < I(2)))
+ {
+ if(reg->flags & ARC_REGISTER_READONLY)
+ *errmsg = "attempt to set readonly register";
+ }
+ if('a' != operand->fmt)
+ {
+ if(reg->flags & ARC_REGISTER_WRITEONLY)
+ *errmsg = "attempt to read writeonly register";
+ }
/* We should never get an invalid register number here. */
if ((unsigned int) reg->value > 60)
{
- /* xgettext:c-format */
- sprintf (buf, _("invalid register number `%d'"), reg->value);
+ sprintf (buf, "invalid register number `%d'", reg->value);
*errmsg = buf;
}
- else
- insn |= reg->value << operand->shift;
+ insn |= reg->value << operand->shift;
+ op_type = OP_REG;
}
}
+ switch (operand->fmt)
+ {
+ case 'a':
+ ls_operand[LS_DEST] = op_type;
+ break;
+ case 's':
+ ls_operand[LS_BASE] = op_type;
+ break;
+ case 'c':
+ if ((insn & I(-1)) == I(2))
+ ls_operand[LS_VALUE] = op_type;
+ else
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ case 'o': case 'O':
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ }
+
return insn;
}
@@ -664,18 +799,34 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_flag (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
/* We can't store anything in the insn until we've parsed the registers.
Just record the fact that we've got this flag. `insert_reg' will use it
to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
flag_p = 1;
+ return insn;
+}
+/* Called when we see an nullify condition. */
+
+static arc_insn
+insert_nullify (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value;
+ const char **errmsg ATTRIBUTE_UNUSED;
+{
+ nullify_p = 1;
+ insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ nullify = value;
return insn;
}
@@ -685,12 +836,12 @@ insert_flag (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_flagfinish (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
if (flag_p && !flagshimm_handled_p)
{
@@ -706,12 +857,12 @@ insert_flagfinish (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_cond (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
cond_p = 1;
insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
@@ -726,34 +877,100 @@ insert_cond (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_forcelimm (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
cond_p = 1;
return insn;
}
-/* Used in ld/st insns to handle the shimm offset field. */
+static arc_insn
+insert_addr_wb (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
+{
+ addrwb_p = 1 << operand->shift;
+ return insn;
+}
+
+static arc_insn
+insert_base (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods;
+ const struct arc_operand_value *reg;
+ long value;
+ const char **errmsg;
+{
+ if (reg != NULL)
+ {
+ arc_insn myinsn;
+ myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
+ insn |= B(myinsn);
+ ls_operand[LS_BASE] = OP_REG;
+ }
+ else if (ARC_SHIMM_CONST_P (value) && !cond_p)
+ {
+ if (shimm_p && value != shimm)
+ {
+ /* convert the previous shimm operand to a limm. */
+ limm_p = 1;
+ limm = shimm;
+ insn &= ~C(-1); /* we know where the value is in insn. */
+ insn |= C(ARC_REG_LIMM);
+ ls_operand[LS_VALUE] = OP_LIMM;
+ }
+ insn |= ARC_REG_SHIMM << operand->shift;
+ shimm_p = 1;
+ shimm = value;
+ ls_operand[LS_BASE] = OP_SHIMM;
+ }
+ else
+ {
+ if (limm_p && value != limm)
+ {
+ *errmsg = "too many long constants";
+ return insn;
+ }
+ limm_p = 1;
+ limm = value;
+ insn |= B(ARC_REG_LIMM);
+ ls_operand[LS_BASE] = OP_LIMM;
+ }
+
+ return insn;
+}
+
+/* Used in ld/st insns to handle the offset field. We don't try to
+ match operand syntax here. we catch bad combinations later. */
static arc_insn
-insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+insert_offset (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods;
+ const struct arc_operand_value *reg;
+ long value;
+ const char **errmsg;
{
long minval, maxval;
- static char buf[100];
if (reg != NULL)
{
- *errmsg = "register appears where shimm value expected";
+ arc_insn myinsn;
+ myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
+ ls_operand[LS_OFFSET] = OP_REG;
+ if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */
+ if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */
+ insn |= C(myinsn);
}
else
{
@@ -769,46 +986,281 @@ insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
minval = 0;
maxval = (1 << operand->bits) - 1;
}
- if (value < minval || value > maxval)
+ if ((cond_p && !limm_p) || (value < minval || value > maxval))
{
- /* xgettext:c-format */
- sprintf (buf, _("value won't fit in range %ld - %ld"),
- minval, maxval);
- *errmsg = buf;
+ if (limm_p && value != limm)
+ {
+ *errmsg = "too many long constants";
+ }
+ else
+ {
+ limm_p = 1;
+ limm = value;
+ if (operand->flags & ARC_OPERAND_STORE)
+ insn |= B(ARC_REG_LIMM);
+ if (operand->flags & ARC_OPERAND_LOAD)
+ insn |= C(ARC_REG_LIMM);
+ ls_operand[LS_OFFSET] = OP_LIMM;
+ }
}
else
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ {
+ if ((value < minval || value > maxval))
+ *errmsg = "need too many limms";
+ else if (shimm_p && value != shimm)
+ {
+ /* check for bad operand combinations before we lose info about them. */
+ if ((insn & I(-1)) == I(1))
+ {
+ *errmsg = "to many shimms in load";
+ goto out;
+ }
+ if (limm_p && operand->flags & ARC_OPERAND_LOAD)
+ {
+ *errmsg = "too many long constants";
+ goto out;
+ }
+ /* convert what we thought was a shimm to a limm. */
+ limm_p = 1;
+ limm = shimm;
+ if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+ {
+ insn &= ~C(-1);
+ insn |= C(ARC_REG_LIMM);
+ ls_operand[LS_VALUE] = OP_LIMM;
+ }
+ if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+ {
+ insn &= ~B(-1);
+ insn |= B(ARC_REG_LIMM);
+ ls_operand[LS_BASE] = OP_LIMM;
+ }
+ }
+ shimm = value;
+ shimm_p = 1;
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ }
}
+ out:
return insn;
}
-/* Used in ld/st insns when the shimm offset is 0. */
+/* Used in st insns to do final disasemble syntax check. */
+
+static long
+extract_st_syntax (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+#define ST_SYNTAX(V,B,O) \
+((ls_operand[LS_VALUE] == (V) && \
+ ls_operand[LS_BASE] == (B) && \
+ ls_operand[LS_OFFSET] == (O)))
+ if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+ || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
+ || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+ || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
+ || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
+ || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
+ || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+ || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
+ || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
+ *invalid = 1;
+ return 0;
+}
+
+int
+arc_limm_fixup_adjust(insn)
+ arc_insn insn;
+{
+ int retval = 0;
+
+ /* check for st shimm,[limm]. */
+ if ((insn & (I(-1) | C(-1) | B(-1))) ==
+ (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
+ {
+ retval = insn & 0x1ff;
+ if (retval & 0x100) /* sign extend 9 bit offset. */
+ retval |= ~0x1ff;
+ }
+ return(-retval); /* negate offset for return. */
+}
+
+/* Used in st insns to do final syntax check. */
+
+static arc_insn
+insert_st_syntax (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg;
+{
+ if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
+ {
+ /* change an illegal insn into a legal one, it's easier to
+ do it here than to try to handle it during operand scan. */
+ limm_p = 1;
+ limm = shimm;
+ shimm_p = 0;
+ shimm = 0;
+ insn = insn & ~(C(-1) | 511);
+ insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
+ ls_operand[LS_VALUE] = OP_LIMM;
+ }
+
+ if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE))
+ {
+ /* try to salvage this syntax. */
+ if (shimm & 0x1) /* odd shimms won't work. */
+ {
+ if (limm_p) /* do we have a limm already? */
+ {
+ *errmsg = "impossible store";
+ }
+ limm_p = 1;
+ limm = shimm;
+ shimm = 0;
+ shimm_p = 0;
+ insn = insn & ~(B(-1) | 511);
+ insn |= B(ARC_REG_LIMM);
+ ls_operand[LS_BASE] = OP_LIMM;
+ }
+ else
+ {
+ shimm >>= 1;
+ insn = insn & ~511;
+ insn |= shimm;
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ }
+ }
+ if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
+ {
+ limm += arc_limm_fixup_adjust(insn);
+ }
+ if (ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) && (shimm * 2 == limm))
+ {
+ insn &= ~C(-1);
+ limm_p = 0;
+ limm = 0;
+ insn |= C(ARC_REG_SHIMM);
+ ls_operand[LS_VALUE] = OP_SHIMM;
+ }
+ if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE)
+ || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
+ || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
+ || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
+ || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE)
+ || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)
+ || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
+ *errmsg = "st operand error";
+ if (addrwb_p)
+ {
+ if (ls_operand[LS_BASE] != OP_REG)
+ *errmsg = "address writeback not allowed";
+ insn |= addrwb_p;
+ }
+ if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
+ *errmsg = "store value must be zero";
+ return insn;
+}
+
+/* Used in ld insns to do final syntax check. */
static arc_insn
-insert_shimmzero (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg;
{
- shimm_p = 1;
- shimm = 0;
+#define LD_SYNTAX(D,B,O) \
+((ls_operand[LS_DEST] == (D) && \
+ ls_operand[LS_BASE] == (B) && \
+ ls_operand[LS_OFFSET] == (O)))
+
+ int test = insn & I(-1);
+
+ if (!(test == I(1)))
+ {
+ if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+ || ls_operand[LS_OFFSET] == OP_SHIMM))
+ *errmsg = "invalid load/shimm insn";
+ }
+ if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
+ || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
+ || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
+ || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
+ || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+ *errmsg = "ld operand error";
+ if (addrwb_p)
+ {
+ if (ls_operand[LS_BASE] != OP_REG)
+ *errmsg = "address writeback not allowed";
+ insn |= addrwb_p;
+ }
return insn;
}
+/* Used in ld insns to do final syntax check. */
+
+static long
+extract_ld_syntax (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+ int test = insn[0] & I(-1);
+
+ if (!(test == I(1)))
+ {
+ if((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+ || ls_operand[LS_OFFSET] == OP_SHIMM))
+ *invalid = 1;
+ }
+ if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1)))
+ || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
+ || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
+ || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0))
+ || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+ *invalid = 1;
+ return 0;
+}
+
/* Called at the end of processing normal insns (eg: add) to insert a shimm
value (if present) into the insn. */
static arc_insn
insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
if (shimm_p)
insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
@@ -829,15 +1281,52 @@ insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_limmfinish (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
+#if 0
if (limm_p)
- ; /* nothing to do, gas does it */
+ ; /* nothing to do, gas does it. */
+#endif
+ return insn;
+}
+
+static arc_insn
+insert_jumpflags (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value;
+ const char **errmsg;
+{
+ if (!flag_p)
+ {
+ *errmsg = "jump flags, but no .f seen";
+ }
+ if (!limm_p)
+ {
+ *errmsg = "jump flags, but no limm addr";
+ }
+ if (limm & 0xfc000000)
+ {
+ *errmsg = "flag bits of jump address limm lost";
+ }
+ if (limm & 0x03000000)
+ {
+ *errmsg = "attempt to set HR bits";
+ }
+ if ((value & ((1 << operand->bits) - 1)) != value)
+ {
+ *errmsg = "bad jump flags value";
+ }
+ jumpflags_p = 1;
+ limm = (limm & ((1 << operand->shift) - 1))
+ | ((value & ((1 << operand->bits) - 1)) << operand->shift);
return insn;
}
@@ -845,12 +1334,12 @@ insert_limmfinish (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_unopmacro (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
return insn;
@@ -860,15 +1349,15 @@ insert_unopmacro (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_reladdr (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value;
+ const char **errmsg;
{
if (value & 3)
- *errmsg = _("branch address not on 4 byte boundary");
+ *errmsg = "branch address not on 4 byte boundary";
insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
@@ -878,23 +1367,42 @@ insert_reladdr (insn, operand, mods, reg, value, errmsg)
Note that this function is only intended to handle instructions (with 4 byte
immediate operands). It is not intended to handle data. */
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
+/* ??? Actually, there's little for us to do as we can't call frag_more, the
caller must do that. The extract fns take a pointer to two words. The
insert fns could be converted and then we could do something useful, but
then the reloc handlers would have to know to work on the second word of
- a 2 word quantity. That's too much so we don't handle them. */
+ a 2 word quantity. That's too much so we don't handle them.
+
+ We do check for correct usage of the nullify suffix, or we
+ set the default correctly, though. */
static arc_insn
insert_absaddr (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg;
{
if (limm_p)
- ; /* nothing to do */
+ {
+ /* if it is a jump and link, .jd must be specified. */
+ if (insn & R(-1,9,1))
+ {
+ if (!nullify_p)
+ {
+ insn |= 0x02 << 5; /* default nullify to .jd. */
+ }
+ else
+ {
+ if(nullify != 0x02)
+ {
+ *errmsg = "must specify .jd or no nullify suffix";
+ }
+ }
+ }
+ }
return insn;
}
@@ -912,10 +1420,7 @@ static const struct arc_operand_value *lookup_register (int type, long regno);
void
arc_opcode_init_extract ()
{
- flag_p = 0;
- flagshimm_handled_p = 0;
- shimm_p = 0;
- limm_p = 0;
+ arc_opcode_init_insert();
}
/* As we're extracting registers, keep an eye out for the 'f' indicator
@@ -927,46 +1432,76 @@ arc_opcode_init_extract ()
static long
extract_reg (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods;
+ const struct arc_operand_value **opval;
+ int *invalid ATTRIBUTE_UNUSED;
{
int regno;
long value;
+ enum operand op_type;
/* Get the register number. */
- regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
/* Is it a constant marker? */
if (regno == ARC_REG_SHIMM)
{
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
- flagshimm_handled_p = 1;
+ op_type = OP_SHIMM;
+ /* always return zero if dest is a shimm mlm. */
+
+ if ('a' != operand->fmt)
+ {
+ value = *insn & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED)
+ && (value & 256))
+ value -= 512;
+ if (!flagshimm_handled_p)
+ flag_p = 0;
+ flagshimm_handled_p = 1;
+ }
+ else
+ {
+ value = 0;
+ }
}
else if (regno == ARC_REG_SHIMM_UPDATE)
{
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
+ op_type = OP_SHIMM;
+
+ /* always return zero if dest is a shimm mlm. */
+
+ if ('a' != operand->fmt)
+ {
+ value = *insn & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+ value -= 512;
+ }
+ else
+ {
+ value = 0;
+ }
flag_p = 1;
flagshimm_handled_p = 1;
}
else if (regno == ARC_REG_LIMM)
{
+ op_type = OP_LIMM;
value = insn[1];
limm_p = 1;
+ /* if this is a jump instruction (j,jl), show new pc correctly. */
+ if(0x07 == ((*insn & I(-1)) >> 27))
+ {
+ value = (value & 0xffffff);
+ }
}
/* It's a register, set OPVAL (that's the only way we distinguish registers
from constants here). */
else
{
const struct arc_operand_value *reg = lookup_register (REG, regno);
+ op_type = OP_REG;
if (reg == NULL)
abort ();
@@ -986,6 +1521,24 @@ extract_reg (insn, operand, mods, opval, invalid)
if (reg != NULL && opval != NULL)
*opval = reg;
}
+ switch(operand->fmt)
+ {
+ case 'a':
+ ls_operand[LS_DEST] = op_type;
+ break;
+ case 's':
+ ls_operand[LS_BASE] = op_type;
+ break;
+ case 'c':
+ if((insn[0]& I(-1)) == I(2))
+ ls_operand[LS_VALUE] = op_type;
+ else
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ case 'o': case 'O':
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ }
return value;
}
@@ -995,11 +1548,11 @@ extract_reg (insn, operand, mods, opval, invalid)
static long
extract_flag (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval;
+ int *invalid ATTRIBUTE_UNUSED;
{
int f;
const struct arc_operand_value *val;
@@ -1007,12 +1560,12 @@ extract_flag (insn, operand, mods, opval, invalid)
if (flagshimm_handled_p)
f = flag_p != 0;
else
- f = (insn[0] & (1 << operand->shift)) != 0;
+ f = (*insn & (1 << operand->shift)) != 0;
/* There is no text for zero values. */
if (f == 0)
return 0;
-
+ flag_p = 1;
val = arc_opcode_lookup_suffix (operand, 1);
if (opval != NULL && val != NULL)
*opval = val;
@@ -1026,11 +1579,11 @@ extract_flag (insn, operand, mods, opval, invalid)
static long
extract_cond (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval;
+ int *invalid ATTRIBUTE_UNUSED;
{
long cond;
const struct arc_operand_value *val;
@@ -1038,7 +1591,7 @@ extract_cond (insn, operand, mods, opval, invalid)
if (flagshimm_handled_p)
return 0;
- cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
val = arc_opcode_lookup_suffix (operand, cond);
/* Ignore NULL values of `val'. Several condition code values are
@@ -1053,42 +1606,109 @@ extract_cond (insn, operand, mods, opval, invalid)
static long
extract_reladdr (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid ATTRIBUTE_UNUSED;
{
long addr;
- addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
if ((operand->flags & ARC_OPERAND_SIGNED)
&& (addr & (1 << (operand->bits - 1))))
addr -= 1 << operand->bits;
-
return addr << 2;
}
+/* extract the flags bits from a j or jl long immediate. */
+static long
+extract_jumpflags(insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+ if (!flag_p || !limm_p)
+ *invalid = 1;
+ return((flag_p && limm_p)
+ ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
+}
+
+/* extract st insn's offset. */
+
+static long
+extract_st_offset (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+ int value = 0;
+
+ if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
+ {
+ value = insn[0] & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+ value -= 512;
+ if(value)
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ }
+ else
+ {
+ *invalid = 1;
+ }
+ return(value);
+}
+
+/* extract ld insn's offset. */
+
+static long
+extract_ld_offset (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods;
+ const struct arc_operand_value **opval;
+ int *invalid;
+{
+ int test = insn[0] & I(-1);
+ int value;
+
+ if (test)
+ {
+ value = insn[0] & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+ value -= 512;
+ if (value)
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ return(value);
+ }
+/* if it isn't in the insn, it's concealed behind reg 'c'. */
+ return extract_reg(insn,
+ &arc_operands[arc_operand_map['c']], mods, opval, invalid);
+}
+
/* The only thing this does is set the `invalid' flag if B != C.
This is needed because the "mov" macro appears before it's real insn "and"
and we don't want the disassembler to confuse them. */
static long
extract_unopmacro (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ arc_insn *insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
{
/* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
printed as "and"s. */
- if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
- != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
+ if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
+ != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
if (invalid != NULL)
*invalid = 1;
-
return 0;
}
@@ -1097,10 +1717,19 @@ extract_unopmacro (insn, operand, mods, opval, invalid)
const struct arc_operand_value *
arc_opcode_lookup_suffix (type, value)
- const struct arc_operand *type;
- int value;
+ const struct arc_operand *type;
+ int value;
{
register const struct arc_operand_value *v,*end;
+ struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+ while (ext_oper)
+ {
+ if (type == &arc_operands[ext_oper->operand.type]
+ && value == ext_oper->operand.value)
+ return (&ext_oper->operand);
+ ext_oper = ext_oper->next;
+ }
/* ??? This is a little slow and can be speeded up. */
@@ -1113,10 +1742,18 @@ arc_opcode_lookup_suffix (type, value)
static const struct arc_operand_value *
lookup_register (type, regno)
- int type;
- long regno;
+ int type;
+ long regno;
{
register const struct arc_operand_value *r,*end;
+ struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+ while (ext_oper)
+ {
+ if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
+ return (&ext_oper->operand);
+ ext_oper = ext_oper->next;
+ }
if (type == REG)
return &arc_reg_names[regno];
@@ -1129,3 +1766,58 @@ lookup_register (type, regno)
return r;
return 0;
}
+
+int
+arc_insn_is_j(insn)
+ arc_insn insn;
+{
+ return (insn & (I(-1))) == I(0x7);
+}
+
+int
+arc_insn_not_jl(insn)
+ arc_insn insn;
+{
+ return (insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) !=
+ (I(0x7) | R(-1,9,1));
+}
+
+int
+arc_operand_type(int opertype)
+{
+ switch (opertype)
+ {
+ case 0:
+ return(COND);
+ break;
+ case 1:
+ return(REG);
+ break;
+ case 2:
+ return(AUXREG);
+ break;
+ }
+ return -1;
+}
+
+struct arc_operand_value *
+get_ext_suffix(s)
+ char *s;
+{
+ struct arc_ext_operand_value *suffix = arc_ext_operands;
+
+ while (suffix)
+ {
+ if ((COND == suffix->operand.type)
+ && !strcmp(s,suffix->operand.name))
+ return(&suffix->operand);
+ suffix = suffix->next;
+ }
+ return(NULL);
+}
+
+int
+arc_get_noshortcut_flag()
+{
+ return(ARC_REGISTER_NOSHORT_CUT);
+}
diff --git a/opcodes/configure b/opcodes/configure
index 08ca1cd..426a70e 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -4516,7 +4516,7 @@ if test x${all_targets} = xfalse ; then
bfd_a29k_arch) ta="$ta a29k-dis.lo" ;;
bfd_alliant_arch) ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
- bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo" ;;
+ bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_convex_arch) ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 7b18cfa..b0d4288 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -170,7 +170,7 @@ if test x${all_targets} = xfalse ; then
bfd_a29k_arch) ta="$ta a29k-dis.lo" ;;
bfd_alliant_arch) ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
- bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo" ;;
+ bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_convex_arch) ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index f4c61f3..9a957c2 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -87,8 +87,7 @@ disassembler (abfd)
#ifdef ARCH_arc
case bfd_arch_arc:
{
- disassemble = arc_get_disassembler (bfd_get_mach (abfd),
- bfd_big_endian (abfd));
+ disassemble = arc_get_disassembler (abfd);
break;
}
#endif
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index 1b24f67..b30cbd5 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -2,6 +2,7 @@ a29k-dis.c
alpha-dis.c
alpha-opc.c
arc-dis.c
+arc-ext.c
arc-opc.c
arm-dis.c
arm-opc.h
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index f286872..3336bbd 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-01-09 12:07-0800\n"
+"POT-Creation-Date: 2001-01-11 12:44-0800\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@@ -22,31 +22,8 @@ msgstr ""
msgid "jump hint unaligned"
msgstr ""
-#. Default text to print if an instruction isn't recognized.
-#: arc-dis.c:232 fr30-dis.c:39 m32r-dis.c:39
-msgid "*unknown*"
-msgstr ""
-
-#: arc-opc.c:629
-msgid "unable to fit different valued constants into instruction"
-msgstr ""
-
-#: arc-opc.c:639
-msgid "auxiliary register not allowed here"
-msgstr ""
-
-#: arc-opc.c:652
-#, c-format
-msgid "invalid register number `%d'"
-msgstr ""
-
-#: arc-opc.c:775
-#, c-format
-msgid "value won't fit in range %ld - %ld"
-msgstr ""
-
-#: arc-opc.c:871
-msgid "branch address not on 4 byte boundary"
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
msgstr ""
#: arm-dis.c:489
@@ -143,6 +120,11 @@ msgstr ""
msgid "bad instruction `%.50s'"
msgstr ""
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:39 m32r-dis.c:39
+msgid "*unknown*"
+msgstr ""
+
#: fr30-dis.c:300 m32r-dis.c:239
#, c-format
msgid "Unrecognized field %d while printing insn.\n"
@@ -204,7 +186,7 @@ msgstr ""
msgid "%02x\t\t*unknown*"
msgstr ""
-#: i386-dis.c:2624
+#: i386-dis.c:2740
msgid "<internal disassembler error>"
msgstr ""
generated by cgit v1.1 at 2024-11-16 02:38:53 +0000