diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/elf/common.h | 5 | ||||
| -rw-r--r-- | include/libiberty.h | 22 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 201 | ||||
| -rw-r--r-- | include/opcode/kvx.h | 4 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 37 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 43 |
6 files changed, 258 insertions, 54 deletions
diff --git a/include/elf/common.h b/include/elf/common.h index fd032d1..01812b4 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -1041,6 +1041,11 @@ #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) #define GNU_PROPERTY_AARCH64_FEATURE_1_GCS (1U << 2) +/* RISC-V specific GNU PROPERTY. */ +#define GNU_PROPERTY_RISCV_FEATURE_1_AND 0xc0000000 +#define GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED (1U << 0) +#define GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS (1U << 1) + /* Values used in GNU .note.ABI-tag notes (NT_GNU_ABI_TAG). */ #define GNU_ABI_TAG_LINUX 0 #define GNU_ABI_TAG_HURD 1 diff --git a/include/libiberty.h b/include/libiberty.h index e39f187..b88eb64 100644 --- a/include/libiberty.h +++ b/include/libiberty.h @@ -133,6 +133,18 @@ extern const char *dos_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIB extern const char *unix_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1); +/* A dirname () that is always compiled in. */ + +extern char *ldirname (const char *) ATTRIBUTE_NONNULL(1); + +/* Same, but assumes DOS semantics regardless of host. */ + +extern char *dos_ldirname (const char *) ATTRIBUTE_NONNULL(1); + +/* Same, but assumes Unix semantics regardless of host. */ + +extern char *unix_ldirname (const char *) ATTRIBUTE_NONNULL(1); + /* A well-defined realpath () that is always compiled in. */ extern char *lrealpath (const char *); @@ -199,6 +211,16 @@ extern int fdmatch (int fd1, int fd2); extern int ffs(int); #endif +#if defined (HAVE_DECL_MKSTEMPS) && !HAVE_DECL_MKSTEMPS +extern int mkstemps(char *, int); +#endif + +/* Make memrchr available on systems that do not have it. */ +#if !defined (__GNU_LIBRARY__ ) && !defined (__linux__) && \ + !defined (HAVE_MEMRCHR) +extern void *memrchr(const void *, int, size_t); +#endif + /* Get the working directory. The result is cached, so don't call chdir() between calls to getpwd(). */ diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dfe3f05..7c1163d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -79,6 +79,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_CRC, /* LSE instructions. */ AARCH64_FEATURE_LSE, + /* LSFE instructions. */ + AARCH64_FEATURE_LSFE, /* PAN instructions. */ AARCH64_FEATURE_PAN, /* LOR instructions. */ @@ -135,8 +137,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_ID_PFR2, /* SSBS mechanism enabled. */ AARCH64_FEATURE_SSBS, + /* Compare and branch instructions. */ + AARCH64_FEATURE_CMPBR, /* Memory Tagging Extension. */ AARCH64_FEATURE_MEMTAG, + /* Outer Cacheable Cache Maintenance Operation. */ + AARCH64_FEATURE_OCCMO, /* Transactional Memory Extension. */ AARCH64_FEATURE_TME, /* XS memory attribute. */ @@ -210,7 +216,7 @@ enum aarch64_feature_bit { /* Instrumentation Extension. */ AARCH64_FEATURE_ITE, /* 128-bit page table descriptor, system registers - and isntructions. */ + and instructions. */ AARCH64_FEATURE_D128, /* Armv8.9-A/Armv9.4-A architecture Debug extension. */ AARCH64_FEATURE_DEBUGv8p9, @@ -230,6 +236,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME2p1, /* SVE2.1 instructions. */ AARCH64_FEATURE_SVE2p1, + /* SVE_F16F32MM instructions. */ + AARCH64_FEATURE_SVE_F16F32MM, + /* F8F32MM instructions. */ + AARCH64_FEATURE_F8F32MM, + /* F8F16MM instructions. */ + AARCH64_FEATURE_F8F16MM, /* RCPC3 instructions. */ AARCH64_FEATURE_RCPC3, /* Enhanced Software Step Extension. */ @@ -264,12 +276,26 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_F8F16, /* Non-widening half-precision FP16 to FP16 arithmetic for SME2. */ AARCH64_FEATURE_SME_F16F16, + /* FEAT_SVE_BFSCALE. */ + AARCH64_FEATURE_SVE_BFSCALE, /* SVE Z-targeting non-widening BFloat16 instructions. */ AARCH64_FEATURE_SVE_B16B16, /* SME non-widening BFloat16 instructions. */ AARCH64_FEATURE_SME_B16B16, + /* Armv9.1-A processors. */ + AARCH64_FEATURE_V9_1A, + /* Armv9.2-A processors. */ + AARCH64_FEATURE_V9_2A, + /* Armv9.3-A processors. */ + AARCH64_FEATURE_V9_3A, + /* Armv9.4-A processors. */ + AARCH64_FEATURE_V9_4A, /* Armv9.5-A processors. */ AARCH64_FEATURE_V9_5A, + /* FPRCVT instructions. */ + AARCH64_FEATURE_FPRCVT, + /* Point of Physical Storage. */ + AARCH64_FEATURE_PoPS, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -281,6 +307,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FP8DOT2_SVE, /* +sme-f16f16 or +sme-f8f16 */ AARCH64_FEATURE_SME_F16F16_F8F16, + /* +sve2 or +sme2 */ + AARCH64_FEATURE_SVE2_SME2, /* +sve2p1 or +sme */ AARCH64_FEATURE_SVE2p1_SME, /* +sve2p1 or +sme2 */ @@ -290,13 +318,49 @@ enum aarch64_feature_bit { AARCH64_NUM_FEATURES }; +typedef uint64_t aarch64_feature_word; +#define AARCH64_BITS_PER_FEATURE_WORD 64 + +#define AA64_REPLICATE(SEP, BODY, ...) \ + BODY (0, __VA_ARGS__) SEP \ + BODY (1, __VA_ARGS__) SEP \ + BODY (2, __VA_ARGS__) + +/* Some useful SEP operators for use with replication. */ +#define REP_COMMA , +#define REP_SEMICOLON ; +#define REP_OR_OR || +#define REP_AND_AND && +#define REP_PLUS + + +/* Not currently needed, but if an empty SEP is required define: + #define REP_NO_SEP + Then use REP_NO_SEP in the SEP field. */ + +/* Used to generate one instance of VAL for each value of ELT (ELT is + not otherwise used). */ +#define AA64_REPVAL(ELT, VAL) VAL + +/* static_assert requires C11 (or C++11) or later. Support older + versions by disabling this check since compilers without this are + pretty uncommon these days. */ +#if ((defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L) \ + || (defined __cplusplus && __cplusplus >= 201103L)) +static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, + AARCH64_BITS_PER_FEATURE_WORD)) + >= AARCH64_NUM_FEATURES, + "Insufficient repetitions in AA64_REPLICATE()"); +#endif + /* These macros take an initial argument X that gives the index into an aarch64_feature_set. The macros then return the bitmask for that array index. */ /* A mask in which feature bit BIT is set and all other bits are clear. */ -#define AARCH64_UINT64_BIT(X, BIT) \ - ((X) == (BIT) / 64 ? 1ULL << (BIT) % 64 : 0) +#define AARCH64_UINT64_BIT(X, BIT) \ + ((X) == (BIT) / AARCH64_BITS_PER_FEATURE_WORD \ + ? 1ULL << (BIT) % AARCH64_BITS_PER_FEATURE_WORD \ + : 0) /* A mask that includes only AARCH64_FEATURE_<NAME>. */ #define AARCH64_FEATBIT(X, NAME) \ @@ -374,10 +438,14 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, F16) \ | AARCH64_FEATBIT (X, SVE) \ | AARCH64_FEATBIT (X, SVE2)) -#define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X) -#define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X) -#define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X) -#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \ +#define AARCH64_ARCH_V9_1A_FEATURES(X) (AARCH64_FEATBIT (X, V9_1A) \ + | AARCH64_ARCH_V8_6A_FEATURES (X)) +#define AARCH64_ARCH_V9_2A_FEATURES(X) (AARCH64_FEATBIT (X, V9_2A) \ + | AARCH64_ARCH_V8_7A_FEATURES (X)) +#define AARCH64_ARCH_V9_3A_FEATURES(X) (AARCH64_FEATBIT (X, V9_3A) \ + | AARCH64_ARCH_V8_8A_FEATURES (X)) +#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_FEATBIT (X, V9_4A) \ + | AARCH64_ARCH_V8_9A_FEATURES (X) \ | AARCH64_FEATBIT (X, SVE2p1)) #define AARCH64_ARCH_V9_5A_FEATURES(X) (AARCH64_FEATBIT (X, V9_5A) \ | AARCH64_FEATBIT (X, CPA) \ @@ -431,60 +499,74 @@ enum aarch64_feature_bit { /* CPU-specific features. */ typedef struct { - uint64_t flags[(AARCH64_NUM_FEATURES + 63) / 64]; + aarch64_feature_word flags[AA64_REPLICATE (REP_PLUS, AA64_REPVAL, 1)]; } aarch64_feature_set; -#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ - ((~(CPU).flags[0] & AARCH64_FEATBIT (0, FEAT)) == 0 \ - && (~(CPU).flags[1] & AARCH64_FEATBIT (1, FEAT)) == 0) +#define AARCH64_CPU_HAS_FEATURE_BODY(ELT, CPU, FEAT) \ + ((~(CPU).flags[ELT] & AARCH64_FEATBIT (ELT, FEAT)) == 0) +#define AARCH64_CPU_HAS_FEATURE(CPU, FEAT) \ + (AA64_REPLICATE (REP_AND_AND, AARCH64_CPU_HAS_FEATURE_BODY, CPU, FEAT)) -#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ - ((~(CPU).flags[0] & (FEAT).flags[0]) == 0 \ - && (~(CPU).flags[1] & (FEAT).flags[1]) == 0) +#define AARCH64_CPU_HAS_ALL_FEATURES_BODY(ELT, CPU, FEAT) \ + ((~(CPU).flags[ELT] & (FEAT).flags[ELT]) == 0) +#define AARCH64_CPU_HAS_ALL_FEATURES(CPU, FEAT) \ + (AA64_REPLICATE (REP_AND_AND, AARCH64_CPU_HAS_ALL_FEATURES_BODY, CPU, FEAT)) +#define AARCH64_CPU_HAS_ANY_FEATURES_BODY(ELT, CPU, FEAT) \ + (((CPU).flags[ELT] & (FEAT).flags[ELT]) != 0) #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ - (((CPU).flags[0] & (FEAT).flags[0]) != 0 \ - || ((CPU).flags[1] & (FEAT).flags[1]) != 0) + (AA64_REPLICATE (REP_OR_OR, AARCH64_CPU_HAS_ANY_FEATURES_BODY, CPU, FEAT)) +#define AARCH64_SET_FEATURE_BODY(ELT, DEST, FEAT) \ + (DEST).flags[ELT] = FEAT (ELT) #define AARCH64_SET_FEATURE(DEST, FEAT) \ - ((DEST).flags[0] = FEAT (0), \ - (DEST).flags[1] = FEAT (1)) + (AA64_REPLICATE (REP_COMMA, AARCH64_SET_FEATURE_BODY, DEST, FEAT)) +#define AARCH64_CLEAR_FEATURE_BODY(ELT, DEST, SRC, FEAT) \ + (DEST).flags[ELT] = ((SRC).flags[ELT] \ + & ~AARCH64_FEATBIT (ELT, FEAT)) #define AARCH64_CLEAR_FEATURE(DEST, SRC, FEAT) \ - ((DEST).flags[0] = (SRC).flags[0] & ~AARCH64_FEATBIT (0, FEAT), \ - (DEST).flags[1] = (SRC).flags[1] & ~AARCH64_FEATBIT (1, FEAT)) - -#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ - do \ - { \ - (TARG).flags[0] = (F1).flags[0] | (F2).flags[0]; \ - (TARG).flags[1] = (F1).flags[1] | (F2).flags[1]; \ - } \ + (AA64_REPLICATE (REP_COMMA, AARCH64_CLEAR_FEATURE_BODY, DEST, SRC, FEAT)) + +#define AARCH64_MERGE_FEATURE_SETS_BODY(ELT, TARG, F1, F2) \ + (TARG).flags[ELT] = (F1).flags[ELT] | (F2).flags[ELT]; +#define AARCH64_MERGE_FEATURE_SETS(TARG, F1, F2) \ + do \ + { \ + AA64_REPLICATE (REP_SEMICOLON, \ + AARCH64_MERGE_FEATURE_SETS_BODY, TARG, F1, F2); \ + } \ while (0) -#define AARCH64_CLEAR_FEATURES(TARG,F1,F2) \ - do \ - { \ - (TARG).flags[0] = (F1).flags[0] &~ (F2).flags[0]; \ - (TARG).flags[1] = (F1).flags[1] &~ (F2).flags[1]; \ - } \ +#define AARCH64_CLEAR_FEATURES_BODY(ELT, TARG, F1, F2) \ + (TARG).flags[ELT] = (F1).flags[ELT] &~ (F2).flags[ELT]; +#define AARCH64_CLEAR_FEATURES(TARG,F1,F2) \ + do \ + { \ + AA64_REPLICATE (REP_SEMICOLON, \ + AARCH64_CLEAR_FEATURES_BODY, TARG, F1, F2); \ + } \ while (0) /* aarch64_feature_set initializers for no features and all features, respectively. */ -#define AARCH64_NO_FEATURES { { 0, 0 } } -#define AARCH64_ALL_FEATURES { { -1, -1 } } +#define AARCH64_NO_FEATURES { { AA64_REPLICATE (REP_COMMA, AA64_REPVAL, 0) } } +#define AARCH64_ALL_FEATURES { { AA64_REPLICATE (REP_COMMA, AA64_REPVAL, -1) } } /* An aarch64_feature_set initializer for a single feature, AARCH64_FEATURE_<FEAT>. */ -#define AARCH64_FEATURE(FEAT) \ - { { AARCH64_FEATBIT (0, FEAT), AARCH64_FEATBIT (1, FEAT) } } +#define AARCH64_FEATURE_BODY(ELT, FEAT) \ + AARCH64_FEATBIT (ELT, FEAT) +#define AARCH64_FEATURE(FEAT) \ + { { AA64_REPLICATE (REP_COMMA, AARCH64_FEATURE_BODY, FEAT) } } /* An aarch64_feature_set initializer for a specific architecture version, including all the features that are enabled by default for that architecture version. */ -#define AARCH64_ARCH_FEATURES(ARCH) \ - { { AARCH64_ARCH_##ARCH (0), AARCH64_ARCH_##ARCH (1) } } +#define AARCH64_ARCH_FEATURES_BODY(ELT, ARCH) \ + AARCH64_ARCH_##ARCH (ELT) +#define AARCH64_ARCH_FEATURES(ARCH) \ + { { AA64_REPLICATE (REP_COMMA, AARCH64_ARCH_FEATURES_BODY, ARCH) } } /* Used by AARCH64_CPU_FEATURES. */ #define AARCH64_OR_FEATURES_1(X, ARCH, F1) \ @@ -508,9 +590,11 @@ typedef struct { /* An aarch64_feature_set initializer for a CPU that implements architecture version ARCH, and additionally provides the N features listed in "...". */ +#define AARCH64_CPU_FEATURES_BODY(ELT, ARCH, N, ...) \ + AARCH64_OR_FEATURES_##N (ELT, ARCH, __VA_ARGS__) #define AARCH64_CPU_FEATURES(ARCH, N, ...) \ - { { AARCH64_OR_FEATURES_##N (0, ARCH, __VA_ARGS__), \ - AARCH64_OR_FEATURES_##N (1, ARCH, __VA_ARGS__) } } + { { AA64_REPLICATE (REP_COMMA, AARCH64_CPU_FEATURES_BODY, \ + ARCH, N, __VA_ARGS__) } } /* An aarch64_feature_set initializer for the N features listed in "...". */ #define AARCH64_FEATURES(N, ...) \ @@ -618,6 +702,8 @@ enum aarch64_opnd AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ AARCH64_OPND_IMM, /* Immediate. */ AARCH64_OPND_IMM_2, /* Immediate. */ + AARCH64_OPND_IMMP1_2, /* Immediate plus 1. */ + AARCH64_OPND_IMMS1_2, /* Immediate minus 1. */ AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ @@ -645,6 +731,7 @@ enum aarch64_opnd AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ + AARCH64_OPND_ADDR_PCREL9, /* 9-bit PC-relative address for e.g. CB<cc>. */ AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ @@ -704,12 +791,16 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ - AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ - AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ + AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>{, <Xm|XZR>}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #1}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #2}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #3}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #4}]. */ + AARCH64_OPND_SVE_ADDR_RM, /* SVE [<Xn|SP>, <Xm|XZR>]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ @@ -824,6 +915,7 @@ enum aarch64_opnd AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ + AARCH64_OPND_SME_Zm_17, /* SVE vector register list in [20:17]. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ @@ -1051,6 +1143,8 @@ enum aarch64_insn_class floatdp3, floatimm, floatsel, + fprcvtfloat2int, + fprcvtint2float, ldst_immpost, ldst_immpre, ldst_imm9, /* immpost or immpre */ @@ -1391,7 +1485,7 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_OPD_PAIR_OPT (1ULL << 32) /* This instruction does not allow the full range of values that the width of fields in the assembler instruction would theoretically - allow. This impacts the constraintts on assembly but yelds no + allow. This impacts the constraints on assembly but yields no impact on disassembly. */ #define F_OPD_NARROW (1ULL << 33) /* For the instruction with size[22:23] field. */ @@ -1421,7 +1515,10 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_DP_TAG_ONLY (1ULL << 37) #define F_SUBCLASS_OTHER (F_SUBCLASS) -/* Next bit is 41. */ + +/* For LSFE instructions with size[30:31] field. */ +#define F_LSFE_SZ (1ULL << 41) +/* Next bit is 42. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1505,7 +1602,7 @@ opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND - | F_OPD_SIZE | F_RCPC3_SIZE)) != 0; + | F_OPD_SIZE | F_RCPC3_SIZE | F_LSFE_SZ )) != 0; } struct aarch64_name_value_pair @@ -1757,7 +1854,7 @@ struct aarch64_inst /* Corresponding opcode entry. */ const aarch64_opcode *opcode; - /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ + /* Condition for a truly conditional-executed instruction, e.g. b.cond. */ const aarch64_cond *cond; /* Operands information. */ @@ -1857,7 +1954,7 @@ struct aarch64_inst yet still accept a wider range of registers. AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and - AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the + AARCH64_OPDE_FATAL_SYNTAX_ERROR are only detected by GAS while the AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as only libopcodes has the information about the valid variants of each instruction. diff --git a/include/opcode/kvx.h b/include/opcode/kvx.h index aa51903..9a3c39c 100644 --- a/include/opcode/kvx.h +++ b/include/opcode/kvx.h @@ -140,13 +140,13 @@ struct kvx_pseudo_relocs struct kvx_reloc *kreloc; }; -typedef struct symbol symbolS; +struct symbol; struct pseudo_func { const char *name; - symbolS *sym; + struct symbol *sym; struct kvx_pseudo_relocs pseudo_relocs; }; diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index fea4948..1c64962 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3804,6 +3804,25 @@ #define MASK_SFVFNRCLIPXUFQF 0xfe00707f #define MATCH_SFVFNRCLIPXFQF 0x8e00505b #define MASK_SFVFNRCLIPXFQF 0xfe00707f +/* MIPS custom instruction. */ +#define MATCH_MIPS_CCMOV 0x600300b +#define MASK_MIPS_CCMOV 0x600707f +#define MATCH_MIPS_LWP 0x0010400b +#define MASK_MIPS_LWP 0x0030707f +#define MATCH_MIPS_LDP 0x0000400b +#define MASK_MIPS_LDP 0x0070707f +#define MATCH_MIPS_SWP 0x0000508b +#define MASK_MIPS_SWP 0x000071ff +#define MATCH_MIPS_SDP 0x0000500b +#define MASK_MIPS_SDP 0x000073ff +#define MATCH_MIPS_EHB 0x00301013 +#define MASK_MIPS_EHB 0xffffffff +#define MATCH_MIPS_IHB 0x00101013 +#define MASK_MIPS_IHB 0xffffffff +#define MATCH_MIPS_PAUSE 0x00501013 +#define MASK_MIPS_PAUSE 0xffffffff +#define MATCH_MIPS_PREF 0x0000000b +#define MASK_MIPS_PREF 0xe000707f /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -3895,6 +3914,7 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -4085,6 +4105,7 @@ #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 #define CSR_HGEIE 0x607 +#define CSR_HEDELEGH 0x612 #define CSR_HTVAL 0x643 #define CSR_HIP 0x644 #define CSR_HVIP 0x645 @@ -4186,6 +4207,8 @@ #define CSR_HVIPRIO2H 0x657 #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 +/* Ssccfg CSR address. */ +#define CSR_SCOUNTINHIBIT 0x120 /* Sscsrind extension */ #define CSR_SIREG2 0x152 #define CSR_SIREG3 0x153 @@ -4945,6 +4968,16 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) /* Zicfilp instructions. */ DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) +/* MIPS custom instructions. */ +DECLARE_INSN(mips_ccmov, MATCH_MIPS_CCMOV, MASK_MIPS_CCMOV) +DECLARE_INSN(mips_lwp, MATCH_MIPS_LWP, MASK_MIPS_LWP) +DECLARE_INSN(mips_ldp, MATCH_MIPS_LDP, MASK_MIPS_LDP) +DECLARE_INSN(mips_swp, MATCH_MIPS_SWP, MASK_MIPS_SWP) +DECLARE_INSN(mips_sdp, MATCH_MIPS_SDP, MASK_MIPS_SDP) +DECLARE_INSN(mips_ehb, MATCH_MIPS_EHB, MASK_MIPS_EHB) +DECLARE_INSN(mips_ihb, MATCH_MIPS_IHB, MASK_MIPS_IHB) +DECLARE_INSN(mips_pause, MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE) +DECLARE_INSN(mips_pref, MATCH_MIPS_PREF, MASK_MIPS_PREF) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ @@ -5033,6 +5066,7 @@ DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_ DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(medelegh, CSR_MEDELEGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) @@ -5224,6 +5258,7 @@ DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRI /* Privileged Hypervisor CSRs. */ DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hedelegh, CSR_HEDELEGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) @@ -5318,6 +5353,8 @@ DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_ DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsieh, CSR_VSIEH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsiph, CSR_VSIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Ssccfg CSR. */ +DECLARE_CSR(scountinhibit, CSR_SCOUNTINHIBIT, CSR_CLASS_SSCCFG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Sscsrind extension */ DECLARE_CSR(sireg2, CSR_SIREG2, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(sireg3, CSR_SIREG3, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d76bcdb..2b146af 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -132,6 +132,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) #define EXTRACT_CV_SIMD_UIMM6(x) \ ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1)) +/* Vendor-specific (MIPS) extract macros. */ +#define EXTRACT_MIPS_LWP_IMM(x) \ + (RV_X(x, 22, 5) << 2) +#define EXTRACT_MIPS_LDP_IMM(x) \ + (RV_X(x, 23, 4) << 3) +#define EXTRACT_MIPS_SWP_IMM(x) \ + ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2)) +#define EXTRACT_MIPS_SDP_IMM(x) \ + ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -200,6 +209,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) #define ENCODE_CV_SIMD_UIMM6(x) \ ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) +/* Vendor-specific (MIPS) encode macros. */ +#define ENCODE_MIPS_LWP_IMM(x) \ + (RV_X(x, 2, 5) << 22) +#define ENCODE_MIPS_LDP_IMM(x) \ + (RV_X(x, 3, 4) << 23) +#define ENCODE_MIPS_SWP_IMM(x) \ + ((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9)) +#define ENCODE_MIPS_SDP_IMM(x) \ + ((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10)) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) @@ -383,8 +401,27 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_XSO1 0x1 #define OP_SH_XSO1 26 +/* MIPS fields. */ +#define OP_MASK_MIPS_IMM9 0x1ff +#define OP_SH_MIPS_IMM9 20 +#define OP_MASK_MIPS_HINT 0x1f +#define OP_SH_MIPS_HINT 7 +#define OP_MASK_MIPS_LWP_OFFSET 0x1f +#define OP_SH_MIPS_LWP_OFFSET 22 +#define OP_MASK_MIPS_LDP_OFFSET 0xf +#define OP_SH_MIPS_LDP_OFFSET 23 +#define OP_MASK_MIPS_SWP_OFFSET9 0x7 +#define OP_SH_MIPS_SWP_OFFSET9 9 +#define OP_MASK_MIPS_SWP_OFFSET25 0x3 +#define OP_SH_MIPS_SWP_OFFSET25 25 +#define OP_MASK_MIPS_SDP_OFFSET10 0x3 +#define OP_SH_MIPS_SDP_OFFSET10 10 +#define OP_MASK_MIPS_SDP_OFFSET25 0x3 +#define OP_SH_MIPS_SDP_OFFSET25 25 + /* ABI names for selected x-registers. */ +#define X_ZERO 0 #define X_RA 1 #define X_SP 2 #define X_GP 3 @@ -526,6 +563,8 @@ enum riscv_insn_class INSN_CLASS_ZCMP, INSN_CLASS_ZCMT, INSN_CLASS_SMCTR_OR_SSCTR, + INSN_CLASS_ZILSD, + INSN_CLASS_ZCLSD, INSN_CLASS_SMRNMI, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, @@ -563,6 +602,10 @@ enum riscv_insn_class INSN_CLASS_XSFVQMACCQOQ, INSN_CLASS_XSFVQMACCDOD, INSN_CLASS_XSFVFNRCLIPXFQF, + INSN_CLASS_XMIPSCBOP, + INSN_CLASS_XMIPSCMOV, + INSN_CLASS_XMIPSEXECTL, + INSN_CLASS_XMIPSLSP, }; /* This structure holds information for a particular instruction. */ |