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-rw-r--r--include/opcode/riscv-opc.h5
-rw-r--r--include/opcode/riscv.h1
2 files changed, 6 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1f56317..fea4948 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2311,6 +2311,9 @@
/* Smctr/Ssctr instruction. */
#define MATCH_SCTRCLR 0x10400073
#define MASK_SCTRCLR 0xffffffff
+/* Smrnmi instruction. */
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -4808,6 +4811,8 @@ DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
/* Smctr/Ssctr instruction. */
DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
+/* Smrnmi instruction */
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1f4bede..d76bcdb 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -526,6 +526,7 @@ enum riscv_insn_class
INSN_CLASS_ZCMP,
INSN_CLASS_ZCMT,
INSN_CLASS_SMCTR_OR_SSCTR,
+ INSN_CLASS_SMRNMI,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,