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-rw-r--r--gdb/features/Makefile1
-rw-r--r--gdb/features/alpha-core.xml136
-rw-r--r--gdb/features/alpha.c111
-rw-r--r--gdb/features/alpha.xml11
4 files changed, 259 insertions, 0 deletions
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 7a8c799..750508a 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -100,6 +100,7 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
# --enable-targets=all GDB. You can override this by passing XMLTOC
# to make on the command line.
XMLTOC = \
+ alpha.xml \
microblaze-with-stack-protect.xml \
microblaze.xml \
mips-dsp-linux.xml \
diff --git a/gdb/features/alpha-core.xml b/gdb/features/alpha-core.xml
new file mode 100644
index 0000000..c9e12f4
--- /dev/null
+++ b/gdb/features/alpha-core.xml
@@ -0,0 +1,136 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2025 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.alpha.core">
+ <!-- IEEE rounding mode values -->
+ <enum id="dyn_rm_enum" size="8">
+ <!-- Chopped rounding mode -->
+ <evalue name="chop" value="0"/>
+ <!-- Minus infinity -->
+ <evalue name="-inf" value="1"/>
+ <!-- Normal rounding -->
+ <evalue name="norm" value="2"/>
+ <!-- Plus infinity -->
+ <evalue name="+inf" value="3"/>
+ </enum>
+
+ <!-- Floating-Point Control Register Flags -->
+ <flags id="fpcr_flags" size="8">
+ <!-- Denormal Operand Exception Disable -->
+ <field name="DNOD" start="47" end="47"/>
+ <!-- Denormal Operands to Zero -->
+ <field name="DNZ" start="48" end="48"/>
+ <!-- Invalid Operation Disable -->
+ <field name="INVD" start="49" end="49"/>
+ <!-- Division by Zero Disable -->
+ <field name="DZED" start="50" end="50"/>
+ <!-- Overflow Disable -->
+ <field name="OVFD" start="51" end="51"/>
+ <!-- Invalid Operation -->
+ <field name="INV" start="52" end="52"/>
+ <!-- Division by Zero -->
+ <field name="DZE" start="53" end="53"/>
+ <!-- Overflow -->
+ <field name="OVF" start="54" end="54"/>
+ <!-- Underflow -->
+ <field name="UNF" start="55" end="55"/>
+ <!-- Inexact Result -->
+ <field name="INE" start="56" end="56"/>
+ <!-- Integer Overflow -->
+ <field name="IOV" start="57" end="57"/>
+ <!-- Dynamic Rounding Mode -->
+ <field name="DYN_RM" start="58" end="59" type="dyn_rm_enum"/>
+ <!-- Underflow to Zero -->
+ <field name="UNDZ" start="60" end="60"/>
+ <!-- Underflow Disable -->
+ <field name="UNFD" start="61" end="61"/>
+ <!-- Inexact Disable -->
+ <field name="INED" start="62" end="62"/>
+ <!-- Summary Bit -->
+ <field name="SUM" start="63" end="63"/>
+ </flags>
+
+ <!-- Integer Registers -->
+ <reg name="v0" bitsize="64" type="int64"/>
+ <reg name="t0" bitsize="64" type="int64"/>
+ <reg name="t1" bitsize="64" type="int64"/>
+ <reg name="t2" bitsize="64" type="int64"/>
+ <reg name="t3" bitsize="64" type="int64"/>
+ <reg name="t4" bitsize="64" type="int64"/>
+ <reg name="t5" bitsize="64" type="int64"/>
+ <reg name="t6" bitsize="64" type="int64"/>
+ <reg name="t7" bitsize="64" type="int64"/>
+ <reg name="s0" bitsize="64" type="int64"/>
+ <reg name="s1" bitsize="64" type="int64"/>
+ <reg name="s2" bitsize="64" type="int64"/>
+ <reg name="s3" bitsize="64" type="int64"/>
+ <reg name="s4" bitsize="64" type="int64"/>
+ <reg name="s5" bitsize="64" type="int64"/>
+ <reg name="fp" bitsize="64" type="int64"/>
+ <reg name="a0" bitsize="64" type="int64"/>
+ <reg name="a1" bitsize="64" type="int64"/>
+ <reg name="a2" bitsize="64" type="int64"/>
+ <reg name="a3" bitsize="64" type="int64"/>
+ <reg name="a4" bitsize="64" type="int64"/>
+ <reg name="a5" bitsize="64" type="int64"/>
+ <reg name="t8" bitsize="64" type="int64"/>
+ <reg name="t9" bitsize="64" type="int64"/>
+ <reg name="t10" bitsize="64" type="int64"/>
+ <reg name="t11" bitsize="64" type="int64"/>
+ <reg name="ra" bitsize="64" type="int64"/>
+ <reg name="t12" bitsize="64" type="int64"/>
+ <reg name="at" bitsize="64" type="int64"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="zero" bitsize="64" type="int64" save-restore="no"/>
+
+ <!-- Floating-Point Registers -->
+ <reg name="f0" bitsize="64" type="float" group="float"/>
+ <reg name="f1" bitsize="64" type="float" group="float"/>
+ <reg name="f2" bitsize="64" type="float" group="float"/>
+ <reg name="f3" bitsize="64" type="float" group="float"/>
+ <reg name="f4" bitsize="64" type="float" group="float"/>
+ <reg name="f5" bitsize="64" type="float" group="float"/>
+ <reg name="f6" bitsize="64" type="float" group="float"/>
+ <reg name="f7" bitsize="64" type="float" group="float"/>
+ <reg name="f8" bitsize="64" type="float" group="float"/>
+ <reg name="f9" bitsize="64" type="float" group="float"/>
+ <reg name="f10" bitsize="64" type="float" group="float"/>
+ <reg name="f11" bitsize="64" type="float" group="float"/>
+ <reg name="f12" bitsize="64" type="float" group="float"/>
+ <reg name="f13" bitsize="64" type="float" group="float"/>
+ <reg name="f14" bitsize="64" type="float" group="float"/>
+ <reg name="f15" bitsize="64" type="float" group="float"/>
+ <reg name="f16" bitsize="64" type="float" group="float"/>
+ <reg name="f17" bitsize="64" type="float" group="float"/>
+ <reg name="f18" bitsize="64" type="float" group="float"/>
+ <reg name="f19" bitsize="64" type="float" group="float"/>
+ <reg name="f20" bitsize="64" type="float" group="float"/>
+ <reg name="f21" bitsize="64" type="float" group="float"/>
+ <reg name="f22" bitsize="64" type="float" group="float"/>
+ <reg name="f23" bitsize="64" type="float" group="float"/>
+ <reg name="f24" bitsize="64" type="float" group="float"/>
+ <reg name="f25" bitsize="64" type="float" group="float"/>
+ <reg name="f26" bitsize="64" type="float" group="float"/>
+ <reg name="f27" bitsize="64" type="float" group="float"/>
+ <reg name="f28" bitsize="64" type="float" group="float"/>
+ <reg name="f29" bitsize="64" type="float" group="float"/>
+ <reg name="f30" bitsize="64" type="float" group="float"/>
+
+ <!-- Floating-Point Control Register -->
+ <reg name="fpcr" bitsize="64" type="fpcr_flags" group="float"/>
+
+ <!-- Program Counter -->
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+
+ <!-- Reserved Index for Former Virtual Register -->
+ <reg name="" bitsize="64" type="int64" save-restore="no"/>
+
+ <!-- PALcode Memory Slot -->
+ <reg name="unique" bitsize="64" type="int64" group="system"/>
+</feature>
diff --git a/gdb/features/alpha.c b/gdb/features/alpha.c
new file mode 100644
index 0000000..35f12fc
--- /dev/null
+++ b/gdb/features/alpha.c
@@ -0,0 +1,111 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: alpha.xml */
+
+#include "osabi.h"
+#include "target-descriptions.h"
+
+const struct target_desc *tdesc_alpha;
+static void
+initialize_tdesc_alpha (void)
+{
+ target_desc_up result = allocate_target_description ();
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result.get (), "org.gnu.gdb.alpha.core");
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_enum (feature, "dyn_rm_enum", 8);
+ tdesc_add_enum_value (type_with_fields, 0, "chop");
+ tdesc_add_enum_value (type_with_fields, 1, "-inf");
+ tdesc_add_enum_value (type_with_fields, 2, "norm");
+ tdesc_add_enum_value (type_with_fields, 3, "+inf");
+
+ type_with_fields = tdesc_create_flags (feature, "fpcr_flags", 8);
+ tdesc_add_flag (type_with_fields, 47, "DNOD");
+ tdesc_add_flag (type_with_fields, 48, "DNZ");
+ tdesc_add_flag (type_with_fields, 49, "INVD");
+ tdesc_add_flag (type_with_fields, 50, "DZED");
+ tdesc_add_flag (type_with_fields, 51, "OVFD");
+ tdesc_add_flag (type_with_fields, 52, "INV");
+ tdesc_add_flag (type_with_fields, 53, "DZE");
+ tdesc_add_flag (type_with_fields, 54, "OVF");
+ tdesc_add_flag (type_with_fields, 55, "UNF");
+ tdesc_add_flag (type_with_fields, 56, "INE");
+ tdesc_add_flag (type_with_fields, 57, "IOV");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "dyn_rm_enum");
+ tdesc_add_typed_bitfield (type_with_fields, "DYN_RM", 58, 59, field_type);
+ tdesc_add_flag (type_with_fields, 60, "UNDZ");
+ tdesc_add_flag (type_with_fields, 61, "UNFD");
+ tdesc_add_flag (type_with_fields, 62, "INED");
+ tdesc_add_flag (type_with_fields, 63, "SUM");
+
+ tdesc_create_reg (feature, "v0", 0, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t0", 1, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t1", 2, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t2", 3, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t3", 4, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t4", 5, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t5", 6, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t6", 7, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t7", 8, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "s0", 9, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "s1", 10, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "s2", 11, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "s3", 12, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "s4", 13, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "s5", 14, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "fp", 15, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "a0", 16, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "a1", 17, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "a2", 18, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "a3", 19, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "a4", 20, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "a5", 21, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t8", 22, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t9", 23, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t10", 24, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t11", 25, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "ra", 26, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "t12", 27, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "at", 28, 1, NULL, 64, "int64");
+ tdesc_create_reg (feature, "gp", 29, 1, NULL, 64, "data_ptr");
+ tdesc_create_reg (feature, "sp", 30, 1, NULL, 64, "data_ptr");
+ tdesc_create_reg (feature, "zero", 31, 0, NULL, 64, "int64");
+ tdesc_create_reg (feature, "f0", 32, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f1", 33, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f2", 34, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f3", 35, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f4", 36, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f5", 37, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f6", 38, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f7", 39, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f8", 40, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f9", 41, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f10", 42, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f11", 43, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f12", 44, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f13", 45, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f14", 46, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f15", 47, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f16", 48, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f17", 49, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f18", 50, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f19", 51, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f20", 52, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f21", 53, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f22", 54, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f23", 55, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f24", 56, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f25", 57, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f26", 58, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f27", 59, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f28", 60, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f29", 61, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "f30", 62, 1, "float", 64, "float");
+ tdesc_create_reg (feature, "fpcr", 63, 1, "float", 64, "fpcr_flags");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "", 65, 0, NULL, 64, "int64");
+ tdesc_create_reg (feature, "unique", 66, 1, "system", 64, "int64");
+
+ tdesc_alpha = result.release ();
+}
diff --git a/gdb/features/alpha.xml b/gdb/features/alpha.xml
new file mode 100644
index 0000000..3ae0ab8
--- /dev/null
+++ b/gdb/features/alpha.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2025 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<target version="1.0">
+ <xi:include href="alpha-core.xml"/>
+</target>
generated by cgit v1.1 at 2025-07-04 21:01:47 +0000