diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 13 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sve2-aes.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sve2.l | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sve2.s | 10 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve2.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve2.s | 4 |
7 files changed, 43 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 8bf427e..8209cd0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,16 @@ +2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> + + * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. + * testsuite/gas/aarch64/illegal-sve2.l: Update tests. + * doc/c-aarch64.texi: Add special note of pmull{t,b} + instructions under the sve2-aes architecture extension. + * testsuite/gas/aarch64/illegal-sve2.s: Add small size + pmull{t,b} instructions. + * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} + disassembly. + * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} + instructions. + 2019-07-01 Nick Clifton <nickc@redhat.com> PR 24738 diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index e663061..6844f59 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -203,7 +203,8 @@ automatically cause those extensions to be disabled. @item @code{sve2-sm4} @tab ARMv8-A @tab No @tab Enable SVE2 SM4 Extension. @item @code{sve2-aes} @tab ARMv8-A @tab No - @tab Enable SVE2 AES Extension. + @tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the + @code{pmullt} and @code{pmullb} instructions. @item @code{sve2-sha3} @tab ARMv8-A @tab No @tab Enable SVE2 SHA3 Extension. @end multitable diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-aes.d b/gas/testsuite/gas/aarch64/illegal-sve2-aes.d index 8e6daa2..926db22 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2-aes.d +++ b/gas/testsuite/gas/aarch64/illegal-sve2-aes.d @@ -12,9 +12,5 @@ #error: [^ :]+:[0-9]+: Error: selected processor does not support `aesmc z0\.b,z0\.b' #error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z17\.q,z21\.d,z27\.d' #error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.q,z0\.d,z0\.d' -#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.h,z0\.b,z0\.b' -#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.d,z0\.s,z0\.s' #error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z17\.q,z21\.d,z27\.d' #error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.q,z0\.d,z0\.d' -#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.h,z0\.b,z0\.b' -#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.d,z0\.s,z0\.s' diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 7d93a09..01c6847 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -756,18 +756,24 @@ [^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.d,z0\.d,z0\.d' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d -[^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: pmullb z0\.h, z0\.b, z0\.b -[^ :]+:[0-9]+: Info: pmullb z0\.d, z0\.s, z0\.s +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.h,z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.h,z32\.b,z0\.b' +[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.h,z0\.b,z32\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.b,z0\.b,z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.q,z0\.d,z0\.d' [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.q,z32\.d,z0\.d' [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.q,z0\.d,z32\.d' [^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.d,z0\.d,z0\.d' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d -[^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: pmullt z0\.h, z0\.b, z0\.b -[^ :]+:[0-9]+: Info: pmullt z0\.d, z0\.s, z0\.s +[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.h,z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.h,z32\.b,z0\.b' +[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.h,z0\.b,z32\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.b,z0\.b,z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d [^ :]+:[0-9]+: Error: operand mismatch -- `raddhnb z0\.h,z0\.h,z0\.h' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: raddhnb z0\.b, z0\.h, z0\.h diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s index c6c408c..c963a5c 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.s +++ b/gas/testsuite/gas/aarch64/illegal-sve2.s @@ -519,11 +519,21 @@ pmullb z0.q, z32.d, z0.d pmullb z0.q, z0.d, z32.d pmullb z0.d, z0.d, z0.d +pmullb z32.h, z0.b, z0.b +pmullb z0.h, z32.b, z0.b +pmullb z0.h, z0.b, z32.b +pmullb z0.b, z0.b, z0.b + pmullt z32.q, z0.d, z0.d pmullt z0.q, z32.d, z0.d pmullt z0.q, z0.d, z32.d pmullt z0.d, z0.d, z0.d +pmullt z32.h, z0.b, z0.b +pmullt z0.h, z32.b, z0.b +pmullt z0.h, z0.b, z32.b +pmullt z0.b, z0.b, z0.b + raddhnb z0.h, z0.h, z0.h raddhnb z32.b, z0.h, z0.h raddhnb z0.b, z32.h, z0.h diff --git a/gas/testsuite/gas/aarch64/sve2.d b/gas/testsuite/gas/aarch64/sve2.d index efa9b27..5324583 100644 --- a/gas/testsuite/gas/aarch64/sve2.d +++ b/gas/testsuite/gas/aarch64/sve2.d @@ -264,10 +264,12 @@ Disassembly of section \.text: *[0-9a-f]+: 04206400 pmul z0\.b, z0\.b, z0\.b *[0-9a-f]+: 451b6ab1 pmullb z17\.q, z21\.d, z27\.d *[0-9a-f]+: 45006800 pmullb z0\.q, z0\.d, z0\.d + *[0-9a-f]+: 455b6ab1 pmullb z17\.h, z21\.b, z27\.b *[0-9a-f]+: 45406800 pmullb z0\.h, z0\.b, z0\.b *[0-9a-f]+: 45c06800 pmullb z0\.d, z0\.s, z0\.s *[0-9a-f]+: 451b6eb1 pmullt z17\.q, z21\.d, z27\.d *[0-9a-f]+: 45006c00 pmullt z0\.q, z0\.d, z0\.d + *[0-9a-f]+: 455b6eb1 pmullt z17\.h, z21\.b, z27\.b *[0-9a-f]+: 45406c00 pmullt z0\.h, z0\.b, z0\.b *[0-9a-f]+: 45c06c00 pmullt z0\.d, z0\.s, z0\.s *[0-9a-f]+: 457b6ab1 raddhnb z17\.b, z21\.h, z27\.h diff --git a/gas/testsuite/gas/aarch64/sve2.s b/gas/testsuite/gas/aarch64/sve2.s index 13d2e2a..9417a0d 100644 --- a/gas/testsuite/gas/aarch64/sve2.s +++ b/gas/testsuite/gas/aarch64/sve2.s @@ -338,11 +338,15 @@ pmul z0.b, z0.b, z0.b pmullb z17.q, z21.d, z27.d pmullb z0.q, z0.d, z0.d + +pmullb z17.h, z21.b, z27.b pmullb z0.h, z0.b, z0.b pmullb z0.d, z0.s, z0.s pmullt z17.q, z21.d, z27.d pmullt z0.q, z0.d, z0.d + +pmullt z17.h, z21.b, z27.b pmullt z0.h, z0.b, z0.b pmullt z0.d, z0.s, z0.s |