4 files changed, 20 insertions, 1 deletions
diff --git a/gas/NEWS b/gas/NEWS
index ff0a25d..8ddd38a 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -26,7 +26,7 @@
   for --enable-compressed-debug-sections.
 
 * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs,
-  XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx,
+  XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadInt, XTheadMemIdx,
   XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head
   ISA manual, which are implemented in the Allwinner D1.
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index f2a69d8..d61e8e47 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -739,6 +739,11 @@ The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precisi
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
 
+@item XTheadInt
+The XTheadInt extension provides access to ISR stack management instructions.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
+
 @item XTheadMac
 The XTheadMac extension provides multiply-accumulate instructions.
 
diff --git a/gas/testsuite/gas/riscv/x-thead-int.d b/gas/testsuite/gas/riscv/x-thead-int.d
new file mode 100644
index 0000000..23a82a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-int.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_xtheadint
+#source: x-thead-int.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0040000b[ 	]+th.ipush
+[ 	]+[0-9a-f]+:[ 	]+0050000b[ 	]+th.ipop
diff --git a/gas/testsuite/gas/riscv/x-thead-int.s b/gas/testsuite/gas/riscv/x-thead-int.s
new file mode 100644
index 0000000..23d8674
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-int.s
@@ -0,0 +1,3 @@
+target:
+	th.ipush
+	th.ipop