diff options
Diffstat (limited to 'gas')
40 files changed, 748 insertions, 121 deletions
@@ -1,5 +1,7 @@ -*- text -*- +* Add support for AMD Zen6 processor. + * Emit an SFrame FRE with zero offsets to convey an undefined return address in the SFrame stack trace format. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index eb282bf..54c6678 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1049,6 +1049,12 @@ const relax_typeS md_relax_table[] = { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \ CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS } +#define CPU_ANY_APX_NCI_NDD_NF_FLAGS \ + { .bitfield = \ + { .cpuapx_nci = true, \ + .cpuapx_ndd = true, \ + .cpuapx_nf = true } } + static const arch_entry cpu_arch[] = { /* Do not replace the first two entries - i386_target_format() and @@ -1091,6 +1097,7 @@ static const arch_entry cpu_arch[] = ARCH (znver3, ZNVER, ZNVER3, false), ARCH (znver4, ZNVER, ZNVER4, false), ARCH (znver5, ZNVER, ZNVER5, false), + ARCH (znver6, ZNVER, ZNVER6, false), ARCH (btver1, BT, BTVER1, false), ARCH (btver2, BT, BTVER2, false), @@ -1208,6 +1215,7 @@ static const arch_entry cpu_arch[] = VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset), VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, ANY_AVX512_VP2INTERSECT, reset), + VECARCH (avx512_bmm, AVX512_BMM, ANY_AVX512_BMM, reset), SUBARCH (tdx, TDX, TDX, false), SUBARCH (enqcmd, ENQCMD, ENQCMD, false), SUBARCH (serialize, SERIALIZE, SERIALIZE, false), @@ -1239,7 +1247,11 @@ static const arch_entry cpu_arch[] = SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), SUBARCH (user_msr, USER_MSR, USER_MSR, false), - SUBARCH (apx_f, APX_F, APX_F, false), + SUBARCH (apx_f, APX_F, ANY_APX_F, false), + SUBARCH (apx_nci, APX_NCI, ANY_APX_NCI, false), + SUBARCH (apx_ndd, APX_NDD, ANY_APX_NDD, false), + SUBARCH (apx_nf, APX_NF, ANY_APX_NF, false), + SUBARCH (apx_nci_ndd_nf, APX_NCI_NDD_NF, ANY_APX_NCI_NDD_NF, false), VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set), SUBARCH (gmism2, GMISM2, GMISM2, false), SUBARCH (gmiccs, GMICCS, GMICCS, false), @@ -1383,10 +1395,10 @@ gotrel[] = { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false }, #endif { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, - BFD_RELOC_X86_64_PLTOFF64 }, + BFD_RELOC_64_PLTOFF }, { .bitfield = { .imm64 = 1 } }, true }, { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, - BFD_RELOC_X86_64_PLT32 }, + BFD_RELOC_32_PLT_PCREL }, OPERAND_TYPE_IMM32_32S_DISP32, false }, { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, BFD_RELOC_X86_64_GOTPLT64 }, @@ -1943,6 +1955,10 @@ cpu_flags_all_zero (const union i386_cpu_flags *x) { switch (ARRAY_SIZE(x->array)) { + case 6: + if (x->array[5]) + return 0; + /* Fall through. */ case 5: if (x->array[4]) return 0; @@ -1972,6 +1988,10 @@ cpu_flags_equal (const union i386_cpu_flags *x, { switch (ARRAY_SIZE(x->array)) { + case 6: + if (x->array[5] != y->array[5]) + return 0; + /* Fall through. */ case 5: if (x->array[4] != y->array[4]) return 0; @@ -2009,6 +2029,9 @@ cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 6: + x.array [5] &= y.array [5]; + /* Fall through. */ case 5: x.array [4] &= y.array [4]; /* Fall through. */ @@ -2035,6 +2058,9 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 6: + x.array [5] |= y.array [5]; + /* Fall through. */ case 5: x.array [4] |= y.array [4]; /* Fall through. */ @@ -2061,6 +2087,9 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 6: + x.array [5] &= ~y.array [5]; + /* Fall through. */ case 5: x.array [4] &= ~y.array [4]; /* Fall through. */ @@ -2329,6 +2358,17 @@ cpu_flags_match (const insn_template *t) memset (&any, 0, sizeof (any)); } } + else if (t->opcode_modifier.evex + /* Implicitly !t->opcode_modifier.vex. */ + && all.bitfield.cpuapx_f + && (t->opcode_modifier.nf + || (all.bitfield.cpuadx && t->opcode_modifier.vexvvvv))) + { + /* APX_NDD can't be combined with other ISAs in the opcode table. + Respective entries (ADCX, ADOX, LZCNT, POPCNT, and TZCNT) use APX_F + instead, which are amended here. No need to clear cpuapx_f, though. */ + all.bitfield.cpuapx_ndd = true; + } if (flag_code != CODE_64BIT) active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags); @@ -2669,11 +2709,11 @@ operand_size_match (const insn_template *t) { unsigned int given = i.operands - j - 1; - /* For FMA4 and XOP insns VEX.W controls just the first two - register operands. And APX_F insns just swap the two source operands, + /* For FMA4 and XOP insns VEX.W controls just the first two register + operands. And APX_F / APX_NDD insns just swap the two source operands, with the 3rd one being the destination. */ if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP) - || is_cpu (t, CpuAPX_F)) + || is_cpu (t, CpuAPX_F)|| is_cpu (t, CpuAPX_NDD)) given = j < 2 ? 1 - j : j; if (i.types[given].bitfield.class == Reg @@ -3925,15 +3965,11 @@ _reloc (unsigned int size, if (size == 8) switch (other) { + case BFD_RELOC_64_PLTOFF: + case BFD_RELOC_X86_64_GOTPLT64: + return other; case BFD_RELOC_X86_64_GOT32: return BFD_RELOC_X86_64_GOT64; - break; - case BFD_RELOC_X86_64_GOTPLT64: - return BFD_RELOC_X86_64_GOTPLT64; - break; - case BFD_RELOC_X86_64_PLTOFF64: - return BFD_RELOC_X86_64_PLTOFF64; - break; case BFD_RELOC_X86_64_GOTPC32: other = BFD_RELOC_X86_64_GOTPC64; break; @@ -4104,7 +4140,7 @@ tc_i386_fix_adjustable (fixS *fixP) /* Resolve PLT32 relocation against local symbol to section only for PC-relative relocations. */ if (fixP->fx_r_type == BFD_RELOC_386_PLT32 - || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32) + || fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL) return fixP->fx_pcrel; return 1; } @@ -9597,12 +9633,13 @@ match_template (char mnem_suffix) /* Try reversing direction of operands. */ j = is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP) - || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1; + || is_cpu (t, CpuAPX_F) + || is_cpu (t, CpuAPX_NDD) ? 1 : i.operands - 1; overlap0 = operand_type_and (i.types[0], operand_types[j]); overlap1 = operand_type_and (i.types[j], operand_types[0]); overlap2 = operand_type_and (i.types[1], operand_types[1]); gas_assert (t->operands != 3 || !check_register - || is_cpu (t, CpuAPX_F)); + || is_cpu (t, CpuAPX_F) || is_cpu (t, CpuAPX_NDD)); if (!operand_type_match (overlap0, i.types[0]) || !operand_type_match (overlap1, i.types[j]) || (t->operands == 3 @@ -11743,7 +11780,7 @@ output_jump (void) if (flag_code == CODE_64BIT && size == 4 && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 && need_plt32_p (i.op[0].disps->X_add_symbol)) - jump_reloc = BFD_RELOC_X86_64_PLT32; + jump_reloc = BFD_RELOC_32_PLT_PCREL; #endif jump_reloc = reloc (size, 1, 1, jump_reloc); @@ -13389,7 +13426,7 @@ x86_cons (expressionS *exp, int size) *input_line_pointer = c; } else if ((got_reloc == BFD_RELOC_386_PLT32 - || got_reloc == BFD_RELOC_X86_64_PLT32) + || got_reloc == BFD_RELOC_32_PLT_PCREL) && exp->X_op != O_symbol) { char c = *input_line_pointer; @@ -15733,7 +15770,7 @@ elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) switch ((enum bfd_reloc_code_real) fr_var) { case BFD_RELOC_386_PLT32: - case BFD_RELOC_X86_64_PLT32: + case BFD_RELOC_32_PLT_PCREL: /* Symbol with PLT relocation may be preempted. */ return 0; default: @@ -16194,7 +16231,7 @@ md_estimate_size_before_relax (fragS *fragP, segT segment) && fragP->tc_frag_data.code == CODE_64BIT && fragP->fr_offset == 0 && need_plt32_p (fragP->fr_symbol)) - reloc_type = BFD_RELOC_X86_64_PLT32; + reloc_type = BFD_RELOC_32_PLT_PCREL; #endif old_fr_fix = fragP->fr_fix; @@ -16598,7 +16635,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) switch (fixP->fx_r_type) { case BFD_RELOC_386_PLT32: - case BFD_RELOC_X86_64_PLT32: + case BFD_RELOC_32_PLT_PCREL: /* Make the jump instruction point to the address of the operand. At runtime we merely add the offset to the actual PLT entry. NB: Subtract the offset size only for jump instructions. */ @@ -18315,7 +18352,7 @@ i386_validate_fix (fixS *fixp) if (fixp->fx_addsy && fixp->fx_pcrel && (fixp->fx_r_type == BFD_RELOC_386_PLT32 - || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) + || fixp->fx_r_type == BFD_RELOC_32_PLT_PCREL) && symbol_section_p (fixp->fx_addsy)) fixp->fx_r_type = BFD_RELOC_32_PCREL; if (!object_64bit) @@ -18391,7 +18428,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) #endif /* Fall through. */ - case BFD_RELOC_X86_64_PLT32: + case BFD_RELOC_32_PLT_PCREL: case BFD_RELOC_X86_64_GOT32: case BFD_RELOC_X86_64_GOTPCREL: case BFD_RELOC_X86_64_GOTPCRELX: @@ -18430,7 +18467,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) case BFD_RELOC_X86_64_GOTPCREL64: case BFD_RELOC_X86_64_GOTPC64: case BFD_RELOC_X86_64_GOTPLT64: - case BFD_RELOC_X86_64_PLTOFF64: + case BFD_RELOC_64_PLTOFF: case BFD_RELOC_X86_64_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC: @@ -18544,7 +18581,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) case BFD_RELOC_X86_64_GOTPCREL64: case BFD_RELOC_X86_64_GOTPC64: case BFD_RELOC_X86_64_GOTPLT64: - case BFD_RELOC_X86_64_PLTOFF64: + case BFD_RELOC_64_PLTOFF: as_bad_where (fixp->fx_file, fixp->fx_line, _("cannot represent relocation type %s in x32 mode"), bfd_get_reloc_code_name (code)); @@ -18558,7 +18595,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) else switch (code) { - case BFD_RELOC_X86_64_PLT32: + case BFD_RELOC_32_PLT_PCREL: case BFD_RELOC_X86_64_GOT32: case BFD_RELOC_X86_64_GOTPCREL: case BFD_RELOC_X86_64_GOTPCRELX: diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index b006c6e..df5cf9d 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -1096,9 +1096,11 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) ip->reloc_info[ip->reloc_num].value = const_0; ip->reloc_num++; } - /* check all atomic memory insns */ + /* check all atomic memory insns except amswap.w. + amswap.w $rd,$r1,$rj ($rd==$rj) is used for ud ui5. */ else if (ip->insn->mask == LARCH_MK_ATOMIC_MEM - && LARCH_INSN_ATOMIC_MEM (ip->insn_bin)) + && LARCH_INSN_ATOMIC_MEM (ip->insn_bin) + && !LARCH_INSN_AMSWAP_W (ip->insn_bin)) { /* For AMO insn amswap.[wd], amadd.[wd], etc. */ if (ip->args[0] != 0 diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b03ac64..834e864 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -126,6 +126,7 @@ processor names are recognized: @code{znver3}, @code{znver4}, @code{znver5}, +@code{znver6}, @code{btver1}, @code{btver2}, @code{generic32} and @@ -198,6 +199,7 @@ accept various extension mnemonics. For example, @code{avx512_bf16}, @code{avx_vnni}, @code{avx512_fp16}, +@code{avx512_bmm}, @code{prefetchi}, @code{avx_ifma}, @code{avx_vnni_int8}, @@ -220,6 +222,10 @@ accept various extension mnemonics. For example, @code{user_msr}, @code{msr_imm}, @code{apx_f}, +@code{apx_nci}, +@code{apx_ndd}, +@code{apx_nf}, +@code{apx_nci_ndd_nf}, @code{avx10.2}, @code{avx10.2/512}, @code{avx10.2/256}, @@ -1691,9 +1697,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3} -@item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2} -@item @samp{generic32} -@item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} +@item @samp{znver4} @tab @samp{znver5} @tab @samp{znver6} @tab @samp{btver1} +@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} +@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} @@ -1710,9 +1716,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} -@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{.avx10.1} -@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} -@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} +@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{avx512_bmm} +@item @samp{.avx10.1} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} +@item @samp{.ibt} @tab @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} @@ -1732,6 +1738,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} @item @samp{.tlbsync} @tab @samp{.rmpquery} @tab @samp{.rmpread} @tab @samp{.apx_f} +@item @samp{.apx_nci} @tab @samp{.apx_ndd} @tab @samp{.apx_nf} @tab @samp{.apx_nci_ndd_nf} @item @samp{.gmism2} @tab @samp{.gmiccs} @tab @samp{.padlockrng2} @tab @samp{.padlockphe2} @item @samp{.padlockxmodx} @@ -858,16 +858,24 @@ do_align (unsigned int n, char *fill, unsigned int len, unsigned int max) } /* Find first <eol><next_char>NO_APP<eol>, if any, in the supplied buffer. - Return NULL if there's none, or else the position of <next_char>. */ + Return NULL if there's none, or else the position of <next_char>. + + Note: the S parameter to this function is typed as CHAR* rather than + CONST CHAR* because if it is const then the strstr() function will return + a const pointer, which in turn means that the END local would need to be + const, which would mean that the function itself would have to return a + const pointer, which means that input_line_pointer would have to become + const, which would break lots of things. (See PR 33696). */ + static char * -find_no_app (const char *s, char next_char) +find_no_app (char *s, char next_char) { const char *start = s; const char srch[] = { next_char, 'N', 'O', '_', 'A', 'P', 'P', '\0' }; for (;;) { - char *ends = strstr (s, srch); + char * ends = strstr (s, srch); if (ends == NULL) break; diff --git a/gas/testsuite/gas/i386/apx-nci-ndd-nf.l b/gas/testsuite/gas/i386/apx-nci-ndd-nf.l new file mode 100644 index 0000000..e07ddc2 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-nci-ndd-nf.l @@ -0,0 +1,203 @@ +.* Assembler messages: +.*:14: Error: no EVEX encoding for `add' +.*:15: Error: .* `add' +.*:16: Error: `{nf}' is not supported on `generic64\..*\.apx_f' +.*:18: Error: .* `adox' +.*:20: Error: `{nf}' is not supported on `generic64\..*\.apx_f' +.*:21: Error: `ccmpz' is not supported on `generic64\..*\.apx_f' +.*:22: Error: `cfcmovz' is not supported on `generic64\..*\.apx_f' +.*:23: Error: `cfcmovz' is not supported on `generic64\..*\.apx_f' +.*:24: Error: `cfcmovz' is not supported on `generic64\..*\.apx_f' +.*:25: Error: .* `cmovz' +.*:26: Error: no EVEX encoding for `cmp' +.*:27: Error: no EVEX encoding for `lzcnt' +.*:28: Error: `{nf}' is not supported on `generic64\..*\.apx_f' +.*:29: Error: no EVEX encoding for `tzcnt' +# NCI +.*:14: Error: no EVEX encoding for `add' +.*:15: Error: .* `add' +.*:16: Error: `{nf}' is not supported on `generic64\..*\.apx_nci' +.*:18: Error: .* `adox' +.*:20: Error: `{nf}' is not supported on `generic64\..*\.apx_nci' +.*:27: Error: no EVEX encoding for `lzcnt' +.*:28: Error: `{nf}' is not supported on `generic64\..*\.apx_nci' +.*:29: Error: no EVEX encoding for `tzcnt' +# NDD +.*:16: Error: `{nf}' is not supported on `generic64\..*\.apx_ndd' +.*:20: Error: `{nf}' is not supported on `generic64\..*\.apx_ndd' +.*:21: Error: `ccmpz' is not supported on `generic64\..*\.apx_ndd' +.*:22: Error: `cfcmovz' is not supported on `generic64\..*\.apx_ndd' +.*:23: Error: `cfcmovz' is not supported on `generic64\..*\.apx_ndd' +.*:24: Error: `cfcmovz' is not supported on `generic64\..*\.apx_ndd' +.*:25: Error: .* `cmovz' +.*:26: Error: no EVEX encoding for `cmp' +.*:28: Error: `{nf}' is not supported on `generic64\..*\.apx_ndd' +# NF +.*:14: Error: no EVEX encoding for `add' +.*:15: Error: .* `add' +.*:16: Error: .* `add' +.*:18: Error: .* `adox' +.*:21: Error: `ccmpz' is not supported on `generic64\..*\.apx_nf' +.*:22: Error: `cfcmovz' is not supported on `generic64\..*\.apx_nf' +.*:23: Error: `cfcmovz' is not supported on `generic64\..*\.apx_nf' +.*:24: Error: `cfcmovz' is not supported on `generic64\..*\.apx_nf' +.*:25: Error: .* `cmovz' +.*:26: Error: no EVEX encoding for `cmp' +.*:27: Error: no EVEX encoding for `lzcnt' +.*:28: Error: .* `popcnt' +.*:29: Error: no EVEX encoding for `tzcnt' +#... +[ ]*[0-9]+[ ]+\.irp feat, .* +#... +[ ]*[0-9]+[ ]+\.endr +#... +[ ]*[0-9]+[ ]+> apx_f: +#... +[ ]*[0-9]+[ ]+> +\.arch \.apx_f +[ ]*[0-9]+[ ]+> * +[ ]*[0-9]+[ ]+> +\{evex\} add %r16,%r17 +[ ]*[0-9]+[ ]+> +add %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +\{nf\} add %r16,%r17 +[ ]*[0-9]+[ ]+\?+ 62ECFE08[ ]+> +adox %r16,%r17 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+> +adox %r16,%r17,%r18 +[ ]*[0-9]+[ ]+\?+ 62EAF400[ ]+> +andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+> +\{nf\} andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +ccmpz %r16,%r17 +[ ]*[0-9]+[ ]+> +\{load\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+> +\{store\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+> +cfcmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +cmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +\{evex\} cmp %r16,%r17 +[ ]*[0-9]+[ ]+> +\{evex\} lzcnt %r16,%r17 +[ ]*[0-9]+[ ]+> +\{nf\} popcnt %r16,%r17 +[ ]*[0-9]+[ ]+> +\{evex\} tzcnt %r16,%r17 +#... +[ ]*[0-9]+[ ]+> apx_nci: +#... +[ ]*[0-9]+[ ]+> +\.arch \.apx_nci +[ ]*[0-9]+[ ]+> * +[ ]*[0-9]+[ ]+> +\{evex\} add %r16,%r17 +[ ]*[0-9]+[ ]+> +add %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +\{nf\} add %r16,%r17 +[ ]*[0-9]+[ ]+\?+ 62ECFE08[ ]+> +adox %r16,%r17 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+> +adox %r16,%r17,%r18 +[ ]*[0-9]+[ ]+\?+ 62EAF400[ ]+> +andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+> +\{nf\} andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+\?+ 62EC8404[ ]+> +ccmpz %r16,%r17 +[ ]*[0-9]+[ ]+39C1 +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{load\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+44C8 +[ ]*[0-9]+[ ]+\?+ 62ECFC0C[ ]+> +\{store\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+44C1 +[ ]*[0-9]+[ ]+\?+ 62ECEC14[ ]+> +cfcmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+44C8 +[ ]*[0-9]+[ ]+\?+ 62ECEC10[ ]+> +cmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+44C8 +[ ]*[0-9]+[ ]+\?+ 62EC840A[ ]+> +\{evex\} cmp %r16,%r17 +[ ]*[0-9]+[ ]+39C1 +[ ]*[0-9]+[ ]+> +\{evex\} lzcnt %r16,%r17 +[ ]*[0-9]+[ ]+> +\{nf\} popcnt %r16,%r17 +[ ]*[0-9]+[ ]+> +\{evex\} tzcnt %r16,%r17 +#... +[ ]*[0-9]+[ ]+> apx_ndd: +#... +[ ]*[0-9]+[ ]+> +\.arch \.apx_ndd +[ ]*[0-9]+[ ]+> * +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{evex\} add %r16,%r17 +[ ]*[0-9]+[ ]+01C1 +[ ]*[0-9]+[ ]+\?+ 62ECEC10[ ]+> +add %r16,%r17,%r18 +[ ]*[0-9]+[ ]+01C1 +[ ]*[0-9]+[ ]+> +\{nf\} add %r16,%r17 +[ ]*[0-9]+[ ]+\?+ 62ECFE08[ ]+> +adox %r16,%r17 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+\?+ 62ECEE10[ ]+> +adox %r16,%r17,%r18 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+\?+ 62EAF400[ ]+> +andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+> +\{nf\} andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +ccmpz %r16,%r17 +[ ]*[0-9]+[ ]+> +\{load\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+> +\{store\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+> +cfcmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +cmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +\{evex\} cmp %r16,%r17 +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{evex\} lzcnt %r16,%r17 +[ ]*[0-9]+[ ]+F5C8 +[ ]*[0-9]+[ ]+> +\{nf\} popcnt %r16,%r17 +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{evex\} tzcnt %r16,%r17 +[ ]*[0-9]+[ ]+F4C8 +#... +[ ]*[0-9]+[ ]+> apx_nf: +#... +[ ]*[0-9]+[ ]+> +\.arch \.apx_nf +[ ]*[0-9]+[ ]+> * +[ ]*[0-9]+[ ]+> +\{evex\} add %r16,%r17 +[ ]*[0-9]+[ ]+> +add %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +\{nf\} add %r16,%r17 +[ ]*[0-9]+[ ]+\?+ 62ECFE08[ ]+> +adox %r16,%r17 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+> +adox %r16,%r17,%r18 +[ ]*[0-9]+[ ]+\?+ 62EAF400[ ]+> +andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+\?+ 62EAF404[ ]+> +\{nf\} andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+> +ccmpz %r16,%r17 +[ ]*[0-9]+[ ]+> +\{load\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+> +\{store\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+> +cfcmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +cmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+> +\{evex\} cmp %r16,%r17 +[ ]*[0-9]+[ ]+> +\{evex\} lzcnt %r16,%r17 +[ ]*[0-9]+[ ]+> +\{nf\} popcnt %r16,%r17 +[ ]*[0-9]+[ ]+> +\{evex\} tzcnt %r16,%r17 +#... +[ ]*[0-9]+[ ]+> apx_nci_ndd_nf: +#... +[ ]*[0-9]+[ ]+> +\.arch \.apx_nci_ndd_nf +[ ]*[0-9]+[ ]+> * +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{evex\} add %r16,%r17 +[ ]*[0-9]+[ ]+01C1 +[ ]*[0-9]+[ ]+\?+ 62ECEC10[ ]+> +add %r16,%r17,%r18 +[ ]*[0-9]+[ ]+01C1 +[ ]*[0-9]+[ ]+\?+ 62ECFC0C[ ]+> +\{nf\} add %r16,%r17 +[ ]*[0-9]+[ ]+01C1 +[ ]*[0-9]+[ ]+\?+ 62ECFE08[ ]+> +adox %r16,%r17 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+\?+ 62ECEE10[ ]+> +adox %r16,%r17,%r18 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+\?+ 62EAF400[ ]+> +andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+\?+ 62EAF404[ ]+> +\{nf\} andn %r16,%r17,%r18 +[ ]*[0-9]+[ ]+F2D0 +[ ]*[0-9]+[ ]+\?+ 62EC8404[ ]+> +ccmpz %r16,%r17 +[ ]*[0-9]+[ ]+39C1 +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{load\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+44C8 +[ ]*[0-9]+[ ]+\?+ 62ECFC0C[ ]+> +\{store\} cfcmovz %r16,%r17 +[ ]*[0-9]+[ ]+44C1 +[ ]*[0-9]+[ ]+\?+ 62ECEC14[ ]+> +cfcmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+44C8 +[ ]*[0-9]+[ ]+\?+ 62ECEC10[ ]+> +cmovz %r16,%r17,%r18 +[ ]*[0-9]+[ ]+44C8 +[ ]*[0-9]+[ ]+\?+ 62EC840A[ ]+> +\{evex\} cmp %r16,%r17 +[ ]*[0-9]+[ ]+39C1 +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{evex\} lzcnt %r16,%r17 +[ ]*[0-9]+[ ]+F5C8 +[ ]*[0-9]+[ ]+\?+ 62ECFC0C[ ]+> +\{nf\} popcnt %r16,%r17 +[ ]*[0-9]+[ ]+88C8 +[ ]*[0-9]+[ ]+\?+ 62ECFC08[ ]+> +\{evex\} tzcnt %r16,%r17 +[ ]*[0-9]+[ ]+F4C8 +[ ]*[0-9]+[ ]+> * +[ ]*[0-9]+[ ]+ +[ ]*[0-9]+[ ]+\.arch default +[ ]*[0-9]+[ ]+\.arch \.noapx_nci_ndd_nf +[ ]*[0-9]+[ ]+\?+ D55801C1[ ]+add[ ]+%r16, %r17 +[ ]*[0-9]+[ ]+\?+ 62ECFE08[ ]+adox[ ]+%r16, %r17 +[ ]*[0-9]+[ ]+66C8 +[ ]*[0-9]+[ ]+\?+ 62EAF400[ ]+andn[ ]+%r16, %r17, %r18 +[ ]*[0-9]+[ ]+F2D0 +#pass diff --git a/gas/testsuite/gas/i386/apx-nci-ndd-nf.s b/gas/testsuite/gas/i386/apx-nci-ndd-nf.s new file mode 100644 index 0000000..ebffc24 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-nci-ndd-nf.s @@ -0,0 +1,37 @@ +# .arch .apx_n* directives + + .text + .irp feat, f, nci, ndd, nf, nci_ndd_nf + +apx_\feat: + .arch generic64 + .arch .adx + .arch .bmi + .arch .lzcnt + .arch .popcnt + .arch .apx_\feat + + {evex} add %r16, %r17 + add %r16, %r17, %r18 + {nf} add %r16, %r17 + adox %r16, %r17 + adox %r16, %r17, %r18 + andn %r16, %r17, %r18 + {nf} andn %r16, %r17, %r18 + ccmpz %r16, %r17 + {load} cfcmovz %r16, %r17 + {store} cfcmovz %r16, %r17 + cfcmovz %r16, %r17, %r18 + cmovz %r16, %r17, %r18 + {evex} cmp %r16, %r17 + {evex} lzcnt %r16, %r17 + {nf} popcnt %r16, %r17 + {evex} tzcnt %r16, %r17 + + .endr + + .arch default + .arch .noapx_nci_ndd_nf + add %r16, %r17 + adox %r16, %r17 + andn %r16, %r17, %r18 diff --git a/gas/testsuite/gas/i386/arch-16-znver6.d b/gas/testsuite/gas/i386/arch-16-znver6.d new file mode 100644 index 0000000..f8aa56a --- /dev/null +++ b/gas/testsuite/gas/i386/arch-16-znver6.d @@ -0,0 +1,16 @@ +#source: arch-16.s +#as: -march=znver6 +#objdump: -dw +#name: i386 arch 16 (znver6) + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <\.text>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1 +[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2 +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3 +#pass diff --git a/gas/testsuite/gas/i386/arch-16.d b/gas/testsuite/gas/i386/arch-16.d new file mode 100644 index 0000000..24b5516 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-16.d @@ -0,0 +1,14 @@ +#objdump: -dw +#name: i386 arch 6 + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <\.text>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1 +[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2 +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3 +#pass diff --git a/gas/testsuite/gas/i386/arch-16.s b/gas/testsuite/gas/i386/arch-16.s new file mode 100644 index 0000000..f801784 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-16.s @@ -0,0 +1,8 @@ +# Test -march= + .text + + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM + vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT + vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA + vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8 + vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16 diff --git a/gas/testsuite/gas/i386/avx512_bmm.d b/gas/testsuite/gas/i386/avx512_bmm.d new file mode 100644 index 0000000..043b6ff --- /dev/null +++ b/gas/testsuite/gas/i386/avx512_bmm.d @@ -0,0 +1,23 @@ +#objdump: -dw +#name: i386 AVX512_BMM insns + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <bmm>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3 +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3 +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrevb %zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrevb %zmm1,%zmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrevb 0x2000\(%edx\),%zmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 52 80[\s]*vbitrevb -0x2000\(%edx\),%zmm2\{%k1\}\{z\} +#pass diff --git a/gas/testsuite/gas/i386/avx512_bmm.s b/gas/testsuite/gas/i386/avx512_bmm.s new file mode 100644 index 0000000..4ea0781 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512_bmm.s @@ -0,0 +1,21 @@ +# Check 32bit AVX512_BMM instructions + + .text +bmm: + .arch .noavx512vl + vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM + vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM + vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM + vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8 + + vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM + vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM + vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM + vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8 + + vbitrevb %zmm1, %zmm2 # AVX512_BMM + vbitrevb %zmm1, %zmm2{%k1}{z} # AVX512_BMM + vbitrevb -123456(%esp,%esi,8), %zmm2 # AVX512_BMM + vbitrevb -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM + vbitrevb 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM + vbitrevb -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8 diff --git a/gas/testsuite/gas/i386/avx512_bmm_vl-inval.l b/gas/testsuite/gas/i386/avx512_bmm_vl-inval.l new file mode 100644 index 0000000..2240afe --- /dev/null +++ b/gas/testsuite/gas/i386/avx512_bmm_vl-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:5: Error: operand .* `vbmacor16x16x16' +.*:6: Error: operand .* `vbmacxor16x16x16' diff --git a/gas/testsuite/gas/i386/avx512_bmm_vl-inval.s b/gas/testsuite/gas/i386/avx512_bmm_vl-inval.s new file mode 100644 index 0000000..d082774 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512_bmm_vl-inval.s @@ -0,0 +1,6 @@ +# Check illegal 32bit AVX512_BMM,AVX512VL instructions + + .text +_start: + vbmacor16x16x16 %xmm1, %xmm2, %xmm3 + vbmacxor16x16x16 %xmm1, %xmm2, %xmm3 diff --git a/gas/testsuite/gas/i386/avx512_bmm_vl.d b/gas/testsuite/gas/i386/avx512_bmm_vl.d new file mode 100644 index 0000000..7771679 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512_bmm_vl.d @@ -0,0 +1,29 @@ +#objdump: -dw +#name: i386 AVX512_BMM,AVX512VL insns + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <bmm>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrevb %xmm1,%xmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrevb %xmm1,%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrevb 0x800\(%edx\),%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 52 80[\s]*vbitrevb -0x800\(%edx\),%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrevb %ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrevb %ymm1,%ymm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrevb 0x1000\(%eax\),%ymm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 50 80[\s]*vbitrevb -0x1000\(%eax\),%ymm2\{%k1\}\{z\} +#pass diff --git a/gas/testsuite/gas/i386/avx512_bmm_vl.s b/gas/testsuite/gas/i386/avx512_bmm_vl.s new file mode 100644 index 0000000..b2ba5fa --- /dev/null +++ b/gas/testsuite/gas/i386/avx512_bmm_vl.s @@ -0,0 +1,26 @@ +# Check 32bit AVX512_BMM,AVX512VL instructions + + .text +bmm: + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL + vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8 + + vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL + vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8 + + vbitrevb %xmm1, %xmm2 # AVX512_BMM,AVX512VL + vbitrevb %xmm1, %xmm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %xmm2 # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8 + vbitrevb %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbitrevb %ymm1, %ymm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %ymm2 # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8 diff --git a/gas/testsuite/gas/i386/fsgs-intel.d b/gas/testsuite/gas/i386/fsgs-intel.d deleted file mode 100644 index 84e2ff6..0000000 --- a/gas/testsuite/gas/i386/fsgs-intel.d +++ /dev/null @@ -1,27 +0,0 @@ -#objdump: -dwMintel -#name: i386 FSGSBase (Intel disassembly) -#source: fsgs.s - -.*: +file format .* - - -Disassembly of section .text: - -0+ <foo>: -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx -#pass diff --git a/gas/testsuite/gas/i386/fsgs.d b/gas/testsuite/gas/i386/fsgs.d deleted file mode 100644 index f7b0d0f..0000000 --- a/gas/testsuite/gas/i386/fsgs.d +++ /dev/null @@ -1,26 +0,0 @@ -#objdump: -dw -#name: i386 FSGSBase - -.*: +file format .* - - -Disassembly of section .text: - -0+ <foo>: -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx -[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx -#pass diff --git a/gas/testsuite/gas/i386/fsgs.s b/gas/testsuite/gas/i386/fsgs.s deleted file mode 100644 index 92473a8..0000000 --- a/gas/testsuite/gas/i386/fsgs.s +++ /dev/null @@ -1,19 +0,0 @@ -# Check FSGSBase new instructions. - - .text -foo: - .rept 2 - rdfsbase %ebx - rdgsbase %ebx - wrfsbase %ebx - wrgsbase %ebx - - .intel_syntax noprefix - rdfsbase ebx - rdgsbase ebx - wrfsbase ebx - wrgsbase ebx - - .att_syntax prefix - .code16 - .endr diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 9b23a7b..08f3e3c 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -215,6 +215,7 @@ if [gas_32_check] then { run_dump_test "arch-14-znver3" run_dump_test "arch-14-znver4" run_dump_test "arch-15-znver5" + run_dump_test "arch-16-znver6" run_dump_test "arch-10-btver1" run_dump_test "arch-10-btver2" run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al" @@ -229,6 +230,7 @@ if [gas_32_check] then { run_dump_test "arch-14" run_dump_test "arch-14-1" run_dump_test "arch-15" + run_dump_test "arch-16" run_list_test "arch-dflt" "-march=generic32 -al" run_list_test "arch-stk" "-march=generic32 -al" run_dump_test "8087" @@ -364,8 +366,6 @@ if [gas_32_check] then { run_dump_test "tbm-16bit" run_dump_test "f16c" run_dump_test "f16c-intel" - run_dump_test "fsgs" - run_dump_test "fsgs-intel" run_dump_test "rdrnd" run_dump_test "rdrnd-intel" run_dump_test "bundle" @@ -479,6 +479,9 @@ if [gas_32_check] then { run_dump_test "avx512vnni-intel" run_dump_test "avx512vnni_vl" run_dump_test "avx512vnni_vl-intel" + run_dump_test "avx512_bmm" + run_dump_test "avx512_bmm_vl" + run_list_test "avx512_bmm_vl-inval" run_dump_test "avx512bitalg" run_dump_test "avx512bitalg-intel" run_dump_test "avx512bitalg_vl" diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l index 2525565..660c429 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l @@ -202,8 +202,8 @@ .*:211: Error: no VEX/XOP encoding for `and' .*:212: Error: no VEX/XOP encoding for `and' .*:213: Error: .* `and' -.*:214: Error: no VEX/XOP encoding for `and' -.*:215: Error: no VEX/XOP encoding for `and' +.*:214: Error: .* `and' +.*:215: Error: .* `and' .*:216: Error: .* `and' .*:219: Error: .* `andn' #pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-6-znver6.d b/gas/testsuite/gas/i386/x86-64-arch-6-znver6.d new file mode 100644 index 0000000..54c6374 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-6-znver6.d @@ -0,0 +1,16 @@ +#source: x86-64-arch-6.s +#as: -march=znver6 +#objdump: -dw +#name: x86-64 arch 6 (znver6) + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <\.text>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1 +[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2 +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-6.d b/gas/testsuite/gas/i386/x86-64-arch-6.d new file mode 100644 index 0000000..4fb1f0d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-6.d @@ -0,0 +1,14 @@ +#objdump: -dw +#name: x86-64 arch 6 + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <\.text>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1 +[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2 +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-6.s b/gas/testsuite/gas/i386/x86-64-arch-6.s new file mode 100644 index 0000000..f801784 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-6.s @@ -0,0 +1,8 @@ +# Test -march= + .text + + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM + vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT + vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA + vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8 + vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16 diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.d b/gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.d new file mode 100644 index 0000000..63425d7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.d @@ -0,0 +1,14 @@ +#objdump: -dw +#name: x86_64 AVX512_BMM BAD insns +#source: x86-64-avx512_bmm-bad.s + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <\.text>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 08 80[\s]*\(bad\) +[\s]*[a-f0-9]+:[\s]*c7[\s]*\(bad\) +[\s]*[a-f0-9]+:[\s]*62 f6 ec 08 80[\s]*\(bad\) +[\s]*[a-f0-9]+:[\s]*c7[\s]*.* +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.s b/gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.s new file mode 100644 index 0000000..a84f3a6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.s @@ -0,0 +1,8 @@ +# Check Illegal 64-bit AVX512_BMM instructions + + .text + #vbmacor16x16x16 %xmm7, %xmm2, %xmm0 set EVEX.L'L = 0 (illegal value). + .insn EVEX.128.NP.M6.W0 0x80, %xmm7, %xmm2, %xmm0 + + #vbmacxor16x16x16 %xmm7, %xmm2, %xmm0 set EVEX.L'L = 0 (illegal value). + .insn EVEX.128.NP.M6.W1 0x80, %xmm7, %xmm2, %xmm0 diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm.d b/gas/testsuite/gas/i386/x86-64-avx512_bmm.d new file mode 100644 index 0000000..0213880 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm.d @@ -0,0 +1,23 @@ +#objdump: -dw +#name: x86-64 AVX512_BMM insns + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <bmm>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3 +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3 +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrevb %zmm1,%zmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrevb %zmm1,%zmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrevb 0x2000\(%edx\),%zmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 52 80[\s]*vbitrevb -0x2000\(%edx\),%zmm2\{%k1\}\{z\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm.s b/gas/testsuite/gas/i386/x86-64-avx512_bmm.s new file mode 100644 index 0000000..2ab9f96 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm.s @@ -0,0 +1,21 @@ +# Check 64bit AVX512_BMM instructions + + .text +bmm: + .arch .noavx512vl + vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM + vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM + vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM + vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8 + + vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM + vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM + vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM + vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8 + + vbitrevb %zmm1, %zmm2 # AVX512_BMM + vbitrevb %zmm1, %zmm2{%k1}{z} # AVX512_BMM + vbitrevb -123456(%esp,%esi,8), %zmm2 # AVX512_BMM + vbitrevb -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM + vbitrevb 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM + vbitrevb -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8 diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l new file mode 100644 index 0000000..2240afe --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:5: Error: operand .* `vbmacor16x16x16' +.*:6: Error: operand .* `vbmacxor16x16x16' diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s new file mode 100644 index 0000000..f4d816b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s @@ -0,0 +1,6 @@ +# Check illegal 64bit AVX512_BMM,AVX512VL instructions + + .text +_start: + vbmacor16x16x16 %xmm1, %xmm2, %xmm3 + vbmacxor16x16x16 %xmm1, %xmm2, %xmm3 diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.d b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.d new file mode 100644 index 0000000..1bf26dc --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.d @@ -0,0 +1,29 @@ +#objdump: -dw +#name: x86-64 AVX512_BMM,AVX512VL insns + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]+ <bmm>: +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3 +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrevb %xmm1,%xmm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrevb %xmm1,%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrevb 0x800\(%edx\),%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 52 80[\s]*vbitrevb -0x800\(%edx\),%xmm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrevb %ymm1,%ymm2 +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrevb %ymm1,%ymm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2 +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrevb 0x1000\(%eax\),%ymm2\{%k1\}\{z\} +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 50 80[\s]*vbitrevb -0x1000\(%eax\),%ymm2\{%k1\}\{z\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.s b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.s new file mode 100644 index 0000000..969225f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.s @@ -0,0 +1,26 @@ +# Check 64bit AVX512_BMM,AVX512VL instructions + + .text +bmm: + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL + vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8 + + vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL + vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8 + + vbitrevb %xmm1, %xmm2 # AVX512_BMM,AVX512VL + vbitrevb %xmm1, %xmm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %xmm2 # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8 + vbitrevb %ymm1, %ymm2 # AVX512_BMM,AVX512VL + vbitrevb %ymm1, %ymm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %ymm2 # AVX512_BMM,AVX512VL + vbitrevb -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL + vbitrevb -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8 diff --git a/gas/testsuite/gas/i386/x86-64-fsgs-intel.d b/gas/testsuite/gas/i386/x86-64-fsgs-intel.d index 778f83d..ba768e8 100644 --- a/gas/testsuite/gas/i386/x86-64-fsgs-intel.d +++ b/gas/testsuite/gas/i386/x86-64-fsgs-intel.d @@ -1,3 +1,4 @@ +#as: --divide #objdump: -drwMintel #name: x86-64 FSGSBase (Intel mode) #source: x86-64-fsgs.s @@ -24,6 +25,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: f3 48 0f ae db wrgsbase rbx [ ]*[a-f0-9]+: f3 41 0f ae d8 wrgsbase r8d [ ]*[a-f0-9]+: f3 49 0f ae d8 wrgsbase r8 +[ ]*[a-f0-9]+: 66 f3 0f ae c1 data16 rdfsbase ecx +[ ]*[a-f0-9]+: f3 66 0f ae d9 data16 wrgsbase ecx [ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx [ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase rbx [ ]*[a-f0-9]+: f3 41 0f ae c0 rdfsbase r8d diff --git a/gas/testsuite/gas/i386/x86-64-fsgs.d b/gas/testsuite/gas/i386/x86-64-fsgs.d index 0549a3f..4ce1e68 100644 --- a/gas/testsuite/gas/i386/x86-64-fsgs.d +++ b/gas/testsuite/gas/i386/x86-64-fsgs.d @@ -1,3 +1,4 @@ +#as: --divide #objdump: -dw #name: x86-64 FSGSBase @@ -23,6 +24,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+: f3 48 0f ae db wrgsbase %rbx [ ]*[a-f0-9]+: f3 41 0f ae d8 wrgsbase %r8d [ ]*[a-f0-9]+: f3 49 0f ae d8 wrgsbase %r8 +[ ]*[a-f0-9]+: 66 f3 0f ae c1 data16 rdfsbase %ecx +[ ]*[a-f0-9]+: f3 66 0f ae d9 data16 wrgsbase %ecx [ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx [ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase %rbx [ ]*[a-f0-9]+: f3 41 0f ae c0 rdfsbase %r8d diff --git a/gas/testsuite/gas/i386/x86-64-fsgs.s b/gas/testsuite/gas/i386/x86-64-fsgs.s index 8234b85..3356348 100644 --- a/gas/testsuite/gas/i386/x86-64-fsgs.s +++ b/gas/testsuite/gas/i386/x86-64-fsgs.s @@ -19,6 +19,10 @@ foo: wrgsbase %r8d wrgsbase %r8 + data16 rdfsbase %ecx + repe + .insn 0x0fae/3, %cx + .intel_syntax noprefix rdfsbase ebx rdfsbase rbx diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 738cd31..feb26cc 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -182,6 +182,7 @@ run_dump_test "x86-64-arch-4" run_dump_test "x86-64-arch-4-1" run_dump_test "rmpquery" run_dump_test "x86-64-arch-5" +run_dump_test "x86-64-arch-6" run_dump_test "x86-64-arch-2-lzcnt" run_dump_test "x86-64-arch-2-prefetchw" run_dump_test "x86-64-arch-2-bdver1" @@ -193,6 +194,7 @@ run_dump_test "x86-64-arch-3-znver2" run_dump_test "x86-64-arch-4-znver3" run_dump_test "x86-64-arch-4-znver4" run_dump_test "x86-64-arch-5-znver5" +run_dump_test "x86-64-arch-6-znver6" run_dump_test "x86-64-arch-2-btver1" run_dump_test "x86-64-arch-2-btver2" run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al" @@ -359,6 +361,7 @@ run_dump_test "x86-64-apx-cfcmov-intel" run_dump_test "x86-64-apx-pushp-popp" run_dump_test "x86-64-apx-pushp-popp-intel" run_list_test "x86-64-apx-pushp-popp-inval" +run_list_test "apx-nci-ndd-nf" "-almn" run_dump_test "x86-64-avx512dq-rcigrd" run_dump_test "x86-64-avx512dq-rcigrne" run_dump_test "x86-64-avx512dq-rcigru" @@ -441,6 +444,10 @@ run_dump_test "x86-64-avx512vnni" run_dump_test "x86-64-avx512vnni-intel" run_dump_test "x86-64-avx512vnni_vl" run_dump_test "x86-64-avx512vnni_vl-intel" +run_dump_test "x86-64-avx512_bmm" +run_dump_test "x86-64-avx512_bmm_vl" +run_list_test "x86-64-avx512_bmm_vl-inval" +run_dump_test "x86-64-avx512_bmm-bad" run_dump_test "x86-64-avx512bitalg" run_dump_test "x86-64-avx512bitalg-intel" run_dump_test "x86-64-avx512bitalg_vl" diff --git a/gas/testsuite/gas/loongarch/illegal-operand.l b/gas/testsuite/gas/loongarch/illegal-operand.l index 33e859c..09b5ea3 100644 --- a/gas/testsuite/gas/loongarch/illegal-operand.l +++ b/gas/testsuite/gas/loongarch/illegal-operand.l @@ -101,13 +101,11 @@ .*:101: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 .*:102: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 .*:103: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -.*:104: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -.*:105: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 +.*:106: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd +.*:107: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd .*:108: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd .*:109: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -.*:110: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -.*:111: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd +.*:112: Error: g\?csrxchg require rj != r0 && rj != r1 +.*:113: Error: g\?csrxchg require rj != r0 && rj != r1 .*:114: Error: g\?csrxchg require rj != r0 && rj != r1 .*:115: Error: g\?csrxchg require rj != r0 && rj != r1 -.*:116: Error: g\?csrxchg require rj != r0 && rj != r1 -.*:117: Error: g\?csrxchg require rj != r0 && rj != r1 diff --git a/gas/testsuite/gas/loongarch/illegal-operand.s b/gas/testsuite/gas/loongarch/illegal-operand.s index 3860539..60de2fd 100644 --- a/gas/testsuite/gas/loongarch/illegal-operand.s +++ b/gas/testsuite/gas/loongarch/illegal-operand.s @@ -31,8 +31,6 @@ amadd_db.b $r1,$r1,$r2 amadd_db.b $r1,$r2,$r1 amadd_db.h $r1,$r1,$r2 amadd_db.h $r1,$r2,$r1 -amswap.w $r1,$r1,$r2 -amswap.w $r1,$r2,$r1 amswap.d $r1,$r1,$r2 amswap.d $r1,$r2,$r1 amadd.w $r1,$r1,$r2 diff --git a/gas/testsuite/gas/loongarch/macro_ud.d b/gas/testsuite/gas/loongarch/macro_ud.d new file mode 100644 index 0000000..dbc1cdc --- /dev/null +++ b/gas/testsuite/gas/loongarch/macro_ud.d @@ -0,0 +1,41 @@ +#as: +#objdump: -d + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 38600400 amswap.w \$zero, \$ra, \$zero + *[0-9a-f]+: 38600421 amswap.w \$ra, \$ra, \$ra + *[0-9a-f]+: 38600442 amswap.w \$tp, \$ra, \$tp + *[0-9a-f]+: 38600463 amswap.w \$sp, \$ra, \$sp + *[0-9a-f]+: 38600484 amswap.w \$a0, \$ra, \$a0 + *[0-9a-f]+: 386004a5 amswap.w \$a1, \$ra, \$a1 + *[0-9a-f]+: 386004c6 amswap.w \$a2, \$ra, \$a2 + *[0-9a-f]+: 386004e7 amswap.w \$a3, \$ra, \$a3 + *[0-9a-f]+: 38600508 amswap.w \$a4, \$ra, \$a4 + *[0-9a-f]+: 38600529 amswap.w \$a5, \$ra, \$a5 + *[0-9a-f]+: 3860054a amswap.w \$a6, \$ra, \$a6 + *[0-9a-f]+: 3860056b amswap.w \$a7, \$ra, \$a7 + *[0-9a-f]+: 3860058c amswap.w \$t0, \$ra, \$t0 + *[0-9a-f]+: 386005ad amswap.w \$t1, \$ra, \$t1 + *[0-9a-f]+: 386005ce amswap.w \$t2, \$ra, \$t2 + *[0-9a-f]+: 386005ef amswap.w \$t3, \$ra, \$t3 + *[0-9a-f]+: 38600610 amswap.w \$t4, \$ra, \$t4 + *[0-9a-f]+: 38600631 amswap.w \$t5, \$ra, \$t5 + *[0-9a-f]+: 38600652 amswap.w \$t6, \$ra, \$t6 + *[0-9a-f]+: 38600673 amswap.w \$t7, \$ra, \$t7 + *[0-9a-f]+: 38600694 amswap.w \$t8, \$ra, \$t8 + *[0-9a-f]+: 386006b5 amswap.w \$r21, \$ra, \$r21 + *[0-9a-f]+: 386006d6 amswap.w \$fp, \$ra, \$fp + *[0-9a-f]+: 386006f7 amswap.w \$s0, \$ra, \$s0 + *[0-9a-f]+: 38600718 amswap.w \$s1, \$ra, \$s1 + *[0-9a-f]+: 38600739 amswap.w \$s2, \$ra, \$s2 + *[0-9a-f]+: 3860075a amswap.w \$s3, \$ra, \$s3 + *[0-9a-f]+: 3860077b amswap.w \$s4, \$ra, \$s4 + *[0-9a-f]+: 3860079c amswap.w \$s5, \$ra, \$s5 + *[0-9a-f]+: 386007bd amswap.w \$s6, \$ra, \$s6 + *[0-9a-f]+: 386007de amswap.w \$s7, \$ra, \$s7 + *[0-9a-f]+: 386007ff amswap.w \$s8, \$ra, \$s8 diff --git a/gas/testsuite/gas/loongarch/macro_ud.s b/gas/testsuite/gas/loongarch/macro_ud.s new file mode 100644 index 0000000..75ebcb8 --- /dev/null +++ b/gas/testsuite/gas/loongarch/macro_ud.s @@ -0,0 +1,32 @@ +ud 0 +ud 1 +ud 2 +ud 3 +ud 4 +ud 5 +ud 6 +ud 7 +ud 8 +ud 9 +ud 10 +ud 11 +ud 12 +ud 13 +ud 14 +ud 15 +ud 16 +ud 17 +ud 18 +ud 19 +ud 20 +ud 21 +ud 22 +ud 23 +ud 24 +ud 25 +ud 26 +ud 27 +ud 28 +ud 29 +ud 30 +ud 31 |