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-rw-r--r--gas/testsuite/gas/arm/mve-vand-bad.d5
-rw-r--r--gas/testsuite/gas/arm/mve-vand-bad.l27
-rw-r--r--gas/testsuite/gas/arm/mve-vand-bad.s38
-rw-r--r--gas/testsuite/gas/arm/mve-vbic-bad.d5
-rw-r--r--gas/testsuite/gas/arm/mve-vbic-bad.l28
-rw-r--r--gas/testsuite/gas/arm/mve-vbic-bad.s38
-rw-r--r--gas/testsuite/gas/arm/mve-veor-bad.d5
-rw-r--r--gas/testsuite/gas/arm/mve-veor-bad.l12
-rw-r--r--gas/testsuite/gas/arm/mve-veor-bad.s18
-rw-r--r--gas/testsuite/gas/arm/mve-vorn-bad.d5
-rw-r--r--gas/testsuite/gas/arm/mve-vorn-bad.l27
-rw-r--r--gas/testsuite/gas/arm/mve-vorn-bad.s38
-rw-r--r--gas/testsuite/gas/arm/mve-vorr-bad.d5
-rw-r--r--gas/testsuite/gas/arm/mve-vorr-bad.l27
-rw-r--r--gas/testsuite/gas/arm/mve-vorr-bad.s38
15 files changed, 316 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/mve-vand-bad.d b/gas/testsuite/gas/arm/mve-vand-bad.d
new file mode 100644
index 0000000..1889759
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vand-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VAND instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vand-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vand-bad.l b/gas/testsuite/gas/arm/mve-vand-bad.l
new file mode 100644
index 0000000..f6044b1
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vand-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vand q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vandt q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vand.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vandt.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vand.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vand.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vand.i16 q0,#0'
+[^:]*:38: Error: immediate value out of range -- `vand.i32 q0,#0'
diff --git a/gas/testsuite/gas/arm/mve-vand-bad.s b/gas/testsuite/gas/arm/mve-vand-bad.s
new file mode 100644
index 0000000..77f27bd
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vand-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vand q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vand.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vandeq q0, q1, q2
+vandeq q0, q1, q2
+vpst
+vandeq q0, q1, q2
+vpst
+vand q0, q1, q2
+vandt q0, q1, q2
+cond2
+it eq
+vandeq.i16 q0, #255
+vandeq.i16 q0, #255
+vpst
+vandeq.i16 q0, #255
+vpst
+vand.i16 q0, #255
+vandt.i16 q0, #255
+vand.i8 q0, #255
+vand.i64 q0, #255
+vand.i16 q0, #0
+vand.i32 q0, #0
diff --git a/gas/testsuite/gas/arm/mve-vbic-bad.d b/gas/testsuite/gas/arm/mve-vbic-bad.d
new file mode 100644
index 0000000..5c17bf4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VBIC instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vbic-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vbic-bad.l b/gas/testsuite/gas/arm/mve-vbic-bad.l
new file mode 100644
index 0000000..10deb9d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.l
@@ -0,0 +1,28 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vbic q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vbict q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vbic.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vbict.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vbic.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vbic.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vbic.i16 q0,#257'
+[^:]*:38: Error: immediate value out of range -- `vbic.i32 q0,#257'
+
diff --git a/gas/testsuite/gas/arm/mve-vbic-bad.s b/gas/testsuite/gas/arm/mve-vbic-bad.s
new file mode 100644
index 0000000..4f35158
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vbic q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vbic.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vbiceq q0, q1, q2
+vbiceq q0, q1, q2
+vpst
+vbiceq q0, q1, q2
+vpst
+vbic q0, q1, q2
+vbict q0, q1, q2
+cond2
+it eq
+vbiceq.i16 q0, #255
+vbiceq.i16 q0, #255
+vpst
+vbiceq.i16 q0, #255
+vpst
+vbic.i16 q0, #255
+vbict.i16 q0, #255
+vbic.i8 q0, #255
+vbic.i64 q0, #255
+vbic.i16 q0, #257
+vbic.i32 q0, #257
diff --git a/gas/testsuite/gas/arm/mve-veor-bad.d b/gas/testsuite/gas/arm/mve-veor-bad.d
new file mode 100644
index 0000000..e512286
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-veor-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VEOR instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-veor-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-veor-bad.l b/gas/testsuite/gas/arm/mve-veor-bad.l
new file mode 100644
index 0000000..3da9c71
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-veor-bad.l
@@ -0,0 +1,12 @@
+[^:]*: Assembler messages:
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Error: syntax error -- `veoreq q0,q1,q2'
+[^:]*:13: Error: syntax error -- `veoreq q0,q1,q2'
+[^:]*:15: Error: syntax error -- `veoreq q0,q1,q2'
+[^:]*:17: Error: instruction missing MVE vector predication code -- `veor q0,q1,q2'
+[^:]*:18: Error: vector predicated instruction should be in VPT/VPST block -- `veort q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-veor-bad.s b/gas/testsuite/gas/arm/mve-veor-bad.s
new file mode 100644
index 0000000..ffc1a00
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-veor-bad.s
@@ -0,0 +1,18 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+veor q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+it eq
+veoreq q0, q1, q2
+veoreq q0, q1, q2
+vpst
+veoreq q0, q1, q2
+vpst
+veor q0, q1, q2
+veort q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vorn-bad.d b/gas/testsuite/gas/arm/mve-vorn-bad.d
new file mode 100644
index 0000000..e78957f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VORN instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vorn-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vorn-bad.l b/gas/testsuite/gas/arm/mve-vorn-bad.l
new file mode 100644
index 0000000..69e479b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vorn q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vornt q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vorneq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vorneq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vorneq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vorn.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vornt.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vorn.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vorn.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vorn.i16 q0,#0'
+[^:]*:38: Error: immediate value out of range -- `vorn.i32 q0,#0'
diff --git a/gas/testsuite/gas/arm/mve-vorn-bad.s b/gas/testsuite/gas/arm/mve-vorn-bad.s
new file mode 100644
index 0000000..9a2edb0
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorn q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorn.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vorneq q0, q1, q2
+vorneq q0, q1, q2
+vpst
+vorneq q0, q1, q2
+vpst
+vorn q0, q1, q2
+vornt q0, q1, q2
+cond2
+it eq
+vorneq.i16 q0, #255
+vorneq.i16 q0, #255
+vpst
+vorneq.i16 q0, #255
+vpst
+vorn.i16 q0, #255
+vornt.i16 q0, #255
+vorn.i8 q0, #255
+vorn.i64 q0, #255
+vorn.i16 q0, #0
+vorn.i32 q0, #0
diff --git a/gas/testsuite/gas/arm/mve-vorr-bad.d b/gas/testsuite/gas/arm/mve-vorr-bad.d
new file mode 100644
index 0000000..4e94b8a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VORR instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vorr-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vorr-bad.l b/gas/testsuite/gas/arm/mve-vorr-bad.l
new file mode 100644
index 0000000..19a0ab8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vorr q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vorrt q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vorreq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vorreq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vorreq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vorr.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vorrt.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vorr.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vorr.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vorr.i16 q0,#257'
+[^:]*:38: Error: immediate value out of range -- `vorr.i32 q0,#257'
diff --git a/gas/testsuite/gas/arm/mve-vorr-bad.s b/gas/testsuite/gas/arm/mve-vorr-bad.s
new file mode 100644
index 0000000..671e35f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorr q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorr.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vorreq q0, q1, q2
+vorreq q0, q1, q2
+vpst
+vorreq q0, q1, q2
+vpst
+vorr q0, q1, q2
+vorrt q0, q1, q2
+cond2
+it eq
+vorreq.i16 q0, #255
+vorreq.i16 q0, #255
+vpst
+vorreq.i16 q0, #255
+vpst
+vorr.i16 q0, #255
+vorrt.i16 q0, #255
+vorr.i8 q0, #255
+vorr.i64 q0, #255
+vorr.i16 q0, #257
+vorr.i32 q0, #257