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-rw-r--r--gas/doc/as.texi53
-rw-r--r--gas/doc/c-aarch64.texi18
-rw-r--r--gas/doc/c-riscv.texi36
3 files changed, 100 insertions, 7 deletions
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 40d45f7..70c2540 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -260,7 +260,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{--sectname-subst}]
[@b{--size-check=[error|warning]}]
[@b{--statistics}]
- [@b{-v}] [@b{-version}] [@b{--version}]
+ [@b{-v}] [@b{--verbose}]
+ [@b{-version}] [@b{--version}]
[@b{-W}] [@b{--no-warn}] [@b{--warn}] [@b{--fatal-warnings}]
[@b{-w}] [@b{-x}]
[@b{-Z}] [@b{@@@var{FILE}}]
@@ -552,7 +553,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
@emph{Target RISC-V options:}
[@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
- [@b{-march}=@var{ISA}]
+ [@b{-march}=@var{ISA}|@var{Profiles}|@var{Profiles_ISA}]
[@b{-mabi}=@var{ABI}]
[@b{-mlittle-endian}|@b{-mbig-endian}]
@end ifset
@@ -778,6 +779,10 @@ symbols with the @code{STT_COMMON} type. The default can be controlled
by a configure option @option{--enable-elf-stt-common}.
@end ifset
+@item --emit-local-absolute
+Emit even pre-defined (local) absolute symbols to the outgoing symbol table.
+Note that this isn't the exact opposite of @samp{--strip-local-absolute}.
+
@item --emulation=@var{name}
If the assembler is configured to support multiple different target
configurations then this option can be used to select the desired form.
@@ -975,10 +980,11 @@ assembly.
Remove local absolute symbols from the outgoing symbol table.
@item -v
-@itemx -version
+@itemx --verbose
Print the @command{as} version.
@item --version
+@itemx -version
Print the @command{as} version and exit.
@item -W
@@ -3907,6 +3913,7 @@ the same order they were declared. This may break some debuggers.
* Symbol Names:: Symbol Names
* Dot:: The Special Dot Symbol
* Symbol Attributes:: Symbol Attributes
+* Predefined Symbols:: Predefined Symbols
@end menu
@node Labels
@@ -4248,6 +4255,30 @@ Language Reference Manual} (HP 92432-90001) under the @code{IMPORT} and
@code{EXPORT} assembler directive documentation.
@end ifset
+@node Predefined Symbols
+@section Predefined Symbols
+
+Certain pre-defined symbols will be made available for use, and possibly also
+inserted in the symbol table. Because of the use of parentheses, access to
+these symbols will require quotation.
+
+Independent of the specific target, the following symbols will (perhaps
+conditionally; see each individual item) be made available:
+@itemize @bullet
+
+@item @code{GAS(version)}
+The version of the assembler, expressed as @samp{major} @code{*} 100000000
+@code{+} @samp{minor} @code{*} 1000000 @code{+} @samp{rev} @code{*} 10000.
+
+@item @code{GAS(date)}
+The date of the assembler sources (which may not be the date the assembler was
+built). This is added only for non-release versions of gas. The specific
+value probably better isn't checked for, just its defined-ness.
+
+@end itemize
+
+All symbols of the form @code{GAS(...)} are reserved for use by GNU @value{AS}.
+
@node Expressions
@chapter Expressions
@@ -4551,6 +4582,7 @@ Some machine configurations provide additional directives.
* Equiv:: @code{.equiv @var{symbol}, @var{expression}}
* Eqv:: @code{.eqv @var{symbol}, @var{expression}}
* Err:: @code{.err}
+* Errif:: @code{.errif @var{expression}}
* Error:: @code{.error @var{string}}
* Exitm:: @code{.exitm}
* Extern:: @code{.extern}
@@ -4683,6 +4715,7 @@ Some machine configurations provide additional directives.
* VTableInherit:: @code{.vtable_inherit @var{child}, @var{parent}}
@end ifset
+* Warnif:: @code{.warnif @var{expression}}
* Warning:: @code{.warning @var{string}}
* Weak:: @code{.weak @var{names}}
* Weakref:: @code{.weakref @var{alias}, @var{symbol}}
@@ -5526,6 +5559,13 @@ If @command{@value{AS}} assembles a @code{.err} directive, it will print an erro
message and, unless the @option{-Z} option was used, it will not generate an
object file. This can be used to signal an error in conditionally compiled code.
+@node Errif
+@section @code{.errif "@var{expression}"}
+@cindex errif directive
+
+Record @var{expression} for evaluation at the end of assembly. Raise an error
+if the expression evaluates to non-zero.
+
@node Error
@section @code{.error "@var{string}"}
@cindex error directive
@@ -7719,6 +7759,13 @@ parent whose addend is the value of the child symbol. As a special case the
parent name of @code{0} is treated as referring to the @code{*ABS*} section.
@end ifset
+@node Warnif
+@section @code{.warnif "@var{expression}"}
+@cindex errif directive
+
+Record @var{expression} for evaluation at the end of assembly. Raise a
+warning if the expression evaluates to non-zero.
+
@node Warning
@section @code{.warning "@var{string}"}
@cindex warning directive
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 10888d1..d7e9c95 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -167,6 +167,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Branch Record Buffer extension.
@item @code{chk} @tab
@tab Enable the Check Feature Status Extension.
+@item @code{cmpbr} @tab
+ @tab Enable Compare and Branch instructions.
@item @code{compnum} @tab @code{simd}
@tab Enable the complex number SIMD extensions. An alias of @code{fcma}.
@item @code{cpa} @tab
@@ -185,6 +187,10 @@ automatically cause those extensions to be disabled.
@tab Enable the F32 Matrix Multiply extension
@item @code{f64mm} @tab @code{sve}
@tab Enable the F64 Matrix Multiply extension.
+@item @code{f8f16mm} @tab @code{simd} @code{fp8}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to half-precision instructions.
+@item @code{f8f32mm} @tab @code{simd} @code{fp}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to single-precision instructions.
@item @code{fcma} @tab @code{fp16}, @code{simd}
@tab Enable the complex number SIMD extensions.
@item @code{flagm} @tab
@@ -205,6 +211,8 @@ automatically cause those extensions to be disabled.
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@tab Enable Armv8.2 16-bit floating-point support.
+@item @code{fprcvt} @tab @code{fp}
+ @tab Enable Armv9.6 fprcvt instructions.
@item @code{frintts} @tab @code{fp}
@tab Enable floating-point round to integral value instructions.
@item @code{gcs} @tab
@@ -225,16 +233,22 @@ automatically cause those extensions to be disabled.
@tab Enable Large System extensions.
@item @code{lse128} @tab @code{lse}
@tab Enable the 128-bit Atomic Instructions extension.
+@item @code{lsfe} @tab @code{fp}
+ @tab Enable Large System Float Extension.
@item @code{lut} @tab
@tab Enable the Lookup Table (LUT) extension.
@item @code{memtag} @tab
@tab Enable Armv8.5-A Memory Tagging Extensions.
@item @code{mops} @tab
@tab Enable Armv8.8-A memcpy and memset acceleration instructions
+@item @code{occmo} @tab
+ @tab Enable Outer Cacheable Cache Maintenance Operations.
@item @code{pan} @tab
@tab Enable Privileged Access Never support.
@item @code{pauth} @tab
@tab Enable Pointer Authentication.
+@item @code{pops} @tab
+ @tab Enable Point of Physical Storage.
@item @code{predres} @tab
@tab Enable the Execution and Data and Prediction instructions.
@item @code{predres2} @tab @code{predres}
@@ -297,6 +311,10 @@ automatically cause those extensions to be disabled.
@tab Enable the Scalable Vector Extension.
@item @code{sve-b16b16} @tab
@tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-bfscale} @tab
+@tab Enable the SVE BFSCALE extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-f16f32mm} @tab @code{sve}
+@tab Enable the SVE_F16F32MM extension.
@item @code{sve2} @tab @code{sve}
@tab Enable SVE2.
@item @code{sve2-aes} @tab @code{sve2}, @code{aes}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 0a92e78..a4c819e 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -41,9 +41,11 @@ Generate position-independent code
@item -fno-pic
Don't generate position-independent code (default)
-@cindex @samp{-march=ISA} option, RISC-V
-@item -march=ISA
-Select the base isa, as specified by ISA. For example -march=rv32ima.
+@cindex @samp{-march=ISA|Profiles|Profiles_ISA} option, RISC-V
+@item -march=ISA|Profiles|Profiles_ISA
+Select the base isa, as specified by ISA or Profiles or Profies_ISA.
+For example @samp{-march=rv32ima} @samp{-march=RVI20U64}
+@samp{-march=RVI20U64_d}.
If this option and the architecture attributes aren't set, then assembler
will check the default configure setting --with-arch=ISA.
@@ -737,7 +739,12 @@ to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
for the default version of its base ISA. On the other hand, the architecture
@code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
-with default versions of the standard extensions.
+with default versions of the standard extensions. All Profiles are expanded
+ to the mandatory extensions it includes then processing. For example,
+@code{RVI20U32} is expanded to @code{RV32I2P0} for processing, which contains
+the mandatory extensions @code{I} as it defined. And you can also combine
+Profiles with ISA use underline, like @code{RVI20U32_D} is expanded to the
+@code{RV32I2P0_F2P0_D2P0}.
@item Tag_RISCV_unaligned_access (6)
Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
@@ -892,4 +899,25 @@ XSfCease provides an instruction to instigates power-down sequence.
It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}.
+@item XMipsCbop
+The XMipsCbop extension provides instruction mips.pref.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
+@item XMipsCmov
+The XMipsCmov extension provides instruction mips.ccmov.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
+@item XMipsExectl
+The XMipsExectl extension provides instructions mips.ehb, mips.ihb and mips.pause.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
+@item XMipsSlsp
+
+The XMipsSlsp extension provides instructions mips.ldp, mips.lwp, mips.sdp and mips.swp.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
@end table
generated by cgit v1.1 at 2025-07-07 19:34:01 +0000