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-rw-r--r--gas/doc/as.texi56
-rw-r--r--gas/doc/c-aarch64.texi4
-rw-r--r--gas/doc/c-i386.texi22
-rw-r--r--gas/doc/c-mips.texi10
-rw-r--r--gas/doc/c-riscv.texi185
-rw-r--r--gas/doc/c-s390.texi12
-rw-r--r--gas/doc/internals.texi2
7 files changed, 174 insertions, 117 deletions
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 33169a5..4c7799a 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -260,7 +260,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{--size-check=[error|warning]}]
[@b{--statistics}]
[@b{-v}] [@b{-version}] [@b{--version}]
- [@b{-W}] [@b{--warn}] [@b{--fatal-warnings}] [@b{-w}] [@b{-x}]
+ [@b{-W}] [@b{--no-warn}] [@b{--warn}] [@b{--fatal-warnings}]
+ [@b{-w}] [@b{-x}]
[@b{-Z}] [@b{@@@var{FILE}}]
[@var{target-options}]
[@b{--}|@var{files} @dots{}]
@@ -983,12 +984,12 @@ Print the @command{as} version and exit.
@itemx --no-warn
Suppress warning messages.
-@item --fatal-warnings
-Treat warnings as errors.
-
@item --warn
Don't suppress warning messages or treat them as errors.
+@item --fatal-warnings
+Treat warnings as errors.
+
@item -w
Ignored.
@@ -1960,7 +1961,7 @@ Specify which s390 processor variant is the target, @samp{g5} (or
@samp{arch6}), @samp{z9-109}, @samp{z9-ec} (or @samp{arch7}), @samp{z10} (or
@samp{arch8}), @samp{z196} (or @samp{arch9}), @samp{zEC12} (or @samp{arch10}),
@samp{z13} (or @samp{arch11}), @samp{z14} (or @samp{arch12}), @samp{z15}
-(or @samp{arch13}), or @samp{z16} (or @samp{arch14}).
+(or @samp{arch13}), @samp{z16} (or @samp{arch14}), or @samp{arch15}.
@item -mregnames
@itemx -mno-regnames
Allow or disallow symbolic names for registers.
@@ -2863,7 +2864,7 @@ option @samp{-v} (which you can also spell as @samp{-version}) on the
command line.
@node W
-@section Control Warnings: @option{-W}, @option{--warn}, @option{--no-warn}, @option{--fatal-warnings}
+@section Control Warnings: @option{-W}, @option{--no-warn}, @option{--warn}, @option{--fatal-warnings}
@command{@value{AS}} should never give a warning or error message when
assembling compiler output. But programs written by people often
@@ -2874,22 +2875,24 @@ made. All such warnings are directed to the standard error file.
@kindex --no-warn
@cindex suppressing warnings
@cindex warnings, suppressing
-If you use the @option{-W} and @option{--no-warn} options, no warnings are issued.
+If you use the @option{-W} or @option{--no-warn} option, no warnings are issued.
This only affects the warning messages: it does not change any particular of
how @command{@value{AS}} assembles your file. Errors, which stop the assembly,
are still reported.
+@kindex --warn
+@cindex outputing warnings
+@cindex warnings, switching on
+Warnings are switched on by default. They can be switched off with @option{-W} or
+@option{--no-warn}. Specifying the @option{--warn} again later on the command line
+will switch on warnings again, and cause them to be output as usual.
+
@kindex --fatal-warnings
@cindex errors, caused by warnings
@cindex warnings, causing error
If you use the @option{--fatal-warnings} option, @command{@value{AS}} considers
files that generate warnings to be in error.
-@kindex --warn
-@cindex warnings, switching on
-You can switch these options off again by specifying @option{--warn}, which
-causes warnings to be output as usual.
-
@node Z
@section Generate Object File in Spite of Errors: @option{-Z}
@cindex object file, after errors
@@ -2987,11 +2990,11 @@ as exactly one space.
@section Comments
@cindex comments
-There are two ways of rendering comments to @command{@value{AS}}. In both
-cases the comment is equivalent to one space.
+There are two ways of rendering comments to @command{@value{AS}}.
Anything from @samp{/*} through the next @samp{*/} is a comment.
-This means you may not nest these comments.
+This means you may not nest these comments. Such a comment is equivalent to
+one space, plus bumping the line counter accordingly.
@smallexample
/*
@@ -4497,6 +4500,7 @@ Some machine configurations provide additional directives.
* Asciz:: @code{.asciz "@var{string}"}@dots{}
* Attach_to_group:: @code{.attach_to_group @var{name}}
* Balign:: @code{.balign [@var{abs-expr}[, @var{abs-expr}]]}
+* Base64:: @code{.base64 "@var{string}"[, @dots{}]}
@ifset ELF
* Bss:: @code{.bss @var{subsection}}
@end ifset
@@ -4784,7 +4788,7 @@ and use the result as a string.
@item No passing arguments to macros based upon keyword assignment.
In altmacro mode arguments cannot be passed to macros by keyword assignment.
-See @xref{altmacro-keyword-arguments} for more details
+See @xref{altmacro-keyword-arguments}.
@end ftable
@node Ascii
@@ -4851,6 +4855,24 @@ filled in with the value 0x368d (the exact placement of the bytes depends upon
the endianness of the processor). If it skips 1 or 3 bytes, the fill value is
undefined.
+@node Base64
+@section @code{.base64 "@var{string}"[, @dots{}]}
+Allows binary data to be entered into a section encoded as a base64 string.
+There is no maximum length to the strings, but they must be a multiple of four
+bytes long. If necessary the ends of the strings can be padded with @code{=}
+characters. Line breaks, control characters and escaped characters are not
+allowed in the strings. The strings must be enclosed between double quote
+characters. Multiple strings are allowed, but they must be separated by
+commas.
+
+As an example of how to create a base64 encoded string, see the
+@command{base64} program (with its @option{-w0} option to disable line breaks).
+
+Note: for targets where the size of a byte is larger than the size of an octet
+the @code{.base64} directive will, if necessary, pad the end of the @emph{last}
+string so that the total number of octets generated are a multiple the number
+of octets in a byte.
+
@ifset ELF
@node Bss
@section @code{.bss @var{subsection}}
@@ -7785,7 +7807,7 @@ section, using the endian model of the target. If an expression will not fit
in two bytes, a warning message is displayed and the least significant two
bytes of the expression's value are used. If an expression cannot be evaluated
at assembly time then relocations will be generated in order to compute the
-value at link time.
+value at link time.
This directive does not apply any alignment before or after inserting the
values. As a result of this, if relocations are generated, they may be
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2126304..8e46038 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -161,8 +161,8 @@ automatically cause those extensions to be disabled.
@headitem Extension @tab Depends upon @tab Description
@item @code{aes} @tab @code{simd}
@tab Enable the AES and PMULL cryptographic extensions.
-@item @code{b16b16} @tab @code{sve2}
- @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
+@c @item @code{b16b16} @tab @code{sve2}
+@c @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
@item @code{bf16} @tab @code{fp}
@tab Enable BFloat16 extension.
@item @code{brbe} @tab
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 36ba825..952ddbc 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -219,6 +219,10 @@ accept various extension mnemonics. For example,
@code{avx10.1/128},
@code{user_msr},
@code{apx_f},
+@code{avx10.2},
+@code{avx10.2/512},
+@code{avx10.2/256},
+@code{avx10.2/128},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -270,7 +274,8 @@ accept various extension mnemonics. For example,
@code{snp},
@code{invlpgb},
@code{tlbsync},
-@code{svme} and
+@code{svme},
+@code{gmi} and
@code{padlock}.
Note that these extension mnemonics can be prefixed with @code{no} to revoke
the respective (and any dependent) functionality. Note further that the
@@ -463,6 +468,16 @@ R_X86_64_REX_GOTPCRELX, in 64-bit mode.
relocations. The default can be controlled by a configure option
@option{--enable-x86-relax-relocations}.
+@cindex @samp{-mtls-check=} option, i386
+@cindex @samp{-mtls-check=} option, x86-64
+@item -mtls-check=@var{no}
+@itemx -mtls-check=@var{yes}
+These options control whether the assembler check tls relocation.
+@option{-mtls-check=@var{yes}} will check tls relocation.
+@option{-mtls-check=@var{no}} will not check tls relocation
+The default can be controlled by a configure option
+@option{--enable-x86-tls-check}.
+
@cindex @samp{-malign-branch-boundary=} option, i386
@cindex @samp{-malign-branch-boundary=} option, x86-64
@item -malign-branch-boundary=@var{NUM}
@@ -1679,7 +1694,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
-@item @samp{.pbndkb} @tab @samp{.user_msr}
+@item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.avx10.2}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -1691,7 +1706,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
@item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
-@item @samp{.tlbsync} @tab @samp{.apx_f}
+@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi}
+
@end multitable
Apart from the warning, there are only two other effects on
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index f3c1f66..4181aa3 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -588,10 +588,12 @@ directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
@c FIXME! (1) reflect these options (next item too) in option summaries;
@c (2) stop teasing, say _which_ instructions expanded _how_.
@code{@value{AS}} automatically macro expands certain division and
-multiplication instructions to check for overflow and division by zero. This
-option causes @code{@value{AS}} to generate code to take a trap exception
-rather than a break exception when an error is detected. The trap instructions
-are only supported at Instruction Set Architecture level 2 and higher.
+multiplication instructions to check for overflow and division by zero.
+This option causes @code{@value{AS}} to generate code to take a trap
+exception rather than a break exception when an error is detected and the
+ISA selected for assembly at the originating place in source code permits
+the use of trap instructions. The trap instructions are only supported at
+Instruction Set Architecture level 2 and higher.
@item --break
@itemx --no-trap
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index d396669..44a1259 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -178,7 +178,12 @@ instead of just
It's not expected that options are changed in this manner during regular use,
but there are a handful of esoteric cases like the one above where users need
to disable particular features of the assembler for particular code sequences.
-The complete list of option arguments is shown below:
+However, it's also useful to enable/disable the extensions for some specific
+code regions by @samp{.option arch, +-}. This is very common in the ifunc
+libraries. We can support functions which are implemented by different
+extensions in the same library, but these should not affect any file-level
+settings, like the elf architecture attribute. The complete list of option
+arguments is shown below:
@table @code
@item push
@@ -437,11 +442,11 @@ instruction formats:
@multitable @columnfractions .15 .40
@item opcode7 @tab Unsigned immediate or opcode name for 7-bits opcode.
@item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
-@item func7 @tab Unsigned immediate for 7-bits function code.
-@item func6 @tab Unsigned immediate for 6-bits function code.
-@item func4 @tab Unsigned immediate for 4-bits function code.
-@item func3 @tab Unsigned immediate for 3-bits function code.
-@item func2 @tab Unsigned immediate for 2-bits function code.
+@item funct7 @tab Unsigned immediate for 7-bits function code.
+@item funct6 @tab Unsigned immediate for 6-bits function code.
+@item funct4 @tab Unsigned immediate for 4-bits function code.
+@item funct3 @tab Unsigned immediate for 3-bits function code.
+@item funct2 @tab Unsigned immediate for 2-bits function code.
@item rd @tab Destination register number for operand x, can be GPR or FPR.
@item rd' @tab Destination register number for operand x,
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
@@ -549,47 +554,47 @@ The following table lists the RISC-V instruction formats that are available
with the @samp{.insn} pseudo directive:
@table @code
-@item R type: .insn r opcode7, func3, func7, rd, rs1, rs2
+@item R type: .insn r opcode7, funct3, funct7, rd, rs1, rs2
@verbatim
-+-------+-----+-----+-------+----+---------+
-| func7 | rs2 | rs1 | func3 | rd | opcode7 |
-+-------+-----+-----+-------+----+---------+
-31 25 20 15 12 7 0
++--------+-----+-----+--------+----+---------+
+| funct7 | rs2 | rs1 | funct3 | rd | opcode7 |
++--------+-----+-----+--------+----+---------+
+31 25 20 15 12 7 0
@end verbatim
-@item R type with 4 register operands: .insn r opcode7, func3, func2, rd, rs1, rs2, rs3
-@itemx R4 type: .insn r4 opcode7, func3, func2, rd, rs1, rs2, rs3
+@item R type with 4 register operands: .insn r opcode7, funct3, funct2, rd, rs1, rs2, rs3
+@itemx R4 type: .insn r4 opcode7, funct3, funct2, rd, rs1, rs2, rs3
@verbatim
-+-----+-------+-----+-----+-------+----+---------+
-| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode7 |
-+-----+-------+-----+-----+-------+----+---------+
-31 27 25 20 15 12 7 0
++-----+--------+-----+-----+--------+----+---------+
+| rs3 | funct2 | rs2 | rs1 | funct3 | rd | opcode7 |
++-----+--------+-----+-----+--------+----+---------+
+31 27 25 20 15 12 7 0
@end verbatim
-@item I type: .insn i opcode7, func3, rd, rs1, simm12
-@itemx I type: .insn i opcode7, func3, rd, simm12(rs1)
+@item I type: .insn i opcode7, funct3, rd, rs1, simm12
+@itemx I type: .insn i opcode7, funct3, rd, simm12(rs1)
@verbatim
-+--------------+-----+-------+----+---------+
-| simm12[11:0] | rs1 | func3 | rd | opcode7 |
-+--------------+-----+-------+----+---------+
-31 20 15 12 7 0
++--------------+-----+--------+----+---------+
+| simm12[11:0] | rs1 | funct3 | rd | opcode7 |
++--------------+-----+--------+----+---------+
+31 20 15 12 7 0
@end verbatim
-@item S type: .insn s opcode7, func3, rs2, simm12(rs1)
+@item S type: .insn s opcode7, funct3, rs2, simm12(rs1)
@verbatim
-+--------------+-----+-----+-------+-------------+---------+
-| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode7 |
-+--------------+-----+-----+-------+-------------+---------+
-31 25 20 15 12 7 0
++--------------+-----+-----+--------+-------------+---------+
+| simm12[11:5] | rs2 | rs1 | funct3 | simm12[4:0] | opcode7 |
++--------------+-----+-----+--------+-------------+---------+
+31 25 20 15 12 7 0
@end verbatim
-@item B type: .insn s opcode7, func3, rs1, rs2, symbol
-@itemx SB type: .insn sb opcode7, func3, rs1, rs2, symbol
+@item B type: .insn s opcode7, funct3, rs1, rs2, symbol
+@itemx SB type: .insn sb opcode7, funct3, rs1, rs2, symbol
@verbatim
-+-----------------+-----+-----+-------+----------------+---------+
-| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode7 |
-+-----------------+-----+-----+-------+----------------+---------+
-31 25 20 15 12 7 0
++-----------------+-----+-----+--------+----------------+---------+
+| simm12[12|10:5] | rs2 | rs1 | funct3 | simm12[4:1|11] | opcode7 |
++-----------------+-----+-----+--------+----------------+---------+
+31 25 20 15 12 7 0
@end verbatim
@item U type: .insn u opcode7, rd, simm20
@@ -609,76 +614,76 @@ with the @samp{.insn} pseudo directive:
31 30 21 20 12 7 0
@end verbatim
-@item CR type: .insn cr opcode2, func4, rd, rs2
+@item CR type: .insn cr opcode2, funct4, rd, rs2
@verbatim
-+-------+--------+-----+---------+
-| func4 | rd/rs1 | rs2 | opcode2 |
-+-------+--------+-----+---------+
-15 12 7 2 0
++--------+--------+-----+---------+
+| funct4 | rd/rs1 | rs2 | opcode2 |
++--------+--------+-----+---------+
+15 12 7 2 0
@end verbatim
-@item CI type: .insn ci opcode2, func3, rd, simm6
+@item CI type: .insn ci opcode2, funct3, rd, simm6
@verbatim
-+-------+----------+--------+------------+---------+
-| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
-+-------+----------+--------+------------+---------+
-15 13 12 7 2 0
++--------+----------+--------+------------+---------+
+| funct3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
++--------+----------+--------+------------+---------+
+15 13 12 7 2 0
@end verbatim
-@item CIW type: .insn ciw opcode2, func3, rd', uimm8
+@item CIW type: .insn ciw opcode2, funct3, rd', uimm8
@verbatim
-+-------+------------+-----+---------+
-| func3 | uimm8[7:0] | rd' | opcode2 |
-+-------+-------- ---+-----+---------+
-15 13 5 2 0
++--------+------------+-----+---------+
+| funct3 | uimm8[7:0] | rd' | opcode2 |
++--------+-------- ---+-----+---------+
+15 13 5 2 0
@end verbatim
-@item CSS type: .insn css opcode2, func3, rd, uimm6
+@item CSS type: .insn css opcode2, funct3, rd, uimm6
@verbatim
-+-------+------------+----+---------+
-| func3 | uimm6[5:0] | rd | opcode2 |
-+-------+------------+----+---------+
-15 13 7 2 0
++--------+------------+----+---------+
+| funct3 | uimm6[5:0] | rd | opcode2 |
++--------+------------+----+---------+
+15 13 7 2 0
@end verbatim
-@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
+@item CL type: .insn cl opcode2, funct3, rd', uimm5(rs1')
@verbatim
-+-------+------------+------+------------+------+---------+
-| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 |
-+-------+------------+------+------------+------+---------+
-15 13 10 7 5 2 0
++--------+------------+------+------------+------+---------+
+| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 |
++--------+------------+------+------------+------+---------+
+15 13 10 7 5 2 0
@end verbatim
-@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
+@item CS type: .insn cs opcode2, funct3, rs2', uimm5(rs1')
@verbatim
-+-------+------------+------+------------+------+---------+
-| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
-+-------+------------+------+------------+------+---------+
-15 13 10 7 5 2 0
++--------+------------+------+------------+------+---------+
+| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
++--------+------------+------+------------+------+---------+
+15 13 10 7 5 2 0
@end verbatim
-@item CA type: .insn ca opcode2, func6, func2, rd', rs2'
+@item CA type: .insn ca opcode2, funct6, funct2, rd', rs2'
@verbatim
-+-- ----+----------+-------+------+---------+
-| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
-+-------+----------+-------+------+---------+
-15 10 7 5 2 0
++--------+----------+--------+------+---------+
+| funct6 | rd'/rs1' | funct2 | rs2' | opcode2 |
++--------+----------+--------+------+---------+
+15 10 7 5 2 0
@end verbatim
-@item CB type: .insn cb opcode2, func3, rs1', symbol
+@item CB type: .insn cb opcode2, funct3, rs1', symbol
@verbatim
-+-------+--------------+------+------------------+---------+
-| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
-+-------+--------------+------+------------------+---------+
-15 13 10 7 2 0
++--------+--------------+------+------------------+---------+
+| funct3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
++--------+--------------+------+------------------+---------+
+15 13 10 7 2 0
@end verbatim
-@item CJ type: .insn cj opcode2, func3, symbol
+@item CJ type: .insn cj opcode2, funct3, symbol
@verbatim
-+-------+-------------------------------+---------+
-| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
-+-------+-------------------------------+---------+
-15 13 2 0
++--------+-------------------------------+---------+
+| funct3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
++--------+-------------------------------+---------+
+15 13 2 0
@end verbatim
@@ -740,13 +745,18 @@ extensions supported and provides the location of their
publicly-released documentation:
@table @r
-@item XCvMac
-The XCvMac extension provides instructions for multiply-accumulate operations.
+@item XCvAlu
+The XCvAlu extension provides instructions for general ALU operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
-@item XCvAlu
-The XCvAlu extension provides instructions for general ALU operations.
+@item XCvBi
+The XCvBi extension provides instructions for branch immediate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
+@item XCvBitmanip
+The XCvBitmanip extension provides instructions for bitmanip operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
@@ -755,8 +765,8 @@ The XCvElw extension provides instructions for event load word operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
-@item XCvBi
-The XCvBi extension provides instructions for branch immediate operations.
+@item XCvMac
+The XCvMac extension provides instructions for multiply-accumulate operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
@@ -765,6 +775,11 @@ The XCvMem extension provides instructions for post inc load/store operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+@item XcvSimd
+The XcvSimd extension provides instructions for SIMD operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi
index f73dfde..9a4fdfe 100644
--- a/gas/doc/c-s390.texi
+++ b/gas/doc/c-s390.texi
@@ -18,7 +18,7 @@ and eleven chip levels. The architecture modes are the Enterprise System
Architecture (ESA) and the newer z/Architecture mode. The chip levels
are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
-(or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14).
+(or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or arch15.
@menu
* s390 Options:: Command-line Options.
@@ -71,8 +71,9 @@ are recognized:
@code{zEC12} (or @code{arch10}),
@code{z13} (or @code{arch11}),
@code{z14} (or @code{arch12}),
-@code{z15} (or @code{arch13}), and
-@code{z16} (or @code{arch14}).
+@code{z15} (or @code{arch13}),
+@code{z16} (or @code{arch14}), and
+@code{arch15}.
Assembling an instruction that is not supported on the target
processor results in an error message.
@@ -300,10 +301,11 @@ field. The notation changes as follows:
@display
@multitable @columnfractions 0.30 0.30
@headitem full notation @tab short notation
-@item Dn(0,Bn) @tab Dn(Bn)
+@item Dn(Xn,0) @tab Dn(Xn,)
+@item Dn(0,Bn) @tab Dn(,Bn) or Dn(Bn)
@item Dn(0,0) @tab Dn
@item Dn(0) @tab Dn
-@item Dn(Ln,0) @tab Dn(Ln)
+@item Dn(Ln,0) @tab Dn(Ln,) or Dn(Ln)
@end multitable
@end display
diff --git a/gas/doc/internals.texi b/gas/doc/internals.texi
index e59d676..18fca0e 100644
--- a/gas/doc/internals.texi
+++ b/gas/doc/internals.texi
@@ -814,7 +814,7 @@ zero if the target is little endian.
@cindex md_show_usage
@cindex md_after_parse_args
GAS uses these variables and functions during option processing.
-@code{md_shortopts} is a @code{const char *} which GAS adds to the machine
+@code{md_shortopts} is a @code{const char []} which GAS adds to the machine
independent string passed to @code{getopt}. @code{md_longopts} is a
@code{struct option []} which GAS adds to the machine independent long options
passed to @code{getopt}; you may use @code{OPTION_MD_BASE}, defined in
generated by cgit v1.1 at 2024-11-04 23:10:35 +0000