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Diffstat (limited to 'gas/doc/c-arc.texi')
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1 files changed, 306 insertions, 223 deletions
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi index 9fa28e5..f72ecae 100644 --- a/gas/doc/c-arc.texi +++ b/gas/doc/c-arc.texi @@ -19,52 +19,54 @@ @menu * ARC Options:: Options * ARC Syntax:: Syntax -* ARC Floating Point:: Floating Point * ARC Directives:: ARC Machine Directives +* ARC Modifiers:: ARC Assembler Modifiers +* ARC Symbols:: ARC Pre-defined Symbols * ARC Opcodes:: Opcodes @end menu - @node ARC Options @section Options -@cindex ARC options (none) -@cindex options for ARC (none) +@cindex ARC options +@cindex options for ARC + +The following options control the type of CPU for which code is +assembled, and generic constraints on the code generated: @table @code -@cindex @code{-marc[5|6|7|8]} command line option, ARC -@item -marc[5|6|7|8] -This option selects the core processor variant. Using -@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which -is also the default. +@item -mcpu=@var{cpu} +@cindex @code{-mcpu=@var{cpu}} command line option, ARC +Set architecture type and register usage for @var{cpu}. There are +also shortcut alias options available for backward compatibility and +convenience. Supported values for @var{cpu} are @table @code +@cindex @code{mA6} command line option, ARC +@cindex @code{marc600} command line option, ARC +@item arc600 +Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}. -@cindex @code{arc5} arc5, ARC -@item arc5 -Base instruction set. +@item arc601 +@cindex @code{mARC601} command line option, ARC +Assemble for ARC 601. Alias: @code{-mARC601}. -@cindex @code{arc6} arc6, ARC -@item arc6 -Jump-and-link (jl) instruction. No requirement of an instruction between -setting flags and conditional jump. For example: +@item arc700 +@cindex @code{mA7} command line option, ARC +@cindex @code{mARC700} command line option, ARC +Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}. -@smallexample - mov.f r0,r1 - beq foo -@end smallexample +@item arcem +@cindex @code{mEM} command line option, ARC +Assemble for ARC EM. Aliases: @code{-mEM} -@cindex @code{arc7} arc7, ARC -@item arc7 -Break (brk) and sleep (sleep) instructions. - -@cindex @code{arc8} arc8, ARC -@item arc8 -Software interrupt (swi) instruction. +@item archs +@cindex @code{mHS} command line option, ARC +Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}. @end table -Note: the @code{.option} directive can to be used to select a core +Note: the @code{.cpu} directive can to be used to select a core variant from within assembly code. @cindex @code{-EB} command line option, ARC @@ -78,6 +80,11 @@ This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default. +@cindex @code{-mcode-density} command line option, ARC +@item -mcode-density +This option turns on Code Density instructions. Only valid for ARC EM +processors. + @end table @node ARC Syntax @@ -90,36 +97,211 @@ default. @node ARC-Chars @subsection Special Characters +@table @code +@item % +@cindex register name prefix character, ARC +@cindex ARC register name prefix character +A register name can optionally be prefixed by a @samp{%} character. So +register @code{%r0} is equivalent to @code{r0} in the assembly code. + +@item # @cindex line comment character, ARC @cindex ARC line comment character -The presence of a @samp{#} on a line indicates the start of a comment -that extends to the end of the current line. Note that if a line -starts with a @samp{#} character then it can also be a logical line -number directive (@pxref{Comments}) or a preprocessor -control command (@pxref{Preprocessing}). - +The presence of a @samp{#} character within a line (but not at the +start of a line) indicates the start of a comment that extends to the +end of the current line. + +@emph{Note:} if a line starts with a @samp{#} character then it can +also be a logical line number directive (@pxref{Comments}) or a +preprocessor control command (@pxref{Preprocessing}). + +@item @@ +@cindex symbol prefix character, ARC +@cindex ARC symbol prefix character +Prefixing an operand with an @samp{@@} specifies that the operand is a +symbol and not a register. This is how the assembler disambiguates +the use of an ARC register name as a symbol. So the instruction +@example +mov r0, @@r0 +@end example +moves the address of symbol @code{r0} into register @code{r0}. + +@item ` @cindex line separator, ARC @cindex statement separator, ARC @cindex ARC line separator -The ARC assembler does not support a line separator character. +The @samp{`} (backtick) character is used to separate statements on a +single line. + +@cindex line +@item - +@cindex C preprocessor macro separator, ARC +@cindex ARC C preprocessor macro separator +Used as a separator to obtain a sequence of commands from a C +preprocessor macro. + +@end table @node ARC-Regs @subsection Register Names @cindex ARC register names @cindex register names, ARC -*TODO* +The ARC assembler uses the following register names for its core +registers: + +@table @code +@item r0-r31 +@cindex core general registers, ARC +@cindex ARC core general registers +The core general registers. Registers @code{r26} through @code{r31} +have special functions, and are usually referred to by those synonyms. + +@item gp +@cindex global pointer, ARC +@cindex ARC global pointer +The global pointer and a synonym for @code{r26}. + +@item fp +@cindex frame pointer, ARC +@cindex ARC frame pointer +The frame pointer and a synonym for @code{r27}. + +@item sp +@cindex stack pointer, ARC +@cindex ARC stack pointer +The stack pointer and a synonym for @code{r28}. + +@item ilink1 +@cindex level 1 interrupt link register, ARC +@cindex ARC level 1 interrupt link register +For ARC 600 and ARC 700, the level 1 interrupt link register and a +synonym for @code{r29}. Not supported for ARCv2. + +@item ilink +@cindex interrupt link register, ARC +@cindex ARC interrupt link register +For ARCv2, the interrupt link register and a synonym for @code{r29}. +Not supported for ARC 600 and ARC 700. + +@item ilink2 +@cindex level 2 interrupt link register, ARC +@cindex ARC level 2 interrupt link register +For ARC 600 and ARC 700, the level 2 interrupt link register and a +synonym for @code{r30}. Not supported for ARC v2. + +@item blink +@cindex link register, ARC +@cindex ARC link register +The link register and a synonym for @code{r31}. + +@item r32-r59 +@cindex extension core registers, ARC +@cindex ARC extension core registers +The extension core registers. + +@item lp_count +@cindex loop counter, ARC +@cindex ARC loop counter +The loop count register. + +@item pcl +@cindex word aligned program counter, ARC +@cindex ARC word aligned program counter +The word aligned program counter. + +@end table +In addition the ARC processor has a large number of @emph{auxiliary +registers}. The precise set depends on the extensions being +supported, but the following baseline set are always defined: -@node ARC Floating Point -@section Floating Point +@table @code +@item identity +@cindex Processor Identification register, ARC +@cindex ARC Processor Identification register +Processor Identification register. Auxiliary register address 0x4. + +@item pc +@cindex Program Counter, ARC +@cindex ARC Program Counter +Program Counter. Auxiliary register address 0x6. + +@item status32 +@cindex Status register, ARC +@cindex ARC Status register +Status register. Auxiliary register address 0x0a. + +@item bta +@cindex Branch Target Address, ARC +@cindex ARC Branch Target Address +Branch Target Address. Auxiliary register address 0x412. + +@item ecr +@cindex Exception Cause Register, ARC +@cindex ARC Exception Cause Register +Exception Cause Register. Auxiliary register address 0x403. + +@item int_vector_base +@cindex Interrupt Vector Base address, ARC +@cindex ARC Interrupt Vector Base address +Interrupt Vector Base address. Auxiliary register address 0x25. + +@item status32_p0 +@cindex Stored STATUS32 register on entry to level P0 interrupts, ARC +@cindex ARC Stored STATUS32 register on entry to level P0 interrupts +Stored STATUS32 register on entry to level P0 interrupts. Auxiliary +register address 0xb. + +@item aux_user_sp +@cindex Saved User Stack Pointer, ARC +@cindex ARC Saved User Stack Pointer +Saved User Stack Pointer. Auxiliary register address 0xd. + +@item eret +@cindex Exception Return Address, ARC +@cindex ARC Exception Return Address +Exception Return Address. Auxiliary register address 0x400. + +@item erbta +@cindex BTA saved on exception entry, ARC +@cindex ARC BTA saved on exception entry +BTA saved on exception entry. Auxiliary register address 0x401. + +@item erstatus +@cindex STATUS32 saved on exception, ARC +@cindex ARC STATUS32 saved on exception +STATUS32 saved on exception. Auxiliary register address 0x402. + +@item bcr_ver +@cindex Build Configuration Registers Version, ARC +@cindex ARC Build Configuration Registers Version +Build Configuration Registers Version. Auxiliary register address 0x60. + +@item bta_link_build +@cindex Build configuration for: BTA Registers, ARC +@cindex ARC Build configuration for: BTA Registers +Build configuration for: BTA Registers. Auxiliary register address 0x63. + +@item vecbase_ac_build +@cindex Build configuration for: Interrupts, ARC +@cindex ARC Build configuration for: Interrupts +Build configuration for: Interrupts. Auxiliary register address 0x68. + +@item rf_build +@cindex Build configuration for: Core Registers, ARC +@cindex ARC Build configuration for: Core Registers +Build configuration for: Core Registers. Auxiliary register address 0x6e. + +@item dccm_build +@cindex DCCM RAM Configuration Register, ARC +@cindex ARC DCCM RAM Configuration Register +DCCM RAM Configuration Register. Auxiliary register address 0xc1. -@cindex floating point, ARC (@sc{ieee}) -@cindex ARC floating point (@sc{ieee}) -The ARC core does not currently have hardware floating point -support. Software floating point support is provided by @code{GCC} -and uses @sc{ieee} floating-point numbers. +@end table +Additional auxiliary register names are defined according to the +processor architecture version and extensions selected by the options. @node ARC Directives @section ARC Machine Directives @@ -131,205 +313,106 @@ machine directives: @table @code -@cindex @code{2byte} directive, ARC -@item .2byte @var{expressions} -*TODO* - -@cindex @code{3byte} directive, ARC -@item .3byte @var{expressions} -*TODO* - -@cindex @code{4byte} directive, ARC -@item .4byte @var{expressions} -*TODO* - -@cindex @code{extAuxRegister} directive, ARC -@item .extAuxRegister @var{name},@var{address},@var{mode} -The ARCtangent A4 has extensible auxiliary register space. The -auxiliary registers can be defined in the assembler source code by -using this directive. The first parameter is the @var{name} of the -new auxiallry register. The second parameter is the @var{address} of -the register in the auxiliary register memory map for the variant of -the ARC. The third parameter specifies the @var{mode} in which the -register can be operated is and it can be one of: - +@cindex @code{lcomm} directive +@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] +Reserve @var{length} (an absolute expression) bytes for a local common +denoted by @var{symbol}. The section and value of @var{symbol} are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. Since +@var{symbol} is not declared global, it is normally not visible to +@code{@value{LD}}. The optional third parameter, @var{alignment}, +specifies the desired alignment of the symbol in the bss section, +specified as a byte boundary (for example, an alignment of 16 means +that the least significant 4 bits of the address should be zero). The +alignment must be an absolute expression, and it must be a power of +two. If no alignment is specified, as will set the alignment to the +largest power of two less than or equal to the size of the symbol, up +to a maximum of 16. + +@cindex @code{lcommon} directive +@item .lcommon @var{symbol} , @var{length}[, @var{alignment}] +The same as @code{lcomm} directive. + +@cindex @code{cpu} directive, ARC +@cindex @code{cpu} directive, ARC +The @code{.cpu} directive must be followed by the desired core +version. Permitted values for CPU are: @table @code -@item r (readonly) -@item w (write only) -@item r|w (read or write) -@end table - -For example: - -@smallexample - .extAuxRegister mulhi,0x12,w -@end smallexample +@item ARC600 +Assemble for the ARC600 instruction set. -This specifies an extension auxiliary register called @emph{mulhi} -which is at address 0x12 in the memory space and which is only -writable. +@item ARC700 +Assemble for the ARC700 instruction set. -@cindex @code{extCondCode} directive, ARC -@item .extCondCode @var{suffix},@var{value} -The condition codes on the ARCtangent A4 are extensible and can be -specified by means of this assembler directive. They are specified -by the suffix and the value for the condition code. They can be used to -specify extra condition codes with any values. For example: +@item EM +Assemble for the ARC EM instruction set. -@smallexample - .extCondCode is_busy,0x14 +@item HS +Assemble for the ARC HS instruction set. - add.is_busy r1,r2,r3 - bis_busy _main -@end smallexample - -@cindex @code{extCoreRegister} directive, ARC -@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} -Specifies an extension core register @var{name} for the application. -This allows a register @var{name} with a valid @var{regnum} between 0 -and 60, with the following as valid values for @var{mode} - -@table @samp -@item @emph{r} (readonly) -@item @emph{w} (write only) -@item @emph{r|w} (read or write) @end table - -The other parameter gives a description of the register having a -@var{shortcut} in the pipeline. The valid values are: - -@table @code -@item can_shortcut -@item cannot_shortcut +Note: the @code{.cpu} directive overrides the command line option +@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not +consistent between the two. @end table -For example: - -@smallexample - .extCoreRegister mlo,57,r,can_shortcut -@end smallexample - -This defines an extension core register mlo with the value 57 which -can shortcut the pipeline. - -@cindex @code{extInstruction} directive, ARC -@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass} -The ARCtangent A4 allows the user to specify extension instructions. -The extension instructions are not macros. The assembler creates -encodings for use of these instructions according to the specification -by the user. The parameters are: - -@itemize @bullet -@item @var{name} -Name of the extension instruction - -@item @var{opcode} -Opcode to be used. (Bits 27:31 in the encoding). Valid values -0x10-0x1f or 0x03 +@node ARC Modifiers +@section ARC Assembler Modifiers -@item @var{subopcode} -Subopcode to be used. Valid values are from 0x09-0x3f. However the -correct value also depends on @var{syntaxclass} - -@item @var{suffixclass} -Determines the kinds of suffixes to be allowed. Valid values are -@code{SUFFIX_NONE}, @code{SUFFIX_COND}, -@code{SUFFIX_FLAG} which indicates the absence or presence of -conditional suffixes and flag setting by the extension instruction. -It is also possible to specify that an instruction sets the flags and -is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}. - -@item @var{syntaxclass} -Determines the syntax class for the instruction. It can have the -following values: +The following additional assembler modifiers have been added for +position-independent code. These modifiers are available only with +the ARC 700 and above processors and generate relocation entries, +which are interpreted by the linker as follows: @table @code -@item @code{SYNTAX_2OP}: -2 Operand Instruction -@item @code{SYNTAX_3OP}: -3 Operand Instruction -@end table - -In addition there could be modifiers for the syntax class as described -below: - -@itemize @minus -Syntax Class Modifiers are: - -@item @code{OP1_MUST_BE_IMM}: -Modifies syntax class SYNTAX_3OP, specifying that the first operand -of a three-operand instruction must be an immediate (i.e., the result -is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with -SYNTAX_3OP as given in the example below. This could usually be used -to set the flags using specific instructions and not retain results. +@item @@pcl(@var{symbol}) +@cindex @@pcl(@var{symbol}), ARC modifier +Relative distance of @var{symbol}'s from the current program counter +location. + +@item @@gotpc(@var{symbol}) +@cindex @@gotpc(@var{symbol}), ARC modifier +Relative distance of @var{symbol}'s Global Offset Table entry from the +current program counter location. + +@item @@gotoff(@var{symbol}) +@cindex @@gotoff(@var{symbol}), ARC modifier +Distance of @var{symbol} from the base of the Global Offset Table. + +@item @@plt(@var{symbol}) +@cindex @@plt(@var{symbol}), ARC modifier +Distance of @var{symbol}'s Procedure Linkage Table entry from the +current program counter. This is valid only with branch and link +instructions and PC-relative calls. + +@item @@sda(@var{symbol}) +@cindex @@sda(@var{symbol}), ARC modifier +Relative distance of @var{symbol} from the base of the Small Data +Pointer. -@item @code{OP1_IMM_IMPLIED}: -Modifies syntax class SYNTAX_20P, it specifies that there is an -implied immediate destination operand which does not appear in the -syntax. For example, if the source code contains an instruction like: - -@smallexample -inst r1,r2 -@end smallexample - -it really means that the first argument is an implied immediate (that -is, the result is discarded). This is the same as though the source -code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it -with SYNTAX_20P. - -@end itemize -@end itemize - -For example, defining 64-bit multiplier with immediate operands: - -@smallexample -.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , - SYNTAX_3OP|OP1_MUST_BE_IMM -@end smallexample - -The above specifies an extension instruction called mp64 which has 3 operands, -sets the flags, can be used with a condition code, for which the -first operand is an immediate. (Equivalent to discarding the result -of the operation). - -@smallexample - .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED -@end smallexample - -This describes a 2 operand instruction with an implicit first -immediate operand. The result of this operation would be discarded. - -@cindex @code{half} directive, ARC -@item .half @var{expressions} -*TODO* - -@cindex @code{long} directive, ARC -@item .long @var{expressions} -*TODO* +@end table -@cindex @code{option} directive, ARC -@item .option @var{arc|arc5|arc6|arc7|arc8} -The @code{.option} directive must be followed by the desired core -version. Again @code{arc} is an alias for -@code{arc@value{ARC_CORE_DEFAULT}}. +@node ARC Symbols +@section ARC Pre-defined Symbols -Note: the @code{.option} directive overrides the command line option -@code{-marc}; a warning is emitted when the version is not consistent -between the two - even for the implicit default core version -(arc@value{ARC_CORE_DEFAULT}). +The following assembler symbols will prove useful when developing +position-independent code. These symbols are available only with the +ARC 700 and above processors. -@cindex @code{short} directive, ARC -@item .short @var{expressions} -*TODO* +@table @code +@item __GLOBAL_OFFSET_TABLE__ +@cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol +Symbol referring to the base of the Global Offset Table. -@cindex @code{word} directive, ARC -@item .word @var{expressions} -*TODO* +@item __DYNAMIC__ +@cindex __DYNAMIC__, ARC pre-defined symbol +An alias for the Global Offset Table +@code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with +@code{@@gotpc} modifiers. @end table - @node ARC Opcodes @section Opcodes @@ -337,4 +420,4 @@ between the two - even for the implicit default core version @cindex opcodes for ARC For information on the ARC instruction set, see @cite{ARC Programmers -Reference Manual}, ARC International (www.arc.com) +Reference Manual}, available where you download the processor IP library. |