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-rw-r--r--binutils/doc/binutils.texi11
1 files changed, 8 insertions, 3 deletions
diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 5bf5d80..c74526e 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2146,9 +2146,6 @@ Sets the section alignment field in the PE header - if one is present
in the binary. Sections in memory will always begin at addresses
which are a multiple of this number. Defaults to 0x1000.
-Note - this option will also set the alignment field in each section's
-flags.
-
Note - if a section's LMA or VMA addresses are no longer aligned, and
those addresses have not been set via the @option{--set-section-lma} or
@option{--set-section-vma} options, and the file has been fully
@@ -2704,6 +2701,14 @@ but the result again may not be as you expect.
For RISC-V, the following options are supported:
@table @code
+@item max
+Disassemble without checking architecture string. This is a best effort mode, so
+for overlapping ISA extensions the first match (possibly incorrect in a given
+context) will be used to decode the instruction. It's useful, if the ELF file
+doesn't expose ISA string, preventing automatic ISA subset deduction, and the
+default fallback ISA string (@code{rv64gc}) doesn't cover all instructions in
+the binary.
+
@item numeric
Print numeric register names, rather than ABI names (e.g., print @code{x2}
instead of @code{sp}).