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-rw-r--r--bfd/.Sanitize28
-rw-r--r--bfd/ChangeLog9
-rw-r--r--bfd/archures.c12
-rw-r--r--bfd/bfd-in2.h3
-rw-r--r--bfd/cpu-mips.c8
-rw-r--r--bfd/elf32-mips.c11
-rw-r--r--gas/ChangeLog9
-rw-r--r--gas/config/tc-mips.c57
-rw-r--r--include/elf/.Sanitize28
-rw-r--r--include/elf/ChangeLog10
-rw-r--r--include/elf/mips.h7
-rw-r--r--include/opcode/.Sanitize29
-rw-r--r--opcodes/.Sanitize28
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/mips-dis.c28
-rw-r--r--sim/mips/.Sanitize30
-rw-r--r--sim/mips/ChangeLog7
-rwxr-xr-xsim/mips/configure2
-rw-r--r--sim/mips/configure.in2
-rw-r--r--sim/mips/mips.igen505
-rw-r--r--sim/mips/vr.igen287
21 files changed, 1017 insertions, 90 deletions
diff --git a/bfd/.Sanitize b/bfd/.Sanitize
index 814730e..cd40980 100644
--- a/bfd/.Sanitize
+++ b/bfd/.Sanitize
@@ -523,6 +523,34 @@ else
done
fi
+vr4xxx_files="ChangeLog archures.c bfd-in2.h cpu-mips.c elf32-mips.c"
+if ( echo $* | grep keep\-vr4xxx > /dev/null ) ; then
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Keeping vr4xxx stuff in $i
+ fi
+ fi
+ done
+else
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Removing traces of \"vr4xxx\" from $i...
+ fi
+ cp $i new
+ sed '/start\-sanitize\-vr4xxx/,/end-\sanitize\-vr4xxx/d' < $i > new
+ if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+ if [ -n "${verbose}" ] ; then
+ echo Caching $i in .Recover...
+ fi
+ mv $i .Recover
+ fi
+ mv new $i
+ fi
+ done
+fi
+
m32rx_files="ChangeLog ChangeLog-9697 archures.c bfd-in2.h elf32-m32r.c cpu-m32r.c"
if ( echo $* | grep keep\-m32rx > /dev/null ) ; then
for i in $m32rx_files ; do
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 2bb391a..4b4fabd 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,12 @@
+start-sanitize-vr4xxx
+1998-12-13 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * archures.c,bfd-in2.h (bfd_mach_mips4121): New.
+ * cpu-mips.c: Added vr4121.
+ * elf32-mips.c (elf_mips_mach): Same.
+ (_bfd_mips_elf_final_write_processing): Same.
+
+start-sanitize-vr4xxx
1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
* elf32-mips.c (_bfd_mips_elf_final_write_processing):
diff --git a/bfd/archures.c b/bfd/archures.c
index c3ac243..179f8d8 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -120,6 +120,9 @@ DESCRIPTION
.#define bfd_mach_mips4000 4000
.#define bfd_mach_mips4010 4010
.#define bfd_mach_mips4100 4100
+. {* start-sanitize-vr4xxx *}
+.#define bfd_mach_mips4121 4121
+. {* end-sanitize-vr4xxx *}
.#define bfd_mach_mips4300 4300
.#define bfd_mach_mips4400 4400
.#define bfd_mach_mips4600 4600
@@ -131,7 +134,7 @@ DESCRIPTION
.#define bfd_mach_mips4900 4900
. {* end-sanitize-tx49 *}
.#define bfd_mach_mips5000 5000
-. {* start-sanitize-cygnus *} {* CYGNUS LOCAL vr5400/raeburn *}
+. {* start-sanitize-cygnus *}
.#define bfd_mach_mips5400 5400
. {* end-sanitize-cygnus *}
. {* start-sanitize-r5900 *}
@@ -179,6 +182,9 @@ DESCRIPTION
.#define bfd_mach_sh3e 0x3e
.#define bfd_mach_sh4 0x40
. bfd_arch_alpha, {* Dec Alpha *}
+.#define bfd_mach_alpha_ev4 0x10
+.#define bfd_mach_alpha_ev5 0x20
+.#define bfd_mach_alpha_ev6 0x30
. bfd_arch_arm, {* Advanced Risc Machines ARM *}
.#define bfd_mach_arm_2 1
.#define bfd_mach_arm_2a 2
@@ -211,6 +217,8 @@ DESCRIPTION
. {* start-sanitize-am33 *}
.#define bfd_mach_am33 330
. {* end-sanitize-am33 *}
+. bfd_arch_fr30,
+.#define bfd_mach_fr30 0x46523330
. bfd_arch_last
. };
@@ -281,6 +289,7 @@ extern const bfd_arch_info_type bfd_z8k_arch;
extern const bfd_arch_info_type bfd_ns32k_arch;
extern const bfd_arch_info_type bfd_w65_arch;
extern const bfd_arch_info_type bfd_v850_arch;
+extern const bfd_arch_info_type bfd_fr30_arch;
static const bfd_arch_info_type * const bfd_archures_list[] =
{
@@ -319,6 +328,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_ns32k_arch,
&bfd_w65_arch,
&bfd_v850_arch,
+ & bfd_fr30_arch,
#endif
0
};
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 3fa4b78..99f2d7e 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1257,6 +1257,9 @@ enum bfd_architecture
#define bfd_mach_mips4000 4000
#define bfd_mach_mips4010 4010
#define bfd_mach_mips4100 4100
+ /* start-sanitize-vr4xxx */
+#define bfd_mach_mips4121 4121
+ /* end-sanitize-vr4xxx */
#define bfd_mach_mips4300 4300
#define bfd_mach_mips4400 4400
#define bfd_mach_mips4600 4600
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index db9c948..d5b1a50 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -44,6 +44,9 @@ I_mips3900,
I_mips4000,
I_mips4010,
I_mips4100,
+ /* start-sanitize-vr4xxx */
+I_mips4121,
+ /* end-sanitize-vr4xxx */
I_mips4300,
I_mips4400,
I_mips4600,
@@ -62,7 +65,6 @@ I_mips4320,
I_mips4900,
/* end-sanitize-tx49 */
/* start-sanitize-cygnus */
- /* CYGNUS LOCAL vr5400/raeburn */
I_mips5400,
/* end-sanitize-cygnus */
/* start-sanitize-r5900 */
@@ -87,6 +89,9 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
N (64, 64, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
+ /* start-sanitize-vr4xxx */
+ N (64, 64, bfd_mach_mips4121, "mips:4121", false, NN(I_mips4121)),
+ /* end-sanitize-vr4xxx */
N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
@@ -106,7 +111,6 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips4900, "mips:4900", false, NN(I_mips4900)),
/* end-sanitize-tx49 */
/* start-sanitize-cygnus */
- /* CYGNUS LOCAL vr5400/raeburn */
N (64, 64, bfd_mach_mips5400, "mips:5400", false, NN(I_mips5400)),
/* end-sanitize-cygnus */
/* start-sanitize-r5900 */
diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c
index 08f71ab..70d12a9 100644
--- a/bfd/elf32-mips.c
+++ b/bfd/elf32-mips.c
@@ -1662,6 +1662,11 @@ elf_mips_mach (flags)
case E_MIPS_MACH_4100:
return bfd_mach_mips4100;
+ /* start-sanitize-vr4xxx */
+
+ case E_MIPS_MACH_4121:
+ return bfd_mach_mips4121;
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
case E_MIPS_MACH_4320:
@@ -2104,6 +2109,12 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
case bfd_mach_mips4100:
val = E_MIPS_ARCH_3 | E_MIPS_MACH_4100;
break;
+ /* start-sanitize-vr4xxx */
+
+ case bfd_mach_mips4121:
+ val = E_MIPS_ARCH_3 | E_MIPS_MACH_4121;
+ break;
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
case bfd_mach_mips4320:
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c998a14..25a6250 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,4 +1,11 @@
-1998-12-11 Ken Raeburn <raeburn@cygnus.com>
+start-sanitize-vr4xxx
+1998-12-13 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * config/tc-mips.c (mips_4121): New.
+ (md_begin,mips_ip,md_longopts,md_parse_option): Add vr4121.
+
+end-sanitize-vr4xxx
+98-12-11 Ken Raeburn <raeburn@cygnus.com>
* config/tc-h8300.c (build_bytes): Change message given if the
instruction requires H8/300H mode and we're not in Hmode, to
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index ea96c84..1b455df6 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -207,6 +207,11 @@ static int mips_4010 = -1;
/* Whether the 4100 MADD16 and DMADD16 are permitted. */
static int mips_4100 = -1;
+/* start-sanitize-vr4xxx */
+/* Whether NEC 4121 instructions are permitted. */
+static int mips_4121 = -1;
+
+/* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
/* Whether NEC vr4320 instructions are permitted. */
static int mips_4320 = -1;
@@ -947,6 +952,12 @@ md_begin ()
else if (strcmp (cpu, "mips64vr4100") == 0)
mips_cpu = 4100;
+ /* start-sanitize-vr4xxx */
+ else if (strcmp (cpu, "vr4121") == 0
+ || strcmp (cpu, "mips64vr4121") == 0)
+ mips_cpu = 4121;
+
+ /* end-sanitize-vr4xxx */
else if (strcmp (cpu, "r4010") == 0)
mips_cpu = 4010;
@@ -997,6 +1008,9 @@ md_begin ()
else if (mips_cpu == 4000
|| mips_cpu == 4100
+ /* start-sanitize-vr4xxx */
+ || mips_cpu == 4121
+ /* end-sanitize-vr4xxx */
|| mips_cpu == 4400
|| mips_cpu == 4300
/* start-sanitize-vr4320 */
@@ -1041,6 +1055,11 @@ md_begin ()
if (mips_4100 < 0)
mips_4100 = (mips_cpu == 4100);
+ /* start-sanitize-vr4xxx */
+ if (mips_4121 < 0)
+ mips_4121 = (mips_cpu == 4121);
+
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
if (mips_4320 < 0)
mips_4320 = (mips_cpu == 4320);
@@ -2595,6 +2614,10 @@ macro_build (place, counter, ep, name, fmt, va_alist)
&& (insn.insn_mo->membership & INSN_4010) != 0)
|| (mips_4100
&& (insn.insn_mo->membership & INSN_4100) != 0)
+ /* start-sanitize-vr4xxx */
+ || (mips_4121
+ && (insn.insn_mo->membership & INSN_4121) != 0)
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
|| (mips_4320
&& (insn.insn_mo->membership & INSN_4320) != 0)
@@ -7264,6 +7287,9 @@ mips_ip (str, ip)
else if ((mips_4650 && (insn->membership & INSN_4650) != 0)
|| (mips_4010 && (insn->membership & INSN_4010) != 0)
|| (mips_4100 && (insn->membership & INSN_4100) != 0)
+ /* start-sanitize-vr4xxx */
+ || (mips_4121 && (insn->membership & INSN_4121) != 0)
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
|| (mips_4320 && (insn->membership & INSN_4320) != 0)
/* end-sanitize-vr4320 */
@@ -9424,6 +9450,14 @@ struct option md_longopts[] = {
#define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35)
{"no-fix-4011-branch-bug", no_argument, NULL, OPTION_NO_FIX_4011_BRANCH_BUG},
/* end-sanitize-branchbug4011 */
+
+ /* start-sanitize-vr4xxx */
+#define OPTION_M4121 (OPTION_MD_BASE + 36)
+ {"m4121", no_argument, NULL, OPTION_M4121},
+#define OPTION_NO_M4121 (OPTION_MD_BASE + 37)
+ {"no-m4121", no_argument, NULL, OPTION_NO_M4121},
+
+ /* end-sanitize-vr4xxx */
#define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
#define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
#define OPTION_XGOT (OPTION_MD_BASE + 19)
@@ -9561,6 +9595,10 @@ md_parse_option (c, arg)
mips_cpu = 4000;
else if (strcmp (p, "4100") == 0)
mips_cpu = 4100;
+ /* start-sanitize-vr4xxx */
+ else if (strcmp (p, "4121") == 0)
+ mips_cpu = 4121;
+ /* end-sanitize-vr4xxx */
else if (strcmp (p, "4300") == 0)
mips_cpu = 4300;
/* start-sanitize-vr4320 */
@@ -9619,6 +9657,9 @@ md_parse_option (c, arg)
if (sv
&& (mips_cpu != 4300
&& mips_cpu != 4100
+ /* start-sanitize-vr4xxx */
+ && mips_cpu != 4121
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
&& mips_cpu != 4320
/* end-sanitize-vr4320 */
@@ -9664,6 +9705,16 @@ md_parse_option (c, arg)
mips_4100 = 0;
break;
+ /* start-sanitize-vr4xxx */
+ case OPTION_M4121:
+ mips_4121 = 1;
+ break;
+
+ case OPTION_NO_M4121:
+ mips_4121 = 0;
+ break;
+
+ /* end-sanitize-vr4xxx */
/* start-sanitize-r5900 */
case OPTION_M5900:
mips_5900 = 1;
@@ -9846,6 +9897,12 @@ MIPS options:\n\
-no-m4010 do not permit R4010 instructions\n\
-m4100 permit VR4100 instructions\n\
-no-m4100 do not permit VR4100 instructions\n"));
+ /* start-sanitize-vr4xxx */
+ fprintf(stream, _("\
+-mcpu=vr4121 generate code for vr4121\n\
+-m4121 permit VR4121 instructions\n\
+-no-m4121 do not permit VR4121 instructions\n"));
+ /* end-sanitize-vr4xxx */
fprintf(stream, _("\
-mips16 generate mips16 instructions\n\
-no-mips16 do not generate mips16 instructions\n"));
diff --git a/include/elf/.Sanitize b/include/elf/.Sanitize
index b14ebd7..f2a44e7 100644
--- a/include/elf/.Sanitize
+++ b/include/elf/.Sanitize
@@ -192,6 +192,34 @@ else
done
fi
+vr4xxx_files="ChangeLog mips.h"
+if ( echo $* | grep keep\-vr4xxx > /dev/null ) ; then
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Keeping vr4xxx stuff in $i
+ fi
+ fi
+ done
+else
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Removing traces of \"vr4xxx\" from $i...
+ fi
+ cp $i new
+ sed '/start\-sanitize\-vr4xxx/,/end-\sanitize\-vr4xxx/d' < $i > new
+ if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+ if [ -n "${verbose}" ] ; then
+ echo Caching $i in .Recover...
+ fi
+ mv $i .Recover
+ fi
+ mv new $i
+ fi
+ done
+fi
+
tx49_files="mips.h"
if ( echo $* | grep keep\-tx49 > /dev/null ) ; then
for i in $tx49_files ; do
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index d588b15..d00a8ee 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,13 @@
+start-sanitize-vr4xxx
+1998-12-13 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips.h (E_MIPS_MACH_4121): New.
+
+end-sanitize-vr4xxx
+1998-12-03 Nick Clifton <nickc@cygnus.com>
+
+ * fr30.h: Add R_FR30_48 reloc.
+
1998-12-02 Ulrich Drepper <drepper@cygnus.com>
* mips.h: Add external data type for conflict section.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 58f7ae8..a895d59 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -142,6 +142,9 @@ END_RELOC_NUMBERS
/* start-sanitize-tx49 */
#define E_MIPS_MACH_4900 0x00860000
/* end-sanitize-tx49 */
+/* start-sanitize-vr4xxx */
+#define E_MIPS_MACH_4121 0x00870000
+/* end-sanitize-vr4xxx */
/* start-sanitize-cygnus */
#define E_MIPS_MACH_5400 0x00910000
@@ -360,6 +363,10 @@ typedef struct
/* A section of type SHT_MIPS_CONFLICT is an array of indices into the
.dynsym section. Each element has the following type. */
typedef unsigned long Elf32_Conflict;
+typedef unsigned char Elf32_External_Conflict[4];
+
+typedef unsigned long Elf64_Conflict;
+typedef unsigned char Elf64_External_Conflict[8];
/* A section of type SHT_MIPS_GPTAB contains information about how
much GP space would be required for different -G arguments. This
diff --git a/include/opcode/.Sanitize b/include/opcode/.Sanitize
index 76c1904..4f049d1 100644
--- a/include/opcode/.Sanitize
+++ b/include/opcode/.Sanitize
@@ -329,6 +329,35 @@ else
fi
+vr4xxx_files="ChangeLog mips.h"
+if ( echo $* | grep keep\-vr4xxx > /dev/null ) ; then
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Keeping vr4xxx stuff in $i
+ fi
+ fi
+ done
+else
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Removing traces of \"vr4xxx\" from $i...
+ fi
+ cp $i new
+ sed '/start\-sanitize\-vr4xxx/,/end-\sanitize\-vr4xxx/d' < $i > new
+ if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+ if [ -n "${verbose}" ] ; then
+ echo Caching $i in .Recover...
+ fi
+ mv $i .Recover
+ fi
+ mv new $i
+ fi
+ done
+fi
+
+
for i in * ; do
if test ! -d $i && (grep sanitize $i > /dev/null) ; then
echo '***' Some mentions of Sanitize are still left in $i! 1>&2
diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index 49b8a02..71cd19a 100644
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -276,6 +276,34 @@ else
done
fi
+vr4xxx_files="ChangeLog mips-opc.c mips-dis.c"
+if ( echo $* | grep keep\-vr4xxx > /dev/null ) ; then
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Keeping vr4xxx stuff in $i
+ fi
+ fi
+ done
+else
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Removing traces of \"vr4xxx\" from $i...
+ fi
+ cp $i new
+ sed '/start\-sanitize\-vr4xxx/,/end-\sanitize\-vr4xxx/d' < $i > new
+ if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+ if [ -n "${verbose}" ] ; then
+ echo Caching $i in .Recover...
+ fi
+ mv $i .Recover
+ fi
+ mv new $i
+ fi
+ done
+fi
+
cygnus_files="ChangeLog mips-opc.c mips-dis.c"
if ( echo $* | grep keep\-cygnus > /dev/null ) ; then
for i in $cygnus_files ; do
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c6c55b9..b238a08 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+start-sanitize-vr4xxx
+1998-12-13 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips-dis.c (set_mips_isa_type): Add bfd_mach_mips4121.
+ (_print_insn_mips): Same.
+ * mips-opc.c: Add vr4121.
+
start-sanitize-fr30
Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com>
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 4efd91c..62eb63b 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -87,10 +87,10 @@ print_insn_arg (d, l, pc, info)
case ',':
case '(':
case ')':
- /* start-sanitize-vr5400 */
+ /* start-sanitize-cygnus */
case '[':
case ']':
- /* end-sanitize-vr5400 */
+ /* end-sanitize-cygnus */
/* start-sanitize-r5900 */
case '+':
case '-':
@@ -355,7 +355,7 @@ print_insn_arg (d, l, pc, info)
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
break;
- /* start-sanitize-vr5400 */
+ /* start-sanitize-cygnus */
case 'e':
(*info->fprintf_func) (info->stream, "%d",
(l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
@@ -365,7 +365,7 @@ print_insn_arg (d, l, pc, info)
(*info->fprintf_func) (info->stream, "%d",
(l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
break;
- /* end-sanitize-vr5400 */
+ /* end-sanitize-cygnus */
default:
/* xgettext:c-format */
@@ -418,6 +418,12 @@ set_mips_isa_type (mach, isa, cputype)
target_processor = 4100;
mips_isa = 3;
break;
+ /* start-sanitize-vr4xxx */
+ case bfd_mach_mips4121:
+ target_processor = 4121;
+ mips_isa = 3;
+ break;
+ /* end-sanitize-vr4xxx */
case bfd_mach_mips4300:
target_processor = 4300;
mips_isa = 3;
@@ -450,12 +456,12 @@ set_mips_isa_type (mach, isa, cputype)
target_processor = 5000;
mips_isa = 4;
break;
- /* start-sanitize-vr5400 */
+ /* start-sanitize-cygnus */
case bfd_mach_mips5400:
target_processor = 5400;
mips_isa = 3;
break;
- /* end-sanitize-vr5400 */
+ /* end-sanitize-cygnus */
/* start-sanitize-r5900 */
case bfd_mach_mips5900:
target_processor = 5900;
@@ -535,7 +541,7 @@ _print_insn_mips (memaddr, word, info)
target_processor = mips_target_info.processor;
mips_isa = mips_target_info.isa;
#else
- set_mips_isa_type (info->mach, &target_processor, &mips_isa);
+ set_mips_isa_type (info->mach, &mips_isa, &target_processor);
#endif
info->bytes_per_chunk = 4;
@@ -569,14 +575,18 @@ _print_insn_mips (memaddr, word, info)
&& op->membership & INSN_4010) == 0
&& (target_processor == 4100
&& op->membership & INSN_4100) == 0
+ /* start-sanitize-vr4xxx */
+ && (target_processor == 4121
+ && op->membership & INSN_4121) == 0
+ /* end-sanitize-vr4xxx */
/* start-sanitize-vr4320 */
&& (target_processor == 4320
&& op->membership & INSN_4320) == 0
/* end-sanitize-vr4320 */
- /* start-sanitize-vr5400 */
+ /* start-sanitize-cygnus */
&& (target_processor == 5400
&& op->membership & INSN_5400) == 0
- /* end-sanitize-vr5400 */
+ /* end-sanitize-cygnus */
/* start-sanitize-r5900 */
&& (target_processor == 5900
&& op->membership & INSN_5900) == 0
diff --git a/sim/mips/.Sanitize b/sim/mips/.Sanitize
index ce9cf3b..9ddebee 100644
--- a/sim/mips/.Sanitize
+++ b/sim/mips/.Sanitize
@@ -262,6 +262,36 @@ else
fi
+vr4xxx_files="ChangeLog Makefile.in configure configure.in mips.igen vr.igen"
+
+if ( echo $* | grep keep\-vr4xxx > /dev/null ) ; then
+ for i in $vr4xxx_files ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Keeping vr4xxx stuff in $i
+ fi
+ fi
+ done
+else
+ for i in * ; do
+ if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Removing traces of \"vr4xxx\" from $i...
+ fi
+ cp $i new
+ sed '/start\-sanitize\-vr4xxx/,/end-\sanitize\-vr4xxx/d' < $i > new
+ if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+ if [ -n "${verbose}" ] ; then
+ echo Caching $i in .Recover...
+ fi
+ mv $i .Recover
+ fi
+ mv new $i
+ fi
+ done
+fi
+
+
tx3904_files="ChangeLog configure configure.in interp.c"
if ( echo $* | grep keep\-tx3904 > /dev/null ) ; then
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index a29f164..7aeae1b 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,10 @@
+start-sanitize-vr4xxx
+1998-12-13 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * configure.in,mips.igen,vr.igen: Add vr4121.
+ * configure: Rebuilt.
+
+end-sanitize-vr4xxx
1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
start-sanitize-vr4xxx
diff --git a/sim/mips/configure b/sim/mips/configure
index b4f9044..687d722 100755
--- a/sim/mips/configure
+++ b/sim/mips/configure
@@ -3968,7 +3968,7 @@ case "${target}" in
# end-sanitize-cygnus
# start-sanitize-vr4xxx
mips64vr4xxx-*-*) sim_gen=IGEN
- sim_igen_machine="-M mipsIV,vr4100 -G gen-multi-sim=mipsIV"
+ sim_igen_machine="-M mipsIV,vr4100,vr4121 -G gen-multi-sim=mipsIV"
;;
# end-sanitize-vr4xxx
mips64vr41*) sim_gen=M16
diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index 2cb577f..86e14f8 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -169,7 +169,7 @@ case "${target}" in
# end-sanitize-cygnus
# start-sanitize-vr4xxx
mips64vr4xxx-*-*) sim_gen=IGEN
- sim_igen_machine="-M mipsIV,vr4100 -G gen-multi-sim=mipsIV"
+ sim_igen_machine="-M mipsIV,vr4100,vr4121 -G gen-multi-sim=mipsIV"
;;
# end-sanitize-vr4xxx
mips64vr41*) sim_gen=M16
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 8c07108..ba02a9b 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -48,6 +48,9 @@
:model:::tx19:tx19:
// end-sanitize-tx19
:model:::vr4100:mips4100:
+// start-sanitize-vr4xxx
+:model:::vr4121:mips4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
:model:::vr4320:mips4320:
// end-sanitize-vr4320
@@ -151,6 +154,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -185,6 +191,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -242,6 +251,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -284,6 +296,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -341,6 +356,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -371,6 +389,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -408,6 +429,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -439,6 +463,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -470,6 +497,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -494,6 +524,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -520,6 +553,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -552,6 +588,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -584,6 +623,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -614,6 +656,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -647,6 +692,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -684,6 +732,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -716,6 +767,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -748,6 +802,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -782,6 +839,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -816,6 +876,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -848,6 +911,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -878,6 +944,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -913,6 +982,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -948,6 +1020,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -982,6 +1057,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1014,6 +1092,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1046,6 +1127,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1143,6 +1227,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1174,6 +1261,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1211,6 +1301,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1242,6 +1335,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1292,6 +1388,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1337,6 +1436,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1383,6 +1485,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1428,6 +1533,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1516,6 +1624,9 @@
"dmult r<RS>, r<RT>"
*mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
@@ -1548,6 +1659,9 @@
"dmultu r<RS>, r<RT>"
*mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
@@ -1577,6 +1691,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1601,6 +1718,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1626,6 +1746,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1651,6 +1774,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1675,6 +1801,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1707,6 +1836,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1730,6 +1862,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1754,6 +1889,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1778,6 +1916,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1802,6 +1943,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1838,6 +1982,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1860,6 +2007,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1886,6 +2036,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1914,6 +2067,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1939,6 +2095,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -1984,6 +2143,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2007,6 +2169,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2031,6 +2196,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2055,6 +2223,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2078,6 +2249,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2101,6 +2275,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2123,6 +2300,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2146,6 +2326,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2171,6 +2354,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2222,6 +2408,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2265,6 +2454,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2290,6 +2482,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2313,6 +2508,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2393,6 +2591,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2447,6 +2648,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2471,6 +2675,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2501,6 +2708,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2533,6 +2743,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2556,6 +2769,9 @@
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2597,6 +2813,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2622,6 +2841,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2660,6 +2882,9 @@
"mult r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2704,6 +2929,9 @@
"multu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2741,6 +2969,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2771,6 +3002,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2802,6 +3036,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2875,6 +3112,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2900,6 +3140,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2951,6 +3194,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -2998,6 +3244,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3022,6 +3271,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3042,6 +3294,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3065,6 +3320,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3087,6 +3345,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3118,6 +3379,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3150,6 +3414,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3180,6 +3447,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3210,6 +3480,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3240,6 +3513,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3271,6 +3547,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3302,6 +3581,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3335,6 +3617,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3367,6 +3652,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3399,6 +3687,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3422,6 +3713,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3458,6 +3752,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3480,6 +3777,9 @@
"sw r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
@@ -3504,6 +3804,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3571,6 +3874,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3615,6 +3921,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3641,6 +3950,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3664,6 +3976,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3689,6 +4004,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3714,6 +4032,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3739,6 +4060,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3764,6 +4088,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3789,6 +4116,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3814,6 +4144,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3839,6 +4172,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3864,6 +4200,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3889,6 +4228,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3914,6 +4256,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3939,6 +4284,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3964,6 +4312,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -3994,6 +4345,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4024,6 +4378,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4117,6 +4474,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4147,6 +4507,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4182,6 +4545,12 @@
"bc1%s<TF>%s<ND> <OFFSET>"
*mipsI,mipsII,mipsIII:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
@@ -4211,9 +4580,6 @@
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
*vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
@@ -4280,19 +4646,22 @@
}
}
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
-*mipsI,mipsII,mipsIII:
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
+*mipsI,mipsII,mipsIII:
{
do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
}
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4314,6 +4683,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4347,6 +4719,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4405,6 +4780,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4463,6 +4841,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4493,6 +4874,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4525,6 +4909,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4554,6 +4941,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4583,6 +4973,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4639,6 +5032,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4678,6 +5074,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4712,6 +5111,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4746,6 +5148,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4782,6 +5187,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4886,6 +5294,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -4897,6 +5308,7 @@
*tx19:
// end-sanitize-tx19
{
+ int fs = FS;
if (X)
/*MTC1*/
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
@@ -4910,6 +5322,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5091,6 +5506,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5121,6 +5539,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5291,6 +5712,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5325,6 +5749,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5383,6 +5810,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5420,6 +5850,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5449,6 +5882,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5480,6 +5916,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5571,6 +6010,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5605,6 +6047,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5644,6 +6089,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5657,6 +6105,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5669,6 +6120,9 @@
"bc0t <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
@@ -5676,6 +6130,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5689,6 +6146,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5719,6 +6179,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5732,6 +6195,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5746,6 +6212,9 @@
*mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5777,6 +6246,9 @@
*r3900:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5800,6 +6272,9 @@
// end-sanitize-tx19
*r3900:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5823,6 +6298,9 @@
// end-sanitize-tx19
*r3900:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5842,6 +6320,9 @@
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
@@ -5860,6 +6341,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5873,6 +6357,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5886,6 +6373,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -5899,6 +6389,9 @@
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
diff --git a/sim/mips/vr.igen b/sim/mips/vr.igen
index 6775f91..f04d4e7 100644
--- a/sim/mips/vr.igen
+++ b/sim/mips/vr.igen
@@ -14,6 +14,9 @@
:function:::unsigned64:MulAcc:
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -27,6 +30,9 @@
:function:::void:SET_MulAcc:unsigned64 value
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -41,6 +47,9 @@
:function:::signed64:SignedMultiply:signed32 l, signed32 r
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -54,6 +63,9 @@
:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -65,11 +77,34 @@
return result;
}
+// start-sanitize-vr4xxx
+:function:::signed64:SaturatedAdd:signed32 l, signed32 r
+*vr4121:
+{
+ signed64 result = (signed64) l + (signed64) r;
+ if (result < 0)
+ result = 0xFFFFFFFF8000000LL;
+ else if (result > 0x000000007FFFFFFFLL)
+ result = 0x000000007FFFFFFFLL;
+ return result;
+}
+
+:function:::unsigned64:SaturatedUnsignedAdd:unsigned32 l, unsigned32 r
+*vr4121:
+{
+ unsigned64 result = (unsigned64) l + (unsigned64) r;
+ if (result > 0x000000007FFFFFFFLL)
+ result = 0xFFFFFFFFFFFFFFFFLL;
+ return result;
+}
+
+
+// end-sanitize-vr4xxx
:function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
@@ -80,6 +115,9 @@
:function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
@@ -94,7 +132,7 @@
// Multiply, Accumulate
-000000,5.RS,5.RT,00000,00000,101000::::MAC
+000000,5.RS,5.RT,00000,00000,101000::64::MAC
"mac r<RS>, r<RT>"
*vr4100:
// start-sanitize-vr4320
@@ -106,7 +144,7 @@
// D-Multiply, Accumulate
-000000,5.RS,5.RT,00000,00000,101001::::DMAC
+000000,5.RS,5.RT,00000,00000,101001::64::DMAC
"dmac r<RS>, r<RT>"
*vr4100:
// start-sanitize-vr4320
@@ -119,7 +157,7 @@
// start-sanitize-vr4320
// Count Leading Zeros
-000000,5.RS,00000,5.RD,00000,110101::::CLZ
+000000,5.RS,00000,5.RD,00000,110101::64::CLZ
"clz r<RD>, r<RS>"
// end-sanitize-vr4320
// start-sanitize-vr4320
@@ -144,7 +182,7 @@
// end-sanitize-vr4320
// start-sanitize-vr4320
// D-Count Leading Zeros
-000000,5.RS,00000,5.RD,00000,111101::::DCLZ
+000000,5.RS,00000,5.RD,00000,111101::64::DCLZ
"dclz r<RD>, r<RS>"
// end-sanitize-vr4320
// start-sanitize-vr4320
@@ -173,85 +211,85 @@
// end-sanitize-vr4320
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
// Multiply and Move LO.
-000000,5.RS,5.RT,5.RD,00100,101000::::MUL
+000000,5.RS,5.RT,5.RD,00100,101000::64::MUL
"mul r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
-// end-sanitize-vrXXXX
-// start-sanitize-vrXXXX
+// end-sanitize-cygnus
+// start-sanitize-cygnus
// Unsigned Multiply and Move LO.
-000000,5.RS,5.RT,5.RD,00101,101000::::MULU
+000000,5.RS,5.RT,5.RD,00101,101000::64::MULU
"mulu r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
-// end-sanitize-vrXXXX
-// start-sanitize-vrXXXX
+// end-sanitize-cygnus
+// start-sanitize-cygnus
// Multiply and Move HI.
-000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
+000000,5.RS,5.RT,5.RD,01100,101000::64::MULHI
"mulhi r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
-// end-sanitize-vrXXXX
-// start-sanitize-vrXXXX
+// end-sanitize-cygnus
+// start-sanitize-cygnus
// Unsigned Multiply and Move HI.
-000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
+000000,5.RS,5.RT,5.RD,01101,101000::64::MULHIU
"mulhiu r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-cygnus
// Multiply, Negate and Move LO.
-000000,5.RS,5.RT,5.RD,00011,011000::::MULS
+000000,5.RS,5.RT,5.RD,00011,011000::64::MULS
"muls r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -267,7 +305,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply, Negate and Move LO.
-000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
+000000,5.RS,5.RT,5.RD,00011,011001::64::MULSU
"mulsu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -283,7 +321,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Multiply, Negate and Move HI.
-000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
+000000,5.RS,5.RT,5.RD,01011,011000::64::MULSHI
"mulshi r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -299,7 +337,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply, Negate and Move HI.
-000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
+000000,5.RS,5.RT,5.RD,01011,011001::64::MULSHIU
"mulshiu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -312,103 +350,214 @@
}
-
-
-
// end-sanitize-cygnus
+// start-sanitize-cygnus
+//
// Multiply, Accumulate and Move LO.
-000000,5.RS,5.RT,5.RD,00010,101000::::MACC
+//
+000000,5.RS,5.RT,5.RD,00010,101000::64::MACC
"macc r<RD>, r<RS>, r<RT>"
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
+// end-sanitize-cygnus
+
+// start-sanitize-vr4xxx
+000000,5.RS,5.RT,5.RD,00000,101000::::MACC
+"macc r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+ GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+}
+
+000000,5.RS,5.RT,5.RD,00000,101001::::DMACC
+"dmacc r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
+ GPR[RD] = LO;
+}
+
+000000,5.RS,5.RT,5.RD,10000,101000::::MACCS
+"maccs r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_),
+ SignedMultiply (SD_, GPR[RS], GPR[RT])));
+ GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+}
+
+000000,5.RS,5.RT,5.RD,10000,101001::::DMACCS
+"dmaccs r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ LO = SaturatedAdd (SD_, LO, SignedMultiply (SD_, GPR[RS], GPR[RT]));
+ GPR[RD] = LO;
+}
-// start-sanitize-vrXXXX
+
+
+
+// end-sanitize-vr4xxx
+// start-sanitize-cygnus
+//
// Unsigned Multiply, Accumulate and Move LO.
-000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
+//
+000000,5.RS,5.RT,5.RD,00011,101000::64::MACCU
"maccu r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
+{
+ SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+ GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+}
+
+// end-sanitize-cygnus
+// start-sanitize-vr4xxx
+000000,5.RS,5.RT,5.RD,00001,101000::64::MACCU
+"maccu r<RD>, r<RS>, r<RT>"
+*vr4121:
{
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
+000000,5.RS,5.RT,5.RD,00001,101001::64::DMACCU
+"dmaccu r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ LO = LO + UnsignedMultiply (SD_, GPR[RS], GPR[RT]);
+ GPR[RD] = LO;
+}
+
+000000,5.RS,5.RT,5.RD,10001,101000::64::MACCUS
+"maccus r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ SET_MulAcc (SD_,
+ SaturatedUnsignedAdd (SD_, MulAcc (SD_),
+ UnsignedMultiply (SD_, GPR[RS], GPR[RT])));
+ GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+}
+
+000000,5.RS,5.RT,5.RD,10001,101001::64::DMACCUS
+"dmaccus r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ LO = SaturatedUnsignedAdd (SD_, LO,
+ UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+ GPR[RD] = LO;
+}
+
+
-// end-sanitize-vrXXXX
-// start-sanitize-vrXXXX
+// end-sanitize-vr4xxx
+// start-sanitize-cygnus
+//
// Multiply, Accumulate and Move HI.
-000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
+//
+000000,5.RS,5.RT,5.RD,01010,101000::64::MACCHI
"macchi r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
+// end-sanitize-cygnus
+// start-sanitize-vr4xxx
+000000,5.RS,5.RT,5.RD,01000,101000::64::MACCHI
+"macchi r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+ GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
-// end-sanitize-vrXXXX
-// start-sanitize-vrXXXX
+000000,5.RS,5.RT,5.RD,11000,101000::64::MACCHIS
+"macchis r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_),
+ SignedMultiply (SD_, GPR[RS], GPR[RT])));
+ GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+
+// end-sanitize-vr4xxx
+// start-sanitize-cygnus
+//
// Unsigned Multiply, Accumulate and Move HI.
-000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
+//
+000000,5.RS,5.RT,5.RD,01011,101000::64::MACCHIU
"macchiu r<RD>, r<RS>, r<RT>"
-// end-sanitize-vrXXXX
+// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
-// start-sanitize-vrXXXX
+// start-sanitize-cygnus
{
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
+// end-sanitize-cygnus
+// start-sanitize-vr4xxx
+000000,5.RS,5.RT,5.RD,01001,101000::64::MACCHIU
+"macchiu r<RD>, r<RS>, r<RT>"
+*vr4121:
+{
+ SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+ GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
-// end-sanitize-vrXXXX
-// start-sanitize-cygnus
-// Multiply, Negate, Accumulate and Move LO.
-000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
-"msac r<RD>, r<RS>, r<RT>"
-// end-sanitize-cygnus
-// start-sanitize-cygnus
-*vr5400:
-// end-sanitize-cygnus
-// start-sanitize-cygnus
+000000,5.RS,5.RT,5.RD,11001,101000::64::MACCHIUS
+"macchius r<RD>, r<RS>, r<RT>"
+*vr4121:
{
- SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
- GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+ SET_MulAcc (SD_,
+ SaturatedUnsignedAdd (SD_, MulAcc (SD_),
+ UnsignedMultiply (SD_, GPR[RS], GPR[RT])));
+ GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+
}
-// end-sanitize-cygnus
+
+// end-sanitize-vr4xxx
// start-sanitize-cygnus
// Unsigned Multiply, Negate, Accumulate and Move LO.
-000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
+000000,5.RS,5.RT,5.RD,00111,011001::64::MSACU
"msacu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -439,7 +588,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply, Negate, Accumulate and Move HI.
-000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
+000000,5.RS,5.RT,5.RD,01111,011001::64::MSACHIU
"msachiu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -455,7 +604,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Rotate Right.
-000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
+000000,00001,5.RT,5.RD,5.SHIFT,000010::64::ROR
"ror r<RD>, r<RT>, <SHIFT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -471,7 +620,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Rotate Right Variable.
-000000,5.RS,5.RT,5.RD,00001,000110::::RORV
+000000,5.RS,5.RT,5.RD,00001,000110::64::RORV
"rorv r<RD>, r<RT>, <RS>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -487,7 +636,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Double Rotate Right.
-000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
+000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
"dror r<RD>, r<RT>, <SHIFT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -503,7 +652,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Double Rotate Right Plus 32.
-000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
+000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
"dror32 r<RD>, r<RT>, <SHIFT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
@@ -519,7 +668,7 @@
// end-sanitize-cygnus
// start-sanitize-cygnus
// Double Rotate Right Variable.
-000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
+000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
"drorv r<RD>, r<RT>, <RS>"
// end-sanitize-cygnus
// start-sanitize-cygnus
generated by cgit v1.1 at 2024-09-10 18:54:22 +0000