diff options
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-fld-fsd-fail.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-fld-fsd-fail.l | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-fld-fsd-fail.s | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 32 |
6 files changed, 36 insertions, 16 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 1862390..56aae60 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2018-08-31 Kito Cheng <kito@andestech.com> + + * testsuite/gas/riscv/c-fld-fsd-fail.d: New. + * testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise. + * testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise. + 2018-08-31 H.J. Lu <hongjiu.lu@intel.com> * testsuite/gas/elf/section14.d: Change skip to xfail. diff --git a/gas/testsuite/gas/riscv/c-fld-fsd-fail.d b/gas/testsuite/gas/riscv/c-fld-fsd-fail.d new file mode 100644 index 0000000..a90f7b4f --- /dev/null +++ b/gas/testsuite/gas/riscv/c-fld-fsd-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ic +#source: c-fld-fsd-fail.s +#error-output: c-fld-fsd-fail.l diff --git a/gas/testsuite/gas/riscv/c-fld-fsd-fail.l b/gas/testsuite/gas/riscv/c-fld-fsd-fail.l new file mode 100644 index 0000000..7d99abb --- /dev/null +++ b/gas/testsuite/gas/riscv/c-fld-fsd-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fld fa0,0\(a0\)' +.*: Error: unrecognized opcode `fsd fa0,0\(a0\)' diff --git a/gas/testsuite/gas/riscv/c-fld-fsd-fail.s b/gas/testsuite/gas/riscv/c-fld-fsd-fail.s new file mode 100644 index 0000000..1cb0c5e --- /dev/null +++ b/gas/testsuite/gas/riscv/c-fld-fsd-fail.s @@ -0,0 +1,3 @@ +target: + fld fa0, 0(a0) + fsd fa0, 0(a0) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b621ab0..a2dd3cf 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-08-31 Kito Cheng <kito@andestech.com> + + * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for + compressed floating point instructions. + 2018-08-30 Kito Cheng <kito@andestech.com> * riscv-dis.c (riscv_disassemble_insn): Check XLEN by diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 230ef76..945164a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -509,12 +509,12 @@ const struct riscv_opcode riscv_opcodes[] = {"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, {"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 }, {"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 }, -{"flw", 32, {"C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"flw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"flw", 0, {"F", 0}, "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, -{"fsw", 32, {"C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, -{"fsw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"fsw", 32, {"F", "C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"fsw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"fsw", 0, {"F", 0}, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"fsw", 0, {"F", 0}, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, @@ -574,12 +574,12 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, {"F", 0}, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, /* Double-precision floating-point instruction subset */ -{"fld", 0, {"C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fld", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fld", 0, {"D", "C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fld", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, {"D", 0}, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fld", 0, {"D", 0}, "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, -{"fsd", 0, {"C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, -{"fsd", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fsd", 0, {"D", "C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"fsd", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, {"D", 0}, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, {"D", 0}, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, {"fmv.d", 0, {"D", 0}, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, @@ -733,14 +733,14 @@ const struct riscv_opcode riscv_opcodes[] = {"c.ld", 64, {"C", 0}, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"c.sdsp", 64, {"C", 0}, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, {"c.sd", 64, {"C", 0}, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fldsp", 0, {"C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fld", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fsdsp", 0, {"C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.fsd", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, -{"c.flwsp", 32, {"C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.flw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.fswsp", 32, {"C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.fsw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.fldsp", 0, {"D", "C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fld", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fsdsp", 0, {"D", "C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.fsd", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.flwsp", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.fswsp", 32, {"F", "C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.fsw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, /* Supervisor instructions */ {"csrr", 0, {"I", 0}, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS }, |