18 files changed, 1946 insertions, 1121 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 22643dc..73398b3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,31 @@
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+	* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
+	intel syntax and no register prefix, allow $ in symbol names when
+	intel syntax.
+	(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
+	(intel_float_operand): Add fourth return value indicating math control
+	operations. Make classification more precise.
+	(md_assemble): Complain if memory operand of mov[sz]x has no size
+	specified.
+	(parse_insn): Translate word operands to floating point instructions
+	operating on integers as well as control instructions to short ones
+	as expected by AT&T syntax. Translate 'd' suffix to short one only for
+	floating point instructions operating on non-integer operands.
+	(match_template): Remove fldcw special case. Adjust q-suffix handling
+	to permit it on fild/fistp/fisttp in AT&T mode.
+	(process_suffix): Don't guess DefaultSize insns' suffix from
+	stackop_size for certain floating point control instructions. Guess
+	suffix for branch and [ls][gi]dt based on flag_code. Split error
+	messages for Intel and AT&T syntax, and make the condition more strict
+	for the former. Adjust suppressing of generation of operand size
+	overrides.
+	(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
+	OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
+	more error checking.
+	* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
+	SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
+
 2004-11-03  Hans-Peter Nilsson  <hp@axis.com>
 
 	* symbols.c (colon) [!WORKING_DOT_WORD]: Don't declare
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index b2f42dc..606d16b 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -782,7 +782,7 @@ set_16bit_gcc_code_flag (new_code_flag)
   flag_code = new_code_flag;
   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
   cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
-  stackop_size = 'l';
+  stackop_size = LONG_MNEM_SUFFIX;
 }
 
 static void
@@ -815,6 +815,9 @@ set_intel_syntax (syntax_flag)
 		       && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
   else
     allow_naked_reg = (ask_naked_reg < 0);
+
+  identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
+  identifier_chars['$'] = intel_syntax ? '$' : 0;
 }
 
 static void
@@ -1280,13 +1283,54 @@ static int
 intel_float_operand (mnemonic)
      const char *mnemonic;
 {
-  if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
-    return 2;
-
-  if (mnemonic[0] == 'f')
-    return 1;
+  /* Note that the value returned is meaningful only for opcodes with (memory)
+     operands, hence the code here is free to improperly handle opcodes that
+     have no operands (for better performance and smaller code). */
+
+  if (mnemonic[0] != 'f')
+    return 0; /* non-math */
+
+  switch (mnemonic[1])
+    {
+    /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
+       the fs segment override prefix not currently handled because no
+       call path can make opcodes without operands get here */
+    case 'i':
+      return 2 /* integer op */;
+    case 'l':
+      if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
+	return 3; /* fldcw/fldenv */
+      break;
+    case 'n':
+      if (mnemonic[2] != 'o' /* fnop */)
+	return 3; /* non-waiting control op */
+      break;
+    case 'r':
+      if (mnemonic[2] == 's')
+	return 3; /* frstor/frstpm */
+      break;
+    case 's':
+      if (mnemonic[2] == 'a')
+	return 3; /* fsave */
+      if (mnemonic[2] == 't')
+	{
+	  switch (mnemonic[3])
+	    {
+	    case 'c': /* fstcw */
+	    case 'd': /* fstdw */
+	    case 'e': /* fstenv */
+	    case 's': /* fsts[gw] */
+	      return 3;
+	    }
+	}
+      break;
+    case 'x':
+      if (mnemonic[2] == 'r' || mnemonic[2] == 's')
+	return 0; /* fxsave/fxrstor are not really math ops */
+      break;
+    }
 
-  return 0;
+  return 1;
 }
 
 /* This is the guts of the machine-dependent assembler.  LINE points to a
@@ -1358,7 +1402,20 @@ md_assemble (line)
 	 "word ptr" or "byte ptr" on the source operand, but we'll use
 	 the suffix later to choose the destination register.  */
       if ((i.tm.base_opcode & ~9) == 0x0fb6)
-	i.suffix = 0;
+	{
+	  if (i.reg_operands < 2
+	      && !i.suffix
+	      && (~i.tm.opcode_modifier
+		  & (No_bSuf
+		     | No_wSuf
+		     | No_lSuf
+		     | No_sSuf
+		     | No_xSuf
+		     | No_qSuf)))
+	    as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+
+	  i.suffix = 0;
+	}
     }
 
   if (i.tm.opcode_modifier & FWait)
@@ -1580,6 +1637,9 @@ parse_insn (line, mnemonic)
       switch (mnem_p[-1])
 	{
 	case WORD_MNEM_SUFFIX:
+	  if (intel_syntax && (intel_float_operand (mnemonic) & 2))
+	    i.suffix = SHORT_MNEM_SUFFIX;
+	  else
 	case BYTE_MNEM_SUFFIX:
 	case QWORD_MNEM_SUFFIX:
 	  i.suffix = mnem_p[-1];
@@ -1600,7 +1660,7 @@ parse_insn (line, mnemonic)
 	case 'd':
 	  if (intel_syntax)
 	    {
-	      if (intel_float_operand (mnemonic))
+	      if (intel_float_operand (mnemonic) == 1)
 		i.suffix = SHORT_MNEM_SUFFIX;
 	      else
 		i.suffix = LONG_MNEM_SUFFIX;
@@ -2020,9 +2080,10 @@ match_template ()
   t = current_templates->start;
   if (i.suffix == QWORD_MNEM_SUFFIX
       && flag_code != CODE_64BIT
-      && (!intel_syntax
-	  || (!(t->opcode_modifier & IgnoreSize)
-	      && ! intel_float_operand (t->name)))
+      && (intel_syntax
+	  ? !(t->opcode_modifier & IgnoreSize)
+	    && !intel_float_operand (t->name)
+	  : intel_float_operand (t->name) != 2)
       && (!(t->operand_types[0] & (RegMMX | RegXMM))
 	  || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
       && (t->base_opcode != 0x0fc7
@@ -2037,11 +2098,7 @@ match_template ()
       /* Check the suffix, except for some instructions in intel mode.  */
       if ((t->opcode_modifier & suffix_check)
 	  && !(intel_syntax
-	       && (t->opcode_modifier & IgnoreSize))
-	  && !(intel_syntax
-	       && t->base_opcode == 0xd9
-	       && (t->extension_opcode == 5	     /* 0xd9,5 "fldcw"  */
-		   || t->extension_opcode == 7)))  /* 0xd9,7 "f{n}stcw"  */
+	       && (t->opcode_modifier & IgnoreSize)))
 	continue;
 
       /* Do not verify operands when there are none.  */
@@ -2256,22 +2313,75 @@ process_suffix (void)
       else
 	abort ();
     }
-  else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
+  else if ((i.tm.opcode_modifier & DefaultSize)
+	   && !i.suffix
+	   /* exclude fldenv/frstor/fsave/fstenv */
+	   && (i.tm.opcode_modifier & No_sSuf))
     {
       i.suffix = stackop_size;
       if (i.suffix == QWORD_MNEM_SUFFIX
 	  && (i.tm.opcode_modifier & No_qSuf))
 	i.suffix = LONG_MNEM_SUFFIX;
     }
+  else if (intel_syntax
+	   && !i.suffix
+	   && ((i.tm.operand_types[0] & JumpAbsolute)
+	    || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
+	    || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
+		&& i.tm.extension_opcode <= 3)))
+    {
+      switch (flag_code)
+	{
+	case CODE_64BIT:
+	  if (!(i.tm.opcode_modifier & No_qSuf))
+	    {
+	      i.suffix = QWORD_MNEM_SUFFIX;
+	      break;
+	    }
+	case CODE_32BIT:
+	  if (!(i.tm.opcode_modifier & No_lSuf))
+	    i.suffix = LONG_MNEM_SUFFIX;
+	  break;
+	case CODE_16BIT:
+	  if (!(i.tm.opcode_modifier & No_wSuf))
+	    i.suffix = WORD_MNEM_SUFFIX;
+	  break;
+	}
+    }
 
-  /* Change the opcode based on the operand size given by i.suffix;
-     We need not change things for byte insns.  */
-  if (!i.suffix && (i.tm.opcode_modifier & W))
+  if (!i.suffix)
     {
-      as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
-      return 0;
+      if (!intel_syntax)
+	{
+	  if (i.tm.opcode_modifier & W)
+	    {
+	      as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
+	      return 0;
+	    }
+	}
+      else
+	{
+	  unsigned int suffixes = ~i.tm.opcode_modifier
+				  & (No_bSuf
+				     | No_wSuf
+				     | No_lSuf
+				     | No_sSuf
+				     | No_xSuf
+				     | No_qSuf);
+
+	  if ((i.tm.opcode_modifier & W)
+	      || ((suffixes & (suffixes - 1))
+		  && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
+	    {
+	      as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+	      return 0;
+	    }
+	}
     }
 
+  /* Change the opcode based on the operand size given by i.suffix;
+     We don't need to change things for byte insns.  */
+
   if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
     {
       /* It's not a byte, select word/dword operation.  */
@@ -2287,7 +2397,8 @@ process_suffix (void)
 	 size prefix, except for instructions that will ignore this
 	 prefix anyway.  */
       if (i.suffix != QWORD_MNEM_SUFFIX
-	  && !(i.tm.opcode_modifier & IgnoreSize)
+	  && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
+	  && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
 	  && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
 	      || (flag_code == CODE_64BIT
 		  && (i.tm.opcode_modifier & JumpByte))))
@@ -5336,15 +5447,17 @@ tc_gen_reloc (section, fixp)
 
    Initial production is 'expr'.
 
-    addOp		+ | - | & | \| | << | >>
+    addOp		+ | -
 
     alpha		[a-zA-Z]
 
+    binOp		& | AND | \| | OR | ^ | XOR
+
     byteRegister	AL | AH | BL | BH | CL | CH | DL | DH
 
     constant		digits [[ radixOverride ]]
 
-    dataType		BYTE | WORD | DWORD | QWORD | XWORD
+    dataType		BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
 
     digits		decdigit
 			| digits decdigit
@@ -5352,13 +5465,18 @@ tc_gen_reloc (section, fixp)
 
     decdigit		[0-9]
 
-    e05			e05 addOp e06
+    e04			e04 addOp e05
+			| e05
+
+    e05			e05 binOp e06
 			| e06
 
     e06			e06 mulOp e09
 			| e09
 
     e09			OFFSET e10
+			| ~ e10
+			| NOT e10
 			| e09 PTR e10
 			| e09 : e10
 			| e10
@@ -5373,10 +5491,9 @@ tc_gen_reloc (section, fixp)
 			| id
 			| $
 			| register
-			| ~
 
- => expr		SHORT e05
-			| e05
+ => expr		SHORT e04
+			| e04
 
     gpRegister		AX | EAX | BX | EBX | CX | ECX | DX | EDX
 			| BP | EBP | SP | ESP | DI | EDI | SI | ESI
@@ -5388,7 +5505,7 @@ tc_gen_reloc (section, fixp)
 			| id alpha
 			| id decdigit
 
-    mulOp		* | / | MOD
+    mulOp		* | / | % | MOD | << | SHL | >> | SHR
 
     quote		" | '
 
@@ -5398,7 +5515,7 @@ tc_gen_reloc (section, fixp)
 
     segmentRegister	CS | DS | ES | FS | GS | SS
 
-    specialRegister	CR0 | CR2 | CR3
+    specialRegister	CR0 | CR2 | CR3 | CR4
 			| DR0 | DR1 | DR2 | DR3 | DR6 | DR7
 			| TR3 | TR4 | TR5 | TR6 | TR7
 
@@ -5406,12 +5523,17 @@ tc_gen_reloc (section, fixp)
     done by calling parse_register) and eliminate immediate left recursion
     to implement a recursive-descent parser.
 
-    expr	SHORT e05
-		| e05
+    expr	SHORT e04
+		| e04
+
+    e04		e05 e04'
+
+    e04'	addOp e05 e04'
+		| Empty
 
     e05		e06 e05'
 
-    e05'	addOp e06 e05'
+    e05'	binOp e06 e05'
 		| Empty
 
     e06		e09 e06'
@@ -5420,6 +5542,8 @@ tc_gen_reloc (section, fixp)
 		| Empty
 
     e09		OFFSET e10 e09'
+		| ~ e10
+		| NOT e10
 		| e10 e09'
 
     e09'	PTR e10 e09'
@@ -5436,13 +5560,15 @@ tc_gen_reloc (section, fixp)
 		| BYTE
 		| WORD
 		| DWORD
+		| FWORD
 		| QWORD
-		| XWORD
+		| TBYTE
+		| OWORD
+		| XMMWORD
 		| .
 		| $
 		| register
 		| id
-		| ~
 		| constant  */
 
 /* Parsing structure for the intel syntax parser. Used to implement the
@@ -5476,21 +5602,26 @@ static struct intel_token cur_token, prev_token;
 #define T_REG		2
 #define T_BYTE		3
 #define T_WORD		4
-#define	T_DWORD		5
-#define T_QWORD		6
-#define T_XWORD		7
+#define T_DWORD		5
+#define T_FWORD		6
+#define T_QWORD		7
+#define T_TBYTE		8
+#define T_XMMWORD	9
 #undef  T_SHORT
-#define T_SHORT		8
-#define T_OFFSET	9
-#define T_PTR		10
-#define T_ID		11
-#define T_SHIFTOP	12
+#define T_SHORT		10
+#define T_OFFSET	11
+#define T_PTR		12
+#define T_ID		13
+#define T_SHL		14
+#define T_SHR		15
 
 /* Prototypes for intel parser functions.  */
 static int intel_match_token	PARAMS ((int code));
 static void intel_get_token	PARAMS ((void));
 static void intel_putback_token	PARAMS ((void));
 static int intel_expr		PARAMS ((void));
+static int intel_e04		PARAMS ((void));
+static int intel_e04_1		PARAMS ((void));
 static int intel_e05		PARAMS ((void));
 static int intel_e05_1		PARAMS ((void));
 static int intel_e06		PARAMS ((void));
@@ -5534,9 +5665,15 @@ i386_intel_operand (operand_string, got_a_float)
 
   if (ret)
     {
+      if (cur_token.code != T_NIL)
+	{
+	  as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
+		  current_templates->start->name, cur_token.str);
+	  ret = 0;
+	}
       /* If we found a memory reference, hand it over to i386_displacement
 	 to fill in the rest of the operand fields.  */
-      if (intel_parser.is_mem)
+      else if (intel_parser.is_mem)
 	{
 	  if ((i.mem_operands == 1
 	       && (current_templates->start->opcode_modifier & IsString) == 0)
@@ -5560,7 +5697,7 @@ i386_intel_operand (operand_string, got_a_float)
 	}
 
       /* Constant and OFFSET expressions are handled by i386_immediate.  */
-      else if (intel_parser.op_modifier == OFFSET_FLAT
+      else if (intel_parser.op_modifier == T_OFFSET
 	       || intel_parser.reg == NULL)
 	ret = i386_immediate (intel_parser.disp);
     }
@@ -5571,28 +5708,59 @@ i386_intel_operand (operand_string, got_a_float)
   return ret;
 }
 
-/* expr	SHORT e05
-	| e05  */
+/* expr	SHORT e04
+	| e04  */
 static int
 intel_expr ()
 {
-  /* expr  SHORT e05  */
+  /* expr  SHORT e04  */
   if (cur_token.code == T_SHORT)
     {
-      intel_parser.op_modifier = SHORT;
+      intel_parser.op_modifier = T_SHORT;
       intel_match_token (T_SHORT);
 
-      return (intel_e05 ());
+      return (intel_e04 ());
+    }
+
+  /* expr  e04  */
+  else
+    return intel_e04 ();
+}
+
+/* e04	e06 e04'
+
+   e04'	addOp e06 e04'
+	| Empty  */
+static int
+intel_e04 ()
+{
+  return (intel_e05 () && intel_e04_1 ());
+}
+
+static int
+intel_e04_1 ()
+{
+  /* e04'  addOp e05 e04'  */
+  if (cur_token.code == '+' || cur_token.code == '-')
+    {
+      char str[2];
+
+      str[0] = cur_token.code;
+      str[1] = 0;
+      strcat (intel_parser.disp, str);
+      intel_match_token (cur_token.code);
+
+      return (intel_e05 () && intel_e04_1 ());
     }
 
-  /* expr  e05  */
+  /* e04'  Empty  */
   else
-    return intel_e05 ();
+    return 1;
 }
 
 /* e05	e06 e05'
 
-   e05'	addOp e06 e05'
+   e05'	binOp e06 e05'
 	| Empty  */
 static int
 intel_e05 ()
@@ -5603,12 +5771,14 @@ intel_e05 ()
 static int
 intel_e05_1 ()
 {
-  /* e05'  addOp e06 e05'  */
-  if (cur_token.code == '+' || cur_token.code == '-'
-      || cur_token.code == '&' || cur_token.code == '|'
-      || cur_token.code == T_SHIFTOP)
+  /* e05'  binOp e06 e05'  */
+  if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
     {
-      strcat (intel_parser.disp, cur_token.str);
+      char str[2];
+
+      str[0] = cur_token.code;
+      str[1] = 0;
+      strcat (intel_parser.disp, str);
       intel_match_token (cur_token.code);
 
       return (intel_e06 () && intel_e05_1 ());
@@ -5633,9 +5803,27 @@ static int
 intel_e06_1 ()
 {
   /* e06'  mulOp e09 e06'  */
-  if (cur_token.code == '*' || cur_token.code == '/')
+  if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
     {
-      strcat (intel_parser.disp, cur_token.str);
+      char str[2];
+
+      str[0] = cur_token.code;
+      str[1] = 0;
+      strcat (intel_parser.disp, str);
+      intel_match_token (cur_token.code);
+
+      return (intel_e09 () && intel_e06_1 ());
+    }
+  else if (cur_token.code == T_SHL)
+    {
+      strcat (intel_parser.disp, "<<");
+      intel_match_token (cur_token.code);
+
+      return (intel_e09 () && intel_e06_1 ());
+    }
+  else if (cur_token.code == T_SHR)
+    {
+      strcat (intel_parser.disp, ">>");
       intel_match_token (cur_token.code);
 
       return (intel_e09 () && intel_e06_1 ());
@@ -5649,6 +5837,10 @@ intel_e06_1 ()
 /* e09	OFFSET e10 e09'
 	| e10 e09'
 
+   e09	~ e10 e09'
+	| NOT e10 e09'
+	| e10 e09'
+
    e09'	PTR e10 e09'
 	| : e10 e09'
 	| Empty */
@@ -5659,12 +5851,25 @@ intel_e09 ()
   if (cur_token.code == T_OFFSET)
     {
       intel_parser.is_mem = 0;
-      intel_parser.op_modifier = OFFSET_FLAT;
+      intel_parser.op_modifier = T_OFFSET;
       intel_match_token (T_OFFSET);
 
       return (intel_e10 () && intel_e09_1 ());
     }
 
+  /* e09  NOT e10 e09'  */
+  else if (cur_token.code == '~')
+    {
+      char str[2];
+
+      str[0] = cur_token.code;
+      str[1] = 0;
+      strcat (intel_parser.disp, str);
+      intel_match_token (cur_token.code);
+
+      return (intel_e10 () && intel_e09_1 ());
+    }
+
   /* e09  e10 e09'  */
   else
     return (intel_e10 () && intel_e09_1 ());
@@ -5676,35 +5881,76 @@ intel_e09_1 ()
   /* e09'  PTR e10 e09' */
   if (cur_token.code == T_PTR)
     {
+      char suffix;
+
       if (prev_token.code == T_BYTE)
-	i.suffix = BYTE_MNEM_SUFFIX;
+	suffix = BYTE_MNEM_SUFFIX;
 
       else if (prev_token.code == T_WORD)
 	{
-	  if (intel_parser.got_a_float == 2)	/* "fi..." */
-	    i.suffix = SHORT_MNEM_SUFFIX;
+	  if (current_templates->start->name[0] == 'l'
+	      && current_templates->start->name[2] == 's'
+	      && current_templates->start->name[3] == 0)
+	    suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+	  else if (intel_parser.got_a_float == 2)	/* "fi..." */
+	    suffix = SHORT_MNEM_SUFFIX;
 	  else
-	    i.suffix = WORD_MNEM_SUFFIX;
+	    suffix = WORD_MNEM_SUFFIX;
 	}
 
       else if (prev_token.code == T_DWORD)
 	{
-	  if (intel_parser.got_a_float == 1)	/* "f..." */
-	    i.suffix = SHORT_MNEM_SUFFIX;
+	  if (current_templates->start->name[0] == 'l'
+	      && current_templates->start->name[2] == 's'
+	      && current_templates->start->name[3] == 0)
+	    suffix = WORD_MNEM_SUFFIX;
+	  else if (flag_code == CODE_16BIT
+		   && (current_templates->start->opcode_modifier
+		       & (Jump|JumpDword|JumpInterSegment)))
+	    suffix = LONG_DOUBLE_MNEM_SUFFIX;
+	  else if (intel_parser.got_a_float == 1)	/* "f..." */
+	    suffix = SHORT_MNEM_SUFFIX;
 	  else
-	    i.suffix = LONG_MNEM_SUFFIX;
+	    suffix = LONG_MNEM_SUFFIX;
+	}
+
+      else if (prev_token.code == T_FWORD)
+	{
+	  if (current_templates->start->name[0] == 'l'
+	      && current_templates->start->name[2] == 's'
+	      && current_templates->start->name[3] == 0)
+	    suffix = LONG_MNEM_SUFFIX;
+	  else if (!intel_parser.got_a_float)
+	    {
+	      if (flag_code == CODE_16BIT)
+		add_prefix (DATA_PREFIX_OPCODE);
+	      suffix = LONG_DOUBLE_MNEM_SUFFIX;
+	    }
+	  else
+	    suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
 	}
 
       else if (prev_token.code == T_QWORD)
 	{
 	  if (intel_parser.got_a_float == 1)	/* "f..." */
-	    i.suffix = LONG_MNEM_SUFFIX;
+	    suffix = LONG_MNEM_SUFFIX;
 	  else
-	    i.suffix = QWORD_MNEM_SUFFIX;
+	    suffix = QWORD_MNEM_SUFFIX;
 	}
 
-      else if (prev_token.code == T_XWORD)
-	i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
+      else if (prev_token.code == T_TBYTE)
+	{
+	  if (intel_parser.got_a_float == 1)
+	    suffix = LONG_DOUBLE_MNEM_SUFFIX;
+	  else
+	    suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+	}
+
+      else if (prev_token.code == T_XMMWORD)
+	{
+	  /* XXX ignored for now, but accepted since gcc uses it */
+	  suffix = 0;
+	}
 
       else
 	{
@@ -5712,6 +5958,16 @@ intel_e09_1 ()
 	  return 0;
 	}
 
+      if (current_templates->start->base_opcode == 0x8d /* lea */)
+	;
+      else if (!i.suffix)
+	i.suffix = suffix;
+      else if (i.suffix != suffix)
+	{
+	  as_bad (_("Conflicting operand modifiers"));
+	  return 0;
+	}
+
       intel_match_token (T_PTR);
 
       return (intel_e10 () && intel_e09_1 ());
@@ -5722,7 +5978,7 @@ intel_e09_1 ()
     {
       /* Mark as a memory operand only if it's not already known to be an
 	 offset expression.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
+      if (intel_parser.op_modifier != T_OFFSET)
 	intel_parser.is_mem = 1;
 
       return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
@@ -5754,7 +6010,7 @@ intel_e10_1 ()
       /* Mark as a memory operand only if it's not already known to be an
 	 offset expression.  If it's an offset expression, we need to keep
 	 the brace in.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
+      if (intel_parser.op_modifier != T_OFFSET)
 	intel_parser.is_mem = 1;
       else
 	strcat (intel_parser.disp, "[");
@@ -5767,7 +6023,7 @@ intel_e10_1 ()
       if (intel_expr () && intel_match_token (']'))
 	{
 	  /* Preserve brackets when the operand is an offset expression.  */
-	  if (intel_parser.op_modifier == OFFSET_FLAT)
+	  if (intel_parser.op_modifier == T_OFFSET)
 	    strcat (intel_parser.disp, "]");
 
 	  return intel_e10_1 ();
@@ -5786,13 +6042,15 @@ intel_e10_1 ()
 	| BYTE
 	| WORD
 	| DWORD
+	| FWORD
 	| QWORD
-	| XWORD
+	| TBYTE
+	| OWORD
+	| XMMWORD
 	| $
 	| .
 	| register
 	| id
-	| ~
 	| constant  */
 static int
 intel_e11 ()
@@ -5812,15 +6070,6 @@ intel_e11 ()
 	return 0;
     }
 
-  /* e11 ~ expr */
-  else if (cur_token.code == '~')
-   {
-     strcat (intel_parser.disp, "~");
-     intel_match_token ('~');
-
-     return (intel_e11 ());
-   }
-
   /* e11  [ expr ] */
   else if (cur_token.code == '[')
     {
@@ -5829,16 +6078,14 @@ intel_e11 ()
       /* Mark as a memory operand only if it's not already known to be an
 	 offset expression.  If it's an offset expression, we need to keep
 	 the brace in.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
+      if (intel_parser.op_modifier != T_OFFSET)
 	intel_parser.is_mem = 1;
       else
 	strcat (intel_parser.disp, "[");
 
       /* Operands for jump/call inside brackets denote absolute addresses.  */
-      if (current_templates->start->opcode_modifier & Jump
-	  || current_templates->start->opcode_modifier & JumpDword
-	  || current_templates->start->opcode_modifier & JumpByte
-	  || current_templates->start->opcode_modifier & JumpInterSegment)
+      if (current_templates->start->opcode_modifier
+	  & (Jump|JumpDword|JumpByte|JumpInterSegment))
 	i.types[this_operand] |= JumpAbsolute;
 
       /* Add a '+' to the displacement string if necessary.  */
@@ -5849,7 +6096,7 @@ intel_e11 ()
       if (intel_expr () && intel_match_token (']'))
 	{
 	  /* Preserve brackets when the operand is an offset expression.  */
-	  if (intel_parser.op_modifier == OFFSET_FLAT)
+	  if (intel_parser.op_modifier == T_OFFSET)
 	    strcat (intel_parser.disp, "]");
 
 	  return 1;
@@ -5861,13 +6108,18 @@ intel_e11 ()
   /* e11  BYTE
 	  | WORD
 	  | DWORD
+	  | FWORD
 	  | QWORD
-	  | XWORD  */
+	  | TBYTE
+	  | OWORD
+	  | XMMWORD  */
   else if (cur_token.code == T_BYTE
 	   || cur_token.code == T_WORD
 	   || cur_token.code == T_DWORD
+	   || cur_token.code == T_FWORD
 	   || cur_token.code == T_QWORD
-	   || cur_token.code == T_XWORD)
+	   || cur_token.code == T_TBYTE
+	   || cur_token.code == T_XMMWORD)
     {
       intel_match_token (cur_token.code);
 
@@ -5876,14 +6128,14 @@ intel_e11 ()
 
   /* e11  $
 	  | .  */
-  else if (cur_token.code == '$' || cur_token.code == '.')
+  else if (cur_token.code == '.')
     {
       strcat (intel_parser.disp, cur_token.str);
       intel_match_token (cur_token.code);
 
       /* Mark as a memory operand only if it's not already known to be an
 	 offset expression.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
+      if (intel_parser.op_modifier != T_OFFSET)
 	intel_parser.is_mem = 1;
 
       return 1;
@@ -5980,7 +6232,7 @@ intel_e11 ()
 
       /* Offset modifier. Add the register to the displacement string to be
 	 parsed as an immediate expression after we're done.  */
-      else if (intel_parser.op_modifier == OFFSET_FLAT)
+      else if (intel_parser.op_modifier == T_OFFSET)
 	strcat (intel_parser.disp, reg->reg_name);
 
       /* It's neither base nor index nor offset.  */
@@ -5995,7 +6247,7 @@ intel_e11 ()
 	 when we're parsing offset operands), we may need to remove any
 	 preceding '+' from the displacement string.  */
       if (*intel_parser.disp != '\0'
-	  && intel_parser.op_modifier != OFFSET_FLAT)
+	  && intel_parser.op_modifier != T_OFFSET)
 	{
 	  char *s = intel_parser.disp;
 	  s += strlen (s) - 1;
@@ -6011,13 +6263,19 @@ intel_e11 ()
     {
       /* Add the identifier to the displacement string.  */
       strcat (intel_parser.disp, cur_token.str);
-      intel_match_token (T_ID);
 
       /* The identifier represents a memory reference only if it's not
-	 preceded by an offset modifier.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
-	intel_parser.is_mem = 1;
+	 preceded by an offset modifier and if it's not an equate.  */
+      if (intel_parser.op_modifier != T_OFFSET)
+	{
+	  symbolS *symbolP;
+
+	  symbolP = symbol_find(cur_token.str);
+	  if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
+	    intel_parser.is_mem = 1;
+	}
 
+      intel_match_token (T_ID);
       return 1;
     }
 
@@ -6183,22 +6441,6 @@ intel_get_token ()
 	new_token.code = T_ID;
     }
 
-  else if (strchr ("<>", *intel_parser.op_string)
-	   && *intel_parser.op_string == *(intel_parser.op_string + 1))
-    {
-      new_token.code = T_SHIFTOP;
-      new_token.str[0] = *intel_parser.op_string;
-      new_token.str[1] = *intel_parser.op_string;
-      new_token.str[2] = '\0';
-    }
-
-  else if (strchr ("+-/*&|:[]()~", *intel_parser.op_string))
-    {
-      new_token.code = *intel_parser.op_string;
-      new_token.str[0] = *intel_parser.op_string;
-      new_token.str[1] = '\0';
-    }
-
   else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
 	   && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
     {
@@ -6223,8 +6465,8 @@ intel_get_token ()
 	 Otherwise, it's operator '.' followed by an expression.  */
       if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
 	{
-	  new_token.code = *q;
-	  new_token.str[0] = *q;
+	  new_token.code = '.';
+	  new_token.str[0] = '.';
 	  new_token.str[1] = '\0';
 	}
       else
@@ -6233,7 +6475,28 @@ intel_get_token ()
 	    *p++ = *q++;
 	  *p = '\0';
 
-	  if (strcasecmp (new_token.str, "BYTE") == 0)
+	  if (strcasecmp (new_token.str, "NOT") == 0)
+	    new_token.code = '~';
+
+	  else if (strcasecmp (new_token.str, "MOD") == 0)
+	    new_token.code = '%';
+
+	  else if (strcasecmp (new_token.str, "AND") == 0)
+	    new_token.code = '&';
+
+	  else if (strcasecmp (new_token.str, "OR") == 0)
+	    new_token.code = '|';
+
+	  else if (strcasecmp (new_token.str, "XOR") == 0)
+	    new_token.code = '^';
+
+	  else if (strcasecmp (new_token.str, "SHL") == 0)
+	    new_token.code = T_SHL;
+
+	  else if (strcasecmp (new_token.str, "SHR") == 0)
+	    new_token.code = T_SHR;
+
+	  else if (strcasecmp (new_token.str, "BYTE") == 0)
 	    new_token.code = T_BYTE;
 
 	  else if (strcasecmp (new_token.str, "WORD") == 0)
@@ -6242,11 +6505,20 @@ intel_get_token ()
 	  else if (strcasecmp (new_token.str, "DWORD") == 0)
 	    new_token.code = T_DWORD;
 
+	  else if (strcasecmp (new_token.str, "FWORD") == 0)
+	    new_token.code = T_FWORD;
+
 	  else if (strcasecmp (new_token.str, "QWORD") == 0)
 	    new_token.code = T_QWORD;
 
-	  else if (strcasecmp (new_token.str, "XWORD") == 0)
-	    new_token.code = T_XWORD;
+	  else if (strcasecmp (new_token.str, "TBYTE") == 0
+		   /* XXX remove (gcc still uses it) */
+		   || strcasecmp (new_token.str, "XWORD") == 0)
+	    new_token.code = T_TBYTE;
+
+	  else if (strcasecmp (new_token.str, "XMMWORD") == 0
+		   || strcasecmp (new_token.str, "OWORD") == 0)
+	    new_token.code = T_XMMWORD;
 
 	  else if (strcasecmp (new_token.str, "PTR") == 0)
 	    new_token.code = T_PTR;
@@ -6274,6 +6546,22 @@ intel_get_token ()
 	}
     }
 
+  else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
+    {
+      new_token.code = *intel_parser.op_string;
+      new_token.str[0] = *intel_parser.op_string;
+      new_token.str[1] = '\0';
+    }
+
+  else if (strchr ("<>", *intel_parser.op_string)
+	   && *intel_parser.op_string == *(intel_parser.op_string + 1))
+    {
+      new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
+      new_token.str[0] = *intel_parser.op_string;
+      new_token.str[1] = *intel_parser.op_string;
+      new_token.str[2] = '\0';
+    }
+
   else
     as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
 
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index d5d0ca8..3b377cc 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -141,18 +141,6 @@ extern const char extra_symbol_chars[];
 
 #define END_OF_INSN '\0'
 
-/* Intel Syntax */
-/* Values 0-4 map onto scale factor */
-#define BYTE_PTR     0
-#define WORD_PTR     1
-#define DWORD_PTR    2
-#define QWORD_PTR    3
-#define XWORD_PTR    4
-#define SHORT        5
-#define OFFSET_FLAT  6
-#define FLAT         7
-#define NONE_FOUND   8
-
 typedef struct
 {
   /* instruction name sans width suffix ("mov" for movl insns) */
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 9ee7fb9..fd8f478 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+	* gas/i386/i386.exp: Execute new tests intelbad and intelok.
+	* gas/i386/intelbad.[sl]: New test to check for various things not
+	permitted in Intel mode.
+	* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
+	Adjust for change to segment register store.
+	* gas/i386/intelok.[sd]: New test to check various Intel mode specific
+	things get handled correctly.
+	* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
+	'high' and 'low' parts of an operand, which the parser previously
+	accepted while neither telling that it's not supported nor that it
+	ignored the remainder of the line following these supposed keywords.
+
 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 
 	* gas/crx/cop_insn.d: Regenerate (after a bug fix in Assembler).
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 2fe7ffb..1846268 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -47,6 +47,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "opcode"
     run_dump_test "intel"
     run_dump_test "intel16"
+    run_list_test "intelbad" ""
+    run_dump_test "intelok"
     run_dump_test "prefix"
     run_dump_test "amd"
     run_dump_test "katmai"
diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index 66fd1d7..24f4536 100644
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -480,151 +480,152 @@ Disassembly of section .text:
  7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,0x90909090\(%eax\)
  7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,0x90909090\(%eax\)
  7cc:	66 8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dx
- 7d3:	66 8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
- 7da:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
- 7e1:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
- 7e8:	66 91 [ 	]*xchg   %ax,%cx
- 7ea:	66 92 [ 	]*xchg   %ax,%dx
- 7ec:	66 93 [ 	]*xchg   %ax,%bx
- 7ee:	66 94 [ 	]*xchg   %ax,%sp
- 7f0:	66 95 [ 	]*xchg   %ax,%bp
- 7f2:	66 96 [ 	]*xchg   %ax,%si
- 7f4:	66 97 [ 	]*xchg   %ax,%di
- 7f6:	66 98 [ 	]*cbtw   
- 7f8:	66 99 [ 	]*cwtd   
- 7fa:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
- 800:	66 9c [ 	]*pushfw 
- 802:	66 9d [ 	]*popfw  
- 804:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
- 80a:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
- 810:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
- 812:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
- 814:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
- 818:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
- 81a:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
- 81c:	66 af [ 	]*scas   %es:\(%edi\),%ax
- 81e:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
- 822:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
- 826:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
- 82a:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
- 82e:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
- 832:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
- 836:	66 be 90 90 [ 	]*mov    \$0x9090,%si
- 83a:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
- 83e:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
- 846:	66 c2 90 90 [ 	]*retw   \$0x9090
- 84a:	66 c3 [ 	]*retw   
- 84c:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
- 853:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
- 85a:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
- 863:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
- 868:	66 c9 [ 	]*leavew 
- 86a:	66 ca 90 90 [ 	]*lretw  \$0x9090
- 86e:	66 cb [ 	]*lretw  
- 870:	66 cf [ 	]*iretw  
- 872:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
- 879:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
- 880:	66 e5 90 [ 	]*in     \$0x90,%ax
- 883:	66 e7 90 [ 	]*out    %ax,\$0x90
- 886:	66 e8 8f 90 [ 	]*callw  (0x)?9919.*
- 88a:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
- 890:	66 ed [ 	]*in     \(%dx\),%ax
- 892:	66 ef [ 	]*out    %ax,\(%dx\)
- 894:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
- 89b:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
- 8a2:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
- 8aa:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
- 8b2:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
- 8ba:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
- 8c2:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
- 8ca:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
- 8d2:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
- 8da:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
- 8e2:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
- 8ea:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
- 8f2:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
- 8fa:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
- 902:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
- 90a:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
- 912:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
- 91a:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
- 922:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
- 92a:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
- 932:	66 0f a0 [ 	]*pushw  %fs
- 935:	66 0f a1 [ 	]*popw   %fs
- 938:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
- 940:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
- 949:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
- 951:	66 0f a8 [ 	]*pushw  %gs
- 954:	66 0f a9 [ 	]*popw   %gs
- 957:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
- 95f:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
- 968:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
- 970:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
- 978:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
- 980:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
- 988:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
- 990:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
- 998:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
- 9a0:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
- 9a8:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
- 9b0:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
- 9b8:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
- 9c0:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
- 9c8:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 7d3:	8c 90 90 90 90 90 [ 	]*mov[l ]   %ss,0x90909090\(%eax\)
+ 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
+ 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
+ 7e7:	66 91 [ 	]*xchg   %ax,%cx
+ 7e9:	66 92 [ 	]*xchg   %ax,%dx
+ 7eb:	66 93 [ 	]*xchg   %ax,%bx
+ 7ed:	66 94 [ 	]*xchg   %ax,%sp
+ 7ef:	66 95 [ 	]*xchg   %ax,%bp
+ 7f1:	66 96 [ 	]*xchg   %ax,%si
+ 7f3:	66 97 [ 	]*xchg   %ax,%di
+ 7f5:	66 98 [ 	]*cbtw   
+ 7f7:	66 99 [ 	]*cwtd   
+ 7f9:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
+ 7ff:	66 9c [ 	]*pushfw 
+ 801:	66 9d [ 	]*popfw  
+ 803:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
+ 809:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
+ 80f:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
+ 811:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
+ 813:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
+ 817:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
+ 819:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
+ 81b:	66 af [ 	]*scas   %es:\(%edi\),%ax
+ 81d:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
+ 821:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
+ 825:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
+ 829:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
+ 82d:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
+ 831:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
+ 835:	66 be 90 90 [ 	]*mov    \$0x9090,%si
+ 839:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
+ 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
+ 845:	66 c2 90 90 [ 	]*retw   \$0x9090
+ 849:	66 c3 [ 	]*retw   
+ 84b:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
+ 852:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
+ 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
+ 862:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
+ 867:	66 c9 [ 	]*leavew 
+ 869:	66 ca 90 90 [ 	]*lretw  \$0x9090
+ 86d:	66 cb [ 	]*lretw  
+ 86f:	66 cf [ 	]*iretw  
+ 871:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
+ 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
+ 87f:	66 e5 90 [ 	]*in     \$0x90,%ax
+ 882:	66 e7 90 [ 	]*out    %ax,\$0x90
+ 885:	66 e8 8f 90 [ 	]*callw  (0x)?9918.*
+ 889:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
+ 88f:	66 ed [ 	]*in     \(%dx\),%ax
+ 891:	66 ef [ 	]*out    %ax,\(%dx\)
+ 893:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
+ 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
+ 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
+ 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
+ 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
+ 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
+ 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
+ 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
+ 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
+ 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
+ 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
+ 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
+ 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
+ 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
+ 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
+ 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
+ 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
+ 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
+ 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
+ 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
+ 931:	66 0f a0 [ 	]*pushw  %fs
+ 934:	66 0f a1 [ 	]*popw   %fs
+ 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
+ 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
+ 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
+ 950:	66 0f a8 [ 	]*pushw  %gs
+ 953:	66 0f a9 [ 	]*popw   %gs
+ 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
+ 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
+ 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
+ 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
+ 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
+ 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
+ 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
+ 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
+ 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
+ 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
+ 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
+ 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
+ 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
+ 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
+ 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
 
-0+9d0 <gs_foo>:
- 9d0:	c3 [ 	]*ret    
+0+9cf <gs_foo>:
+ 9cf:	c3 [ 	]*ret    
 
-0+9d1 <short_foo>:
- 9d1:	c3 [ 	]*ret    
+0+9d0 <short_foo>:
+ 9d0:	c3 [ 	]*ret    
 
-0+9d2 <bar>:
- 9d2:	e8 f9 ff ff ff [ 	]*call   9d0 <gs_foo>
- 9d7:	e8 f5 ff ff ff [ 	]*call   9d1 <short_foo>
- 9dc:	dd 1c d0 [ 	]*fstpl  \(%eax,%edx,8\)
- 9df:	b9 00 00 00 00 [ 	]*mov    \$0x0,%ecx
- 9e4:	88 04 16 [ 	]*mov    %al,\(%esi,%edx,1\)
- 9e7:	88 04 32 [ 	]*mov    %al,\(%edx,%esi,1\)
- 9ea:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
- 9ed:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
- 9f0:	eb 0c [ 	]*jmp    9fe <rot5>
- 9f2:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
- 9f3:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
- 9fb:	83 e0 f8 [ 	]*and    \$0xfffffff8,%eax
+0+9d1 <bar>:
+ 9d1:	e8 f9 ff ff ff [ 	]*call   9cf <gs_foo>
+ 9d6:	e8 f5 ff ff ff [ 	]*call   9d0 <short_foo>
+ 9db:	dd 1c d0 [ 	]*fstpl  \(%eax,%edx,8\)
+ 9de:	b9 00 00 00 00 [ 	]*mov    \$0x0,%ecx
+ 9e3:	88 04 16 [ 	]*mov    %al,\(%esi,%edx,1\)
+ 9e6:	88 04 32 [ 	]*mov    %al,\(%edx,%esi,1\)
+ 9e9:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
+ 9ec:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
+ 9ef:	eb 0c [ 	]*jmp    9fd <rot5>
+ 9f1:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
+ 9f2:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 9fa:	83 e0 f8 [ 	]*and    \$0xfffffff8,%eax
 
-0+9fe <rot5>:
- 9fe:	8b 44 ce 04 [ 	]*mov    0x4\(%esi,%ecx,8\),%eax
- a02:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
- a03:	0c 90 [ 	]*or     \$0x90,%al
- a05:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
- a0a:	0e [ 	]*push   %cs
- a0b:	8b 04 5d 00 00 00 00 [ 	]*mov    0x0\(,%ebx,2\),%eax
- a12:	10 14 85 90 90 90 90 [ 	]*adc    %dl,0x90909090\(,%eax,4\)
- a19:	2f [ 	]*das    
- a1a:	ea 90 90 90 90 90 90 [ 	]*ljmp   \$0x9090,\$0x90909090
- a21:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
- a23:	70 90 [ 	]*jo     9b5 <foo\+0x9b5>
- a25:	75 fe [ 	]*jne    a25 <rot5\+0x27>
- a27:	0f 6f 35 28 00 00 00 [ 	]*movq   0x28,%mm6
- a2e:	03 3c c3 [ 	]*add    \(%ebx,%eax,8\),%edi
- a31:	0f 6e 44 c3 04 [ 	]*movd   0x4\(%ebx,%eax,8\),%mm0
- a36:	03 bc cb 00 80 00 00 [ 	]*add    0x8000\(%ebx,%ecx,8\),%edi
- a3d:	0f 6e 8c cb 04 80 00 00 [ 	]*movd   0x8004\(%ebx,%ecx,8\),%mm1
- a45:	0f 6e 94 c3 04 00 01 00 [ 	]*movd   0x10004\(%ebx,%eax,8\),%mm2
- a4d:	03 bc c3 00 00 01 00 [ 	]*add    0x10000\(%ebx,%eax,8\),%edi
- a54:	66 8b 04 43 [ 	]*mov    \(%ebx,%eax,2\),%ax
- a58:	66 8b 8c 4b 00 20 00 00 [ 	]*mov    0x2000\(%ebx,%ecx,2\),%cx
- a60:	66 8b 84 43 00 40 00 00 [ 	]*mov    0x4000\(%ebx,%eax,2\),%ax
- a68:	ff e0 [ 	]*jmp    \*%eax
- a6a:	ff 20 [ 	]*jmp    \*\(%eax\)
- a6c:	ff 25 d2 09 00 00 [ 	]*jmp    \*0x9d2
- a72:	e9 5b ff ff ff [ 	]*jmp    9d2 <bar>
- a77:	b8 12 00 00 00 [ 	]*mov    \$0x12,%eax
- a7c:	25 ff ff fb ff [ 	]*and    \$0xfffbffff,%eax
- a81:	25 ff ff fb ff [ 	]*and    \$0xfffbffff,%eax
- a86:	b0 11 [ 	]*mov    \$0x11,%al
- a88:	b0 11 [ 	]*mov    \$0x11,%al
- a8a:	b3 47 [ 	]*mov    \$0x47,%bl
- a8c:	b3 47 [ 	]*mov    \$0x47,%bl
+0+9fd <rot5>:
+ 9fd:	8b 44 ce 04 [ 	]*mov    0x4\(%esi,%ecx,8\),%eax
+ a01:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
+ a02:	0c 90 [ 	]*or     \$0x90,%al
+ a04:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
+ a09:	0e [ 	]*push   %cs
+ a0a:	8b 04 5d 00 00 00 00 [ 	]*mov    0x0\(,%ebx,2\),%eax
+ a11:	10 14 85 90 90 90 90 [ 	]*adc    %dl,0x90909090\(,%eax,4\)
+ a18:	2f [ 	]*das    
+ a19:	ea 90 90 90 90 90 90 [ 	]*ljmp   \$0x9090,\$0x90909090
+ a20:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
+ a22:	70 90 [ 	]*jo     9b4 <foo\+0x9b4>
+ a24:	75 fe [ 	]*jne    a24 <rot5\+0x27>
+ a26:	0f 6f 35 28 00 00 00 [ 	]*movq   0x28,%mm6
+ a2d:	03 3c c3 [ 	]*add    \(%ebx,%eax,8\),%edi
+ a30:	0f 6e 44 c3 04 [ 	]*movd   0x4\(%ebx,%eax,8\),%mm0
+ a35:	03 bc cb 00 80 00 00 [ 	]*add    0x8000\(%ebx,%ecx,8\),%edi
+ a3c:	0f 6e 8c cb 04 80 00 00 [ 	]*movd   0x8004\(%ebx,%ecx,8\),%mm1
+ a44:	0f 6e 94 c3 04 00 01 00 [ 	]*movd   0x10004\(%ebx,%eax,8\),%mm2
+ a4c:	03 bc c3 00 00 01 00 [ 	]*add    0x10000\(%ebx,%eax,8\),%edi
+ a53:	66 8b 04 43 [ 	]*mov    \(%ebx,%eax,2\),%ax
+ a57:	66 8b 8c 4b 00 20 00 00 [ 	]*mov    0x2000\(%ebx,%ecx,2\),%cx
+ a5f:	66 8b 84 43 00 40 00 00 [ 	]*mov    0x4000\(%ebx,%eax,2\),%ax
+ a67:	ff e0 [ 	]*jmp    \*%eax
+ a69:	ff 20 [ 	]*jmp    \*\(%eax\)
+ a6b:	ff 25 d1 09 00 00 [ 	]*jmp    \*0x9d1
+ a71:	e9 5b ff ff ff [ 	]*jmp    9d1 <bar>
+ a76:	b8 12 00 00 00 [ 	]*mov    \$0x12,%eax
+ a7b:	25 ff ff fb ff [ 	]*and    \$0xfffbffff,%eax
+ a80:	25 ff ff fb ff [ 	]*and    \$0xfffbffff,%eax
+ a85:	b0 11 [ 	]*mov    \$0x11,%al
+ a87:	b0 11 [ 	]*mov    \$0x11,%al
+ a89:	b3 47 [ 	]*mov    \$0x47,%bl
+ a8b:	b3 47 [ 	]*mov    \$0x47,%bl
+ a8d:	00 00 .*
 [ 	]*...
diff --git a/gas/testsuite/gas/i386/intelbad.l b/gas/testsuite/gas/i386/intelbad.l
new file mode 100644
index 0000000..45c21d2
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelbad.l
@@ -0,0 +1,61 @@
+.*: Assembler messages:
+.*:4: (Warning|Error): .*
+.*:5: Error: .*
+.*:6: Error: .*
+.*:7: Error: .*
+.*:10: Error: .*
+.*:13: Error: .*
+.*:15: Error: .*
+.*:18: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:40: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:50: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:56: (Warning|Error): .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:59: Error: .*
+.*:60: Error: .*
+.*:61: Error: .*
+.*:62: Error: .*
+.*:67: Error: .*
+.*:73: Error: .*
+.*:74: Error: .*
+.*:75: Error: .*
+.*:77: Error: .*
+.*:78: Error: .*
+.*:89: Error: .*
+.*:90: Error: .*
+.*:91: Error: .*
diff --git a/gas/testsuite/gas/i386/intelbad.s b/gas/testsuite/gas/i386/intelbad.s
new file mode 100644
index 0000000..c4b03f3
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelbad.s
@@ -0,0 +1,91 @@
+	.intel_syntax noprefix
+	.text
+start:
+	add	eax, byte ptr [eax]
+	add	eax, qword ptr [eax]
+	add	[eax], 1
+	add	qword ptr [eax], 1
+	addpd	xmm0, dword ptr [eax]
+	addpd	xmm0, qword ptr [eax]
+	addpd	xmm0, tbyte ptr [eax]
+	addps	xmm0, dword ptr [eax]
+	addps	xmm0, qword ptr [eax]
+	addps	xmm0, tbyte ptr [eax]
+	addsd	xmm0, dword ptr [eax]
+	addsd	xmm0, tbyte ptr [eax]
+	addsd	xmm0, xmmword ptr [eax]
+	addss	xmm0, qword ptr [eax]
+	addss	xmm0, tbyte ptr [eax]
+	addss	xmm0, xmmword ptr [eax]
+	call	byte ptr [eax]
+	call	qword ptr [eax]
+	call	tbyte ptr [eax]
+	call	xword ptr [eax]
+	cmps	[esi], es:[edi]
+	cmps	dword ptr [esi], word ptr es:[edi]
+	cmpxchg8b dword ptr [eax]
+	fadd	[eax]
+	fadd	word ptr [eax]
+	fadd	tbyte ptr [eax]
+	fbld	byte ptr [eax]
+	fbld	word ptr [eax]
+	fbstp	dword ptr [eax]
+	fbstp	qword ptr [eax]
+	fiadd	[eax]
+	fiadd	byte ptr [eax]
+	fild	[eax]
+	fild	byte ptr [eax]
+	fild	tbyte ptr [eax]
+	fist	[eax]
+	fist	byte ptr [eax]
+	fist	qword ptr [eax]
+	fistp	[eax]
+	fistp	byte ptr [eax]
+	fisttp	[eax]
+	fisttp	byte ptr [eax]
+	fld	[eax]
+	fld	word ptr [eax]
+	fldcw	dword ptr [eax]
+	fst	[eax]
+	fst	word ptr [eax]
+	fst	tbyte ptr [eax]
+	fstp	[eax]
+	fstp	word ptr [eax]
+	ins	es:[edi], dx
+	lds	ax, word ptr [eax]
+	lds	eax, dword ptr [eax]
+	lods	[esi]
+	movs	es:[edi], [esi]
+	movs	dword ptr es:[edi], word ptr [esi]
+	movsx	eax, [eax]
+	movsx	eax, dword ptr [eax]
+	outs	dx, [esi]
+	paddb	mm0, dword ptr [eax]
+	paddb	mm0, xmmword ptr [eax]
+	paddb	xmm0, dword ptr [eax]
+	paddb	xmm0, qword ptr [eax]
+	pinsrw	mm0, byte ptr [eax], 3
+	pinsrw	mm0, dword ptr [eax], 3
+	pinsrw	mm0, qword ptr [eax], 3
+	pinsrw	xmm0, dword ptr [eax], 7
+	pinsrw	xmm0, qword ptr [eax], 7
+	pinsrw	xmm0, xmmword ptr [eax], 7
+	push	byte ptr [eax]
+	push	qword ptr [eax]
+	scas	es:[edi]
+#XXX?	shl	eax
+	stos	es:[edi]
+	xlat	word ptr [ebx]
+#XXX?	xlatb	[ebx]
+
+	# expressions
+#XXX?	push	~ 1
+#XXX?	push	1 % 1
+#XXX?	push	1 << 1
+#XXX?	push	1 >> 1
+#XXX?	push	1 & 1
+#XXX?	push	1 ^ 1
+#XXX?	push	1 | 1
+	push	1 1
+	push	1 +
+	push	1 * * 1
diff --git a/gas/testsuite/gas/i386/intelok.d b/gas/testsuite/gas/i386/intelok.d
new file mode 100644
index 0000000..186c73c
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelok.d
@@ -0,0 +1,105 @@
+#as: -J
+#objdump: -dwMintel
+#name: i386 intel-ok
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <start>:
+[ 	]*[0-9a-f]+:[ 	]+02 00[ 	]+add[ 	]+al,(BYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	02 00[ 	]+add[ 	]+al,(BYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 03 00[ 	]+add[ 	]+ax,(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 03 00[ 	]+add[ 	]+ax,(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	03 00[ 	]+add[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	03 00[ 	]+add[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	80 00 01[ 	]+add[ 	]+BYTE PTR \[eax\],0x1
+[ 	]*[0-9a-f]+:	83 00 01[ 	]+add[ 	]+DWORD PTR \[eax\],0x1
+[ 	]*[0-9a-f]+:	66 83 00 01[ 	]+add[ 	]+WORD PTR \[eax\],0x1
+[ 	]*[0-9a-f]+:	66 0f 58 00[ 	]+addpd[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	66 0f 58 00[ 	]+addpd[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f 58 00[ 	]+addps[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f 58 00[ 	]+addps[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f2 0f 58 00[ 	]+addsd[ 	]+xmm0,QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f2 0f 58 00[ 	]+addsd[ 	]+xmm0,QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f3 0f 58 00[ 	]+addss[ 	]+xmm0,DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f3 0f 58 00[ 	]+addss[ 	]+xmm0,DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	66 ff 10[ 	]+call[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	ff 10[ 	]+call[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	ff 18[ 	]+call[ 	]+FWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	a6[ 	]+cmps[ 	]+(BYTE PTR )(ds:)?\[esi\],(\1)?es:\[edi\]
+[ 	]*[0-9a-f]+:	a7[ 	]+cmps[ 	]+(DWORD PTR )(ds:)?\[esi\],(\1)?es:\[edi\]
+[ 	]*[0-9a-f]+:	66 a7[ 	]+cmps[ 	]+(WORD PTR )(ds:)?\[esi\],(\1)?es:\[edi\]
+[ 	]*[0-9a-f]+:	0f c7 08[ 	]+cmpxchg8b[ 	]+(QWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	d8 00[ 	]+fadd[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dc 00[ 	]+fadd[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 20[ 	]+fbld[ 	]+(TBYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	df 30[ 	]+fbstp[ 	]+(TBYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	da 00[ 	]+fiadd[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	de 00[ 	]+fiadd[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 00[ 	]+fild[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 28[ 	]+fild[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 00[ 	]+fild[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 10[ 	]+fist[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 10[ 	]+fist[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 18[ 	]+fistp[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 38[ 	]+fistp[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 18[ 	]+fistp[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 08[ 	]+fisttp[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 08[ 	]+fisttp[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 08[ 	]+fisttp[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	d9 00[ 	]+fld[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 00[ 	]+fld[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 28[ 	]+fld[ 	]+TBYTE PTR \[eax\]
+[ 	]*[0-9a-f]+:	d9 28[ 	]+fldcw[ 	]+(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	d9 20[ 	]+fldenvd?[ 	]+\[eax\]
+[ 	]*[0-9a-f]+:	d9 20[ 	]+fldenvd?[ 	]+\[eax\]
+[ 	]*[0-9a-f]+:	66 d9 20[ 	]+fldenvw[ 	]+\[eax\]
+[ 	]*[0-9a-f]+:	d9 10[ 	]+fst[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 10[ 	]+fst[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	d9 18[ 	]+fstp[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 18[ 	]+fstp[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 38[ 	]+fstp[ 	]+TBYTE PTR \[eax\]
+[ 	]*[0-9a-f]+:	66 c5 00[ 	]+lds[ 	]+ax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	c5 00[ 	]+lds[ 	]+eax,(FWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 c5 00[ 	]+lds[ 	]+ax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	c5 00[ 	]+lds[ 	]+eax,(FWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	0f 01 10[ 	]+lgdtd?[ 	]+(PWORD PTR)?\[eax\]
+[ 	]*[0-9a-f]+:	0f 01 10[ 	]+lgdtd?[ 	]+(PWORD PTR)?\[eax\]
+[ 	]*[0-9a-f]+:	66 0f 01 10[ 	]+lgdtw[ 	]+(PWORD PTR)?\[eax\]
+[ 	]*[0-9a-f]+:	a4[ 	]+movs[ 	]+(BYTE PTR )es:\[edi\],(\1)?(ds:)?\[esi\]
+[ 	]*[0-9a-f]+:	a5[ 	]+movs[ 	]+(DWORD PTR )es:\[edi\],(\1)?(ds:)?\[esi\]
+[ 	]*[0-9a-f]+:	66 a5[ 	]+movs[ 	]+(WORD PTR )es:\[edi\],(\1)?(ds:)?\[esi\]
+[ 	]*[0-9a-f]+:	0f be 00[ 	]+movsx[ 	]+eax,BYTE PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f bf 00[ 	]+movsx[ 	]+eax,WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f fc 00[ 	]+paddb[ 	]+mm0,(QWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	0f fc 00[ 	]+paddb[ 	]+mm0,(QWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 0f fc 00[ 	]+paddb[ 	]+xmm0,(XMMWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 0f fc 00[ 	]+paddb[ 	]+xmm0,(XMMWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	0f c4 00 03[ 	]+pinsrw[ 	]+mm0,(WORD PTR )?\[eax\],0x3
+[ 	]*[0-9a-f]+:	66 0f c4 00 07[ 	]+pinsrw[ 	]+xmm0,(WORD PTR )?\[eax\],0x7
+[ 	]*[0-9a-f]+:	ff 30[ 	]+push[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
+[ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
+[ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a ff[ 	]+push[ 	]+0xffffffff
+[ 	]*[0-9a-f]+:	6a fe[ 	]+push[ 	]+0xfffffffe
+[ 	]*[0-9a-f]+:	6a 02[ 	]+push[ 	]+0x2
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 04[ 	]+push[ 	]+0x4
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 08[ 	]+push[ 	]+0x8
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 02[ 	]+push[ 	]+0x2
+[ 	]*[0-9a-f]+:	6a 03[ 	]+push[ 	]+0x3
+[ 	]*[0-9a-f]+:	6a 0d[ 	]+push[ 	]+0xd
diff --git a/gas/testsuite/gas/i386/intelok.s b/gas/testsuite/gas/i386/intelok.s
new file mode 100644
index 0000000..04fedbc
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelok.s
@@ -0,0 +1,105 @@
+	.intel_syntax noprefix
+	.text
+start:
+	add	al, [eax]
+	add	al, byte ptr [eax]
+	add	ax, [eax]
+	add	ax, word ptr [eax]
+	add	eax, [eax]
+	add	eax, dword ptr [eax]
+	add	byte ptr [eax], 1
+	add	dword ptr [eax], 1
+	add	word ptr [eax], 1
+	addpd	xmm0, [eax]
+	addpd	xmm0, xmmword ptr [eax]
+	addps	xmm0, [eax]
+	addps	xmm0, xmmword ptr [eax]
+	addsd	xmm0, [eax]
+	addsd	xmm0, qword ptr [eax]
+	addss	xmm0, [eax]
+	addss	xmm0, dword ptr [eax]
+	call	word ptr [eax]
+	call	dword ptr [eax]
+	call	fword ptr [eax]
+	cmps	[esi], byte ptr es:[edi]
+	cmps	dword ptr [esi], es:[edi]
+	cmps	word ptr [esi], word ptr es:[edi]
+	cmpxchg8b qword ptr [eax]
+	fadd	dword ptr [eax]
+	fadd	qword ptr [eax]
+	fbld	[eax]
+#XXX	fbld	tbyte ptr [eax]
+	fbstp	[eax]
+#XXX	fbstp	tbyte ptr [eax]
+	fiadd	dword ptr [eax]
+	fiadd	word ptr [eax]
+	fild	dword ptr [eax]
+	fild	qword ptr [eax]
+	fild	word ptr [eax]
+	fist	dword ptr [eax]
+	fist	word ptr [eax]
+	fistp	dword ptr [eax]
+	fistp	qword ptr [eax]
+	fistp	word ptr [eax]
+	fisttp	dword ptr [eax]
+	fisttp	qword ptr [eax]
+	fisttp	word ptr [eax]
+	fld	dword ptr [eax]
+	fld	qword ptr [eax]
+	fld	tbyte ptr [eax]
+	fldcw	[eax]
+#XXX	fldcw	word ptr [eax]
+	fldenv	[eax]
+	fldenvd	[eax]
+	fldenvw	[eax]
+	fst	dword ptr [eax]
+	fst	qword ptr [eax]
+	fstp	dword ptr [eax]
+	fstp	qword ptr [eax]
+	fstp	tbyte ptr [eax]
+	lds	ax, [eax]
+	lds	eax, [eax]
+	lds	ax, dword ptr [eax]
+	lds	eax, fword ptr [eax]
+	lea	eax, [eax]
+	lea	eax, byte ptr [eax]
+	lea	eax, dword ptr [eax]
+	lea	eax, fword ptr [eax]
+	lea	eax, qword ptr [eax]
+	lea	eax, tbyte ptr [eax]
+	lea	eax, word ptr [eax]
+	lea	eax, xmmword ptr [eax]
+	lgdt	[eax]
+	lgdtd	[eax]
+	lgdtw	[eax]
+	movs	es:[edi], byte ptr [esi]
+	movs	dword ptr es:[edi], [esi]
+	movs	word ptr es:[edi], word ptr [esi]
+	movsx	eax, byte ptr [eax]
+	movsx	eax, word ptr [eax]
+	paddb	mm0, [eax]
+	paddb	mm0, qword ptr [eax]
+	paddb	xmm0, [eax]
+	paddb	xmm0, xmmword ptr [eax]
+	pinsrw	mm0, word ptr [eax], 3
+	pinsrw	xmm0, word ptr [eax], 7
+	push	dword ptr [eax]
+	xlat	[ebx]
+	xlat	byte ptr [ebx]
+	xlatb
+
+	# expressions
+
+	push	+ 1
+	push	- 1
+	push	not 1
+	push	1 + 1
+	push	2 - 1
+	push	2 * 2
+	push	3 / 2
+	push	3 mod 2
+	push	4 shl 1
+	push	5 shr 2
+	push	6 and 3
+	push	7 xor 4
+	push	8 or 5
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index dac75a8..2c2d451 100644
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -1,6 +1,6 @@
 #as: -J
 #objdump: -dw
-#name: i386 opcode
+#name: i386 intel
 
 .*: +file format .*
 
@@ -480,95 +480,95 @@ Disassembly of section .text:
  7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,0x90909090\(%eax\)
  7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,0x90909090\(%eax\)
  7cc:	66 8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dx
- 7d3:	66 8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
- 7da:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
- 7e1:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
- 7e8:	66 91 [ 	]*xchg   %ax,%cx
- 7ea:	66 92 [ 	]*xchg   %ax,%dx
- 7ec:	66 93 [ 	]*xchg   %ax,%bx
- 7ee:	66 94 [ 	]*xchg   %ax,%sp
- 7f0:	66 95 [ 	]*xchg   %ax,%bp
- 7f2:	66 96 [ 	]*xchg   %ax,%si
- 7f4:	66 97 [ 	]*xchg   %ax,%di
- 7f6:	66 98 [ 	]*cbtw   
- 7f8:	66 99 [ 	]*cwtd   
- 7fa:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
- 800:	66 9c [ 	]*pushfw 
- 802:	66 9d [ 	]*popfw  
- 804:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
- 80a:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
- 810:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
- 812:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
- 814:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
- 818:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
- 81a:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
- 81c:	66 af [ 	]*scas   %es:\(%edi\),%ax
- 81e:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
- 822:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
- 826:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
- 82a:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
- 82e:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
- 832:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
- 836:	66 be 90 90 [ 	]*mov    \$0x9090,%si
- 83a:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
- 83e:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
- 846:	66 c2 90 90 [ 	]*retw   \$0x9090
- 84a:	66 c3 [ 	]*retw   
- 84c:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
- 853:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
- 85a:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
- 863:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
- 868:	66 c9 [ 	]*leavew 
- 86a:	66 ca 90 90 [ 	]*lretw  \$0x9090
- 86e:	66 cb [ 	]*lretw  
- 870:	66 cf [ 	]*iretw  
- 872:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
- 879:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
- 880:	66 e5 90 [ 	]*in     \$0x90,%ax
- 883:	66 e7 90 [ 	]*out    %ax,\$0x90
- 886:	66 e8 8f 90 [ 	]*callw  (0x)?9919.*
- 88a:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
- 890:	66 ed [ 	]*in     \(%dx\),%ax
- 892:	66 ef [ 	]*out    %ax,\(%dx\)
- 894:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
- 89b:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
- 8a2:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
- 8aa:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
- 8b2:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
- 8ba:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
- 8c2:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
- 8ca:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
- 8d2:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
- 8da:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
- 8e2:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
- 8ea:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
- 8f2:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
- 8fa:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
- 902:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
- 90a:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
- 912:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
- 91a:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
- 922:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
- 92a:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
- 932:	66 0f a0 [ 	]*pushw  %fs
- 935:	66 0f a1 [ 	]*popw   %fs
- 938:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
- 940:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
- 949:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
- 951:	66 0f a8 [ 	]*pushw  %gs
- 954:	66 0f a9 [ 	]*popw   %gs
- 957:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
- 95f:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
- 968:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
- 970:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
- 978:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
- 980:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
- 988:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
- 990:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
- 998:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
- 9a0:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
- 9a8:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
- 9b0:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
- 9b8:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
- 9c0:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
- 9c8:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 7d3:	8c 90 90 90 90 90 [ 	]*mov[l ]   %ss,0x90909090\(%eax\)
+ 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
+ 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
+ 7e7:	66 91 [ 	]*xchg   %ax,%cx
+ 7e9:	66 92 [ 	]*xchg   %ax,%dx
+ 7eb:	66 93 [ 	]*xchg   %ax,%bx
+ 7ed:	66 94 [ 	]*xchg   %ax,%sp
+ 7ef:	66 95 [ 	]*xchg   %ax,%bp
+ 7f1:	66 96 [ 	]*xchg   %ax,%si
+ 7f3:	66 97 [ 	]*xchg   %ax,%di
+ 7f5:	66 98 [ 	]*cbtw   
+ 7f7:	66 99 [ 	]*cwtd   
+ 7f9:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
+ 7ff:	66 9c [ 	]*pushfw 
+ 801:	66 9d [ 	]*popfw  
+ 803:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
+ 809:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
+ 80f:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
+ 811:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
+ 813:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
+ 817:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
+ 819:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
+ 81b:	66 af [ 	]*scas   %es:\(%edi\),%ax
+ 81d:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
+ 821:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
+ 825:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
+ 829:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
+ 82d:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
+ 831:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
+ 835:	66 be 90 90 [ 	]*mov    \$0x9090,%si
+ 839:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
+ 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
+ 845:	66 c2 90 90 [ 	]*retw   \$0x9090
+ 849:	66 c3 [ 	]*retw   
+ 84b:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
+ 852:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
+ 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
+ 862:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
+ 867:	66 c9 [ 	]*leavew 
+ 869:	66 ca 90 90 [ 	]*lretw  \$0x9090
+ 86d:	66 cb [ 	]*lretw  
+ 86f:	66 cf [ 	]*iretw  
+ 871:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
+ 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
+ 87f:	66 e5 90 [ 	]*in     \$0x90,%ax
+ 882:	66 e7 90 [ 	]*out    %ax,\$0x90
+ 885:	66 e8 8f 90 [ 	]*callw  (0x)?9918.*
+ 889:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
+ 88f:	66 ed [ 	]*in     \(%dx\),%ax
+ 891:	66 ef [ 	]*out    %ax,\(%dx\)
+ 893:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
+ 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
+ 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
+ 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
+ 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
+ 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
+ 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
+ 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
+ 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
+ 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
+ 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
+ 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
+ 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
+ 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
+ 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
+ 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
+ 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
+ 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
+ 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
+ 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
+ 931:	66 0f a0 [ 	]*pushw  %fs
+ 934:	66 0f a1 [ 	]*popw   %fs
+ 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
+ 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
+ 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
+ 950:	66 0f a8 [ 	]*pushw  %gs
+ 953:	66 0f a9 [ 	]*popw   %gs
+ 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
+ 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
+ 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
+ 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
+ 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
+ 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
+ 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
+ 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
+ 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
+ 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
+ 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
+ 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
+ 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
+ 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
+ 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index 58155e2..671876d 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -7,269 +7,272 @@
 Disassembly of section .text:
 
 0+000 <.text>:
-[	 ]*0:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
-[	 ]*3:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
-[	 ]*5:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
-[	 ]*8:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
-[	 ]*a:[	 ]+cb[	 ]+lret[	 ]*(#.*)*
-[	 ]*b:[	 ]+c3[	 ]+retq[	 ]*(#.*)*
-[	 ]*c:[	 ]+cf[	 ]+iret[	 ]*(#.*)*
-[	 ]*d:[	 ]+66 cf[	 ]+iretw[	 ]*(#.*)*
-[	 ]*f:[	 ]+48 cf[	 ]+iretq[	 ]*(#.*)*
-[	 ]*11:[	 ]+66 41 8c 08[	 ]+movw[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
-[	 ]*15:[	 ]+66 8c 08[	 ]+movw[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
-[	 ]*18:[	 ]+66 41 8c 10[	 ]+movw[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
-[	 ]*1c:[	 ]+66 8c 10[	 ]+movw[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
-[	 ]*1f:[	 ]+66 41 8c 20[	 ]+movw[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
-[	 ]*23:[	 ]+66 8c 20[	 ]+movw[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
-[	 ]*26:[	 ]+41 8c 08[	 ]+movl[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
-[	 ]*29:[	 ]+8c 08[	 ]+movl[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
-[	 ]*2b:[	 ]+41 8c 10[	 ]+movl[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
-[	 ]*2e:[	 ]+8c 10[	 ]+movl[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
-[	 ]*30:[	 ]+41 8c 20[	 ]+movl[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
-[	 ]*33:[	 ]+8c 20[	 ]+movl[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
-[	 ]*35:[	 ]+41 8e 10[	 ]+movl[	 ]+\(%r8\),%ss[	 ]*(#.*)*
-[	 ]*38:[	 ]+8e 10[	 ]+movl[	 ]+\(%rax\),%ss[	 ]*(#.*)*
-[	 ]*3a:[	 ]+41 8e 20[	 ]+movl[	 ]+\(%r8\),%fs[	 ]*(#.*)*
-[	 ]*3d:[	 ]+8e 20[	 ]+movl[	 ]+\(%rax\),%fs[	 ]*(#.*)*
-[	 ]*3f:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
-[	 ]*43:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
-[	 ]*46:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
-[	 ]*4c:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
-[	 ]*51:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
-[	 ]*58:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*5e:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
-[	 ]*62:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
-[	 ]*65:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
-[	 ]*6b:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
-[	 ]*70:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*76:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
-[	 ]*7a:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
-[	 ]*7d:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
-[	 ]*83:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
-[	 ]*88:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
-[	 ]*8f:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*95:[	 ]+49 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
-[	 ]*9c:[	 ]+48 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*a3:[	 ]+41 0f c3 00[	 ]+movnti[	 ]+%eax,\(%r8\)[	 ]*(#.*)*
-[	 ]*a7:[	 ]+0f c3 00[	 ]+movnti[	 ]+%eax,\(%rax\)[	 ]*(#.*)*
-[	 ]*aa:[	 ]+49 0f c3 00[	 ]+movnti[	 ]+%rax,\(%r8\)[	 ]*(#.*)*
-[	 ]*ae:[	 ]+48 0f c3 00[	 ]+movnti[	 ]+%rax,\(%rax\)[	 ]*(#.*)*
-[	 ]*b2:[	 ]+4d 0f c3 00[	 ]+movnti[	 ]+%r8,\(%r8\)[	 ]*(#.*)*
-[	 ]*b6:[	 ]+4c 0f c3 00[	 ]+movnti[	 ]+%r8,\(%rax\)[	 ]*(#.*)*
-[	 ]*ba:[	 ]+41 f6 38[	 ]+idivb[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*bd:[	 ]+f6 38[	 ]+idivb[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*bf:[	 ]+66 41 f7 38[	 ]+idivw[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*c3:[	 ]+66 f7 38[	 ]+idivw[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*c6:[	 ]+41 f7 38[	 ]+idivl[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*c9:[	 ]+f7 38[	 ]+idivl[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*cb:[	 ]+49 f7 38[	 ]+idivq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*ce:[	 ]+48 f7 38[	 ]+idivq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*d1:[	 ]+41 f6 28[	 ]+imulb[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*d4:[	 ]+f6 28[	 ]+imulb[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*d6:[	 ]+66 41 f7 28[	 ]+imulw[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*da:[	 ]+66 f7 28[	 ]+imulw[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*dd:[	 ]+41 f7 28[	 ]+imull[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*e0:[	 ]+f7 28[	 ]+imull[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*e2:[	 ]+49 f7 28[	 ]+imulq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*e5:[	 ]+48 f7 28[	 ]+imulq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*e8:[	 ]+66 41 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*ed:[	 ]+66 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*f1:[	 ]+66 45 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*f6:[	 ]+66 44 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*fb:[	 ]+66 45 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*100:[	 ]+66 44 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*105:[	 ]+66 41 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*10a:[	 ]+66 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*10e:[	 ]+66 0f 58 c0[	 ]+addpd[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
-[	 ]*112:[	 ]+66 45 0f 58 ff[	 ]+addpd[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
-[	 ]*117:[	 ]+66 45 0f 58 c7[	 ]+addpd[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
-[	 ]*11c:[	 ]+f2 49 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*121:[	 ]+f2 48 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*126:[	 ]+f2 4d 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*12b:[	 ]+f2 4c 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*130:[	 ]+f2 48 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*135:[	 ]+f2 4d 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*13a:[	 ]+f2 49 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*13f:[	 ]+f2 4d 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*144:[	 ]+f2 49 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*149:[	 ]+f2 4c 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*14e:[	 ]+f2 48 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*153:[	 ]+f2 4c 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*158:[	 ]+f2 49 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*15d:[	 ]+f2 48 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*162:[	 ]+f2 4d 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*167:[	 ]+f2 4c 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*16c:[	 ]+f2 48 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*171:[	 ]+f2 4d 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*176:[	 ]+f2 49 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*17b:[	 ]+f2 4d 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*180:[	 ]+f2 49 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*185:[	 ]+f2 4c 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*18a:[	 ]+f2 48 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*18f:[	 ]+f2 4c 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*194:[	 ]+f3 49 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*199:[	 ]+f3 48 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*19e:[	 ]+f3 4d 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*1a3:[	 ]+f3 4c 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*1a8:[	 ]+f3 48 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*1ad:[	 ]+f3 4d 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*1b2:[	 ]+f3 49 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*1b7:[	 ]+f3 4d 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*1bc:[	 ]+f3 49 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*1c1:[	 ]+f3 4c 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*1c6:[	 ]+f3 48 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*1cb:[	 ]+f3 4c 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*1d0:[	 ]+f3 49 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*1d5:[	 ]+f3 48 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*1da:[	 ]+f3 4d 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*1df:[	 ]+f3 4c 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*1e4:[	 ]+f3 48 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*1e9:[	 ]+f3 4d 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*1ee:[	 ]+f3 49 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*1f3:[	 ]+f3 4d 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*1f8:[	 ]+f3 49 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*1fd:[	 ]+f3 4c 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*202:[	 ]+f3 48 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*207:[	 ]+f3 4c 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*20c:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*211:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*215:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*21a:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*21f:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*224:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*229:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*22e:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*232:[	 ]+f3 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm0[	 ]*(#.*)*
-[	 ]*236:[	 ]+f3 44 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm15[	 ]*(#.*)*
-[	 ]*23b:[	 ]+f3 44 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm8[	 ]*(#.*)*
-[	 ]*240:[	 ]+f3 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm7[	 ]*(#.*)*
-[	 ]*244:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*249:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*24d:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*252:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*257:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*25c:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*261:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*266:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*26a:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*26f:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*273:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*278:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*27d:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*282:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*287:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*28c:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*290:[	 ]+f2 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm0[	 ]*(#.*)*
-[	 ]*294:[	 ]+f2 44 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm15[	 ]*(#.*)*
-[	 ]*299:[	 ]+f2 44 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm8[	 ]*(#.*)*
-[	 ]*29e:[	 ]+f2 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm7[	 ]*(#.*)*
-[	 ]*2a2:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*2a7:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*2ab:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*2b0:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*2b5:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*2ba:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*2bf:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*2c4:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*2c8:[	 ]+66 41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*2cd:[	 ]+66 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*2d1:[	 ]+66 45 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*2d6:[	 ]+66 44 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*2db:[	 ]+66 45 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*2e0:[	 ]+66 44 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*2e5:[	 ]+66 41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*2ea:[	 ]+66 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*2ee:[	 ]+66 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm0[	 ]*(#.*)*
-[	 ]*2f2:[	 ]+66 44 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm15[	 ]*(#.*)*
-[	 ]*2f7:[	 ]+66 44 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm8[	 ]*(#.*)*
-[	 ]*2fc:[	 ]+66 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm7[	 ]*(#.*)*
-[	 ]*300:[	 ]+66 41 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*305:[	 ]+66 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*309:[	 ]+66 45 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
-[	 ]*30e:[	 ]+66 44 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
-[	 ]*313:[	 ]+66 45 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
-[	 ]*318:[	 ]+66 44 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
-[	 ]*31d:[	 ]+66 41 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*322:[	 ]+66 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%rax\)[	 ]*(#.*)*
-[	 ]*326:[	 ]+66 0f 7e c0[	 ]+movd[	 ]+%xmm0,%eax[	 ]*(#.*)*
-[	 ]*32a:[	 ]+66 44 0f 7e f8[	 ]+movd[	 ]+%xmm15,%eax[	 ]*(#.*)*
-[	 ]*32f:[	 ]+66 44 0f 7e c0[	 ]+movd[	 ]+%xmm8,%eax[	 ]*(#.*)*
-[	 ]*334:[	 ]+66 0f 7e f8[	 ]+movd[	 ]+%xmm7,%eax[	 ]*(#.*)*
-[	 ]*338:[	 ]+66 48 0f 6e c0[	 ]+movd[	 ]+%rax,%xmm0[	 ]*(#.*)*
-[	 ]*33d:[	 ]+66 49 0f 6e c0[	 ]+movd[	 ]+%r8,%xmm0[	 ]*(#.*)*
-[	 ]*342:[	 ]+66 4d 0f 6e f8[	 ]+movd[	 ]+%r8,%xmm15[	 ]*(#.*)*
-[	 ]*347:[	 ]+66 48 0f 7e c0[	 ]+movd[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*34c:[	 ]+66 49 0f 7e c0[	 ]+movd[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*351:[	 ]+66 49 0f 7e f8[	 ]+movd[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*356:[	 ]+f3 41 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*35b:[	 ]+f3 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*35f:[	 ]+f3 45 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*364:[	 ]+f3 44 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*369:[	 ]+f3 45 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*36e:[	 ]+f3 44 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*373:[	 ]+f3 41 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*378:[	 ]+f3 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*37c:[	 ]+f3 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
-[	 ]*380:[	 ]+f3 45 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
-[	 ]*385:[	 ]+f3 45 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
-[	 ]*38a:[	 ]+f3 41 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm7[	 ]*(#.*)*
-[	 ]*38f:[	 ]+f3 41 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm0[	 ]*(#.*)*
-[	 ]*394:[	 ]+f3 45 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm15[	 ]*(#.*)*
-[	 ]*399:[	 ]+f3 45 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm8[	 ]*(#.*)*
-[	 ]*39e:[	 ]+f3 41 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm7[	 ]*(#.*)*
-[	 ]*3a3:[	 ]+f3 41 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm0[	 ]*(#.*)*
-[	 ]*3a8:[	 ]+f3 44 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm15[	 ]*(#.*)*
-[	 ]*3ad:[	 ]+f3 44 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm8[	 ]*(#.*)*
-[	 ]*3b2:[	 ]+f3 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm7[	 ]*(#.*)*
-[	 ]*3b6:[	 ]+f3 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm0[	 ]*(#.*)*
-[	 ]*3ba:[	 ]+f3 44 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm15[	 ]*(#.*)*
-[	 ]*3bf:[	 ]+f3 44 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm8[	 ]*(#.*)*
-[	 ]*3c4:[	 ]+f3 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm7[	 ]*(#.*)*
-[	 ]*3c8:[	 ]+66 41 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*3cd:[	 ]+66 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*3d1:[	 ]+66 45 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
-[	 ]*3d6:[	 ]+66 44 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
-[	 ]*3db:[	 ]+66 45 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
-[	 ]*3e0:[	 ]+66 44 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
-[	 ]*3e5:[	 ]+66 41 0f d6 38[	 ]+movq[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*3ea:[	 ]+41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
-[	 ]*3ee:[	 ]+0f 6e 00[	 ]+movd[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
-[	 ]*3f1:[	 ]+41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
-[	 ]*3f5:[	 ]+0f 6e 38[	 ]+movd[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
-[	 ]*3f8:[	 ]+0f 6e c0[	 ]+movd[	 ]+%eax,%mm0[	 ]*(#.*)*
-[	 ]*3fb:[	 ]+0f 6e f8[	 ]+movd[	 ]+%eax,%mm7[	 ]*(#.*)*
-[	 ]*3fe:[	 ]+41 0f 7e 00[	 ]+movd[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*402:[	 ]+0f 7e 00[	 ]+movd[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*405:[	 ]+41 0f 7e 38[	 ]+movd[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*409:[	 ]+0f 7e 38[	 ]+movd[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
-[	 ]*40c:[	 ]+0f 7e c0[	 ]+movd[	 ]+%mm0,%eax[	 ]*(#.*)*
-[	 ]*40f:[	 ]+0f 7e f8[	 ]+movd[	 ]+%mm7,%eax[	 ]*(#.*)*
-[	 ]*412:[	 ]+41 0f 6f 00[	 ]+movq[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
-[	 ]*416:[	 ]+0f 6f 00[	 ]+movq[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
-[	 ]*419:[	 ]+41 0f 6f 38[	 ]+movq[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
-[	 ]*41d:[	 ]+0f 6f 38[	 ]+movq[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
-[	 ]*420:[	 ]+41 0f 7f 00[	 ]+movq[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*424:[	 ]+0f 7f 00[	 ]+movq[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*427:[	 ]+41 0f 7f 38[	 ]+movq[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*42b:[	 ]+0f 7f 38[	 ]+movq[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
-[	 ]*42e:[	 ]+41 8f 00[	 ]+popq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*431:[	 ]+8f 00[	 ]+popq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*433:[	 ]+9d[	 ]+popfq[	 ]*(#.*)*
-[	 ]*434:[	 ]+41 ff 30[	 ]+pushq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*437:[	 ]+ff 30[	 ]+pushq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*439:[	 ]+9c[	 ]+pushfq[	 ]*(#.*)*
-[	 ]*43a:[	 ]+0f 77[	 ]+emms[	 ]*(#.*)*
-[	 ]*43c:[	 ]+0f 0e[	 ]+femms[	 ]*(#.*)*
-[	 ]*43e:[	 ]+0f 08[	 ]+invd[	 ]*(#.*)*
-[	 ]*440:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*444:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*447:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*44b:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*44e:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*452:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*455:[	 ]+0f 00 c0[	 ]+sldt[	 ]+%eax[	 ]*(#.*)*
-[	 ]*458:[	 ]+e6 00[	 ]+out[	 ]+%al,\$0[x0]*[	 ]*(#.*)*
-[	 ]*45a:[	 ]+66 e7 00[	 ]+out[	 ]+%ax,\$0[x0]*[	 ]*(#.*)*
-[	 ]*45d:[	 ]+e7 00[	 ]+out[	 ]+%eax,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+cb[	 ]+lret[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c3[	 ]+retq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+cf[	 ]+iret[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 cf[	 ]+iretw[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 cf[	 ]+iretq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 08[	 ]+movl?[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 08[	 ]+movl?[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 10[	 ]+movl?[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 10[	 ]+movl?[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 20[	 ]+movl?[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 20[	 ]+movl?[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 08[	 ]+movl?[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 08[	 ]+movl?[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 10[	 ]+movl?[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 10[	 ]+movl?[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 20[	 ]+movl?[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 20[	 ]+movl?[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8e 10[	 ]+movl?[	 ]+\(%r8\),%ss[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8e 10[	 ]+movl?[	 ]+\(%rax\),%ss[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8e 20[	 ]+movl?[	 ]+\(%r8\),%fs[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8e 20[	 ]+movl?[	 ]+\(%rax\),%fs[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f c3 00[	 ]+movnti[	 ]+%eax,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f c3 00[	 ]+movnti[	 ]+%eax,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 0f c3 00[	 ]+movnti[	 ]+%rax,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 0f c3 00[	 ]+movnti[	 ]+%rax,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+4d 0f c3 00[	 ]+movnti[	 ]+%r8,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+4c 0f c3 00[	 ]+movnti[	 ]+%r8,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f6 38[	 ]+idivb[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f6 38[	 ]+idivb[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 f7 38[	 ]+idivw[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 f7 38[	 ]+idivw[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f7 38[	 ]+idivl[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f7 38[	 ]+idivl[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 f7 38[	 ]+idivq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 f7 38[	 ]+idivq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f6 28[	 ]+imulb[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f6 28[	 ]+imulb[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 f7 28[	 ]+imulw[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 f7 28[	 ]+imulw[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f7 28[	 ]+imull[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f7 28[	 ]+imull[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 f7 28[	 ]+imulq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 f7 28[	 ]+imulq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 58 c0[	 ]+addpd[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 ff[	 ]+addpd[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 c7[	 ]+addpd[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e c0[	 ]+movd[	 ]+%xmm0,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e f8[	 ]+movd[	 ]+%xmm15,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e c0[	 ]+movd[	 ]+%xmm8,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e f8[	 ]+movd[	 ]+%xmm7,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 48 0f 6e c0[	 ]+movd[	 ]+%rax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 49 0f 6e c0[	 ]+movd[	 ]+%r8,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 4d 0f 6e f8[	 ]+movd[	 ]+%r8,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 48 0f 7e c0[	 ]+movd[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 49 0f 7e c0[	 ]+movd[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 49 0f 7e f8[	 ]+movd[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f d6 38[	 ]+movq[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e 00[	 ]+movd[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e 38[	 ]+movd[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e c0[	 ]+movd[	 ]+%eax,%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e f8[	 ]+movd[	 ]+%eax,%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7e 00[	 ]+movd[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e 00[	 ]+movd[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7e 38[	 ]+movd[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e 38[	 ]+movd[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e c0[	 ]+movd[	 ]+%mm0,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e f8[	 ]+movd[	 ]+%mm7,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6f 00[	 ]+movq[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6f 00[	 ]+movq[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6f 38[	 ]+movq[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6f 38[	 ]+movq[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7f 00[	 ]+movq[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7f 00[	 ]+movq[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7f 38[	 ]+movq[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7f 38[	 ]+movq[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8f 00[	 ]+popq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8f 00[	 ]+popq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+9d[	 ]+popfq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 ff 30[	 ]+pushq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+ff 30[	 ]+pushq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+9c[	 ]+pushfq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 77[	 ]+emms[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 0e[	 ]+femms[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 08[	 ]+invd[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 00 c0[	 ]+sldt[	 ]+%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+e6 00[	 ]+out[	 ]+%al,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 e7 00[	 ]+out[	 ]+%ax,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+e7 00[	 ]+out[	 ]+%eax,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
+[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
+[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
 [	 *]...
diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d
index dd4526b..07f45ec 100644
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -117,10 +117,8 @@ Disassembly of section .text:
  1d7:	66 b8 00 00[ 	]+mov[ 	]+\$0x0,%ax
  1db:	b8 00 00 00 00[ 	]+mov[ 	]+\$0x0,%eax
  1e0:	48 c7 c0 00 00 00 00 	mov[ 	]+\$0x0,%rax
- 1e7:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
- 1ee:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
- 1f5:	a1 00 00 00 00 00 00 00 00 	mov[ 	]+0x0,%eax
- 1fe:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
- 205:	8b 80 00 00 00 00[ 	]+mov[ 	]+0x0\(%rax\),%eax
- 20b:	8b 05 00 00 00 00[ 	]+mov[ 	]+0\(%rip\),%eax.*
+ 1e7:	a1 00 00 00 00 00 00 00 00 	mov[ 	]+0x0,%eax
+ 1f0:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
+ 1f7:	8b 80 00 00 00 00[ 	]+mov[ 	]+0x0\(%rax\),%eax
+ 1fd:	8b 05 00 00 00 00[ 	]+mov[ 	]+0\(%rip\),%eax.*
 	...
diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s
index d65054e..ad2a48d 100644
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -132,9 +132,9 @@ mov ax, flat symbol
 mov eax, flat symbol
 mov rax, flat symbol
 
-#parts
-mov eax, high part symbol
-mov eax, low part symbol
+#parts aren't supported by the parser
+#mov eax, high part symbol
+#mov eax, low part symbol
 
 #addressing modes
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4eb8348..e3bba46 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,19 @@
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+	* i386.h (sldx_Suf): Remove.
+	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
+	(q_FP): Define, implying no REX64.
+	(x_FP, sl_FP): Imply FloatMF.
+	(i386_optab): Split reg and mem forms of moving from segment registers
+	so that the memory forms can ignore the 16-/32-bit operand size
+	distinction. Adjust a few others for Intel mode. Remove *FP uses from
+	all non-floating-point instructions. Unite 32- and 64-bit forms of
+	movsx, movzx, and movd. Adjust floating point operations for the above
+	changes to the *FP macros. Add DefaultSize to floating point control
+	insns operating on larger memory ranges. Remove left over comments
+	hinting at certain insns being Intel-syntax ones where the ones
+	actually meant are already gone.
+
 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 
 	* crx.h: Add COPS_REG_INS - Coprocessor Special register
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 96bf149..cf95608 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -65,13 +65,13 @@ static const template i386_optab[] =
 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
 #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
-#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
 #define bwlq_Suf (No_sSuf|No_xSuf)
-#define FP (NoSuf|IgnoreSize)
-#define l_FP (l_Suf|IgnoreSize)
-#define x_FP (x_Suf|IgnoreSize)
-#define sl_FP (sl_Suf|IgnoreSize)
+#define FP (NoSuf)
+#define l_FP (l_Suf)
+#define q_FP (q_Suf|NoRex64)
+#define x_FP (x_Suf|FloatMF)
+#define sl_FP (sl_Suf|FloatMF)
 #if SYSV386_COMPAT
 /* Someone forgot that the FloatR bit reverses the operation when not
    equal to the FloatD bit.  ie. Changing only FloatD results in the
@@ -97,8 +97,10 @@ static const template i386_optab[] =
    size prefix.  When moving to a 32 bit register, the upper 16 bits
    are set to an implementation defined value (on the Pentium Pro,
    the implementation defined value is zero).  */
-{ "mov",   2,	0x8c, X, 0,	 wl_Suf|Modrm,			{ SReg2, WordReg|WordMem, 0 } },
-{ "mov",   2,	0x8c, X, Cpu386, wl_Suf|Modrm,			{ SReg3, WordReg|WordMem, 0 } },
+{ "mov",   2,	0x8c, X, 0,	 wl_Suf|Modrm,			{ SReg2, WordReg|InvMem, 0 } },
+{ "mov",   2,	0x8c, X, 0,	 wl_Suf|Modrm|IgnoreSize,	{ SReg2, WordMem, 0 } },
+{ "mov",   2,	0x8c, X, Cpu386, wl_Suf|Modrm,			{ SReg3, WordReg|InvMem, 0 } },
+{ "mov",   2,	0x8c, X, Cpu386, wl_Suf|Modrm|IgnoreSize,	{ SReg3, WordMem, 0 } },
 { "mov",   2,	0x8e, X, 0,	 wl_Suf|Modrm|IgnoreSize,	{ WordReg|WordMem, SReg2, 0 } },
 { "mov",   2,	0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize,	{ WordReg|WordMem, SReg3, 0 } },
 /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit
@@ -120,27 +122,25 @@ static const template i386_optab[] =
 {"movsbq", 2, 0x0fbe, X, Cpu64,  NoSuf|Modrm|Rex64,		{ Reg8|ByteMem, Reg64, 0} },
 {"movswq", 2, 0x0fbf, X, Cpu64,  NoSuf|Modrm|Rex64,		{ Reg16|ShortMem,Reg64, 0} },
 {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,		{ Reg32|WordMem, Reg64, 0} },
-/* Intel Syntax next 5 insns */
+/* Intel Syntax next 3 insns */
 {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
-{"movsx",  2, 0x0fbe, X, Cpu64,  b_Suf|Modrm|Rex64,		{ Reg8|ByteMem, Reg64, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|Rex64,		{ Reg16|ShortMem, Reg64, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,			{ Reg16|ShortMem, Reg32|Reg64, 0} },
 {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,		{ Reg32|WordMem, Reg64, 0} },
 
 /* Move with zero extend.  */
-{"movzb",  2, 0x0fb6, X, Cpu386, wl_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+/* "movzbl" & "movzbw" should not be unified into "movzb" for
+   consistency with the sign extending moves above.  */
+{"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,			{ Reg8|ByteMem, Reg32, 0} },
+{"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,			{ Reg8|ByteMem, Reg16, 0} },
 {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
-/* These instructions are not particulary usefull, since the zero extend
+/* These instructions are not particulary useful, since the zero extend
    32->64 is implicit, but we can encode them.  */
 {"movzbq", 2, 0x0fb6, X, Cpu64,  NoSuf|Modrm|Rex64,		{ Reg8|ByteMem,   Reg64, 0} },
 {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,		{ Reg16|ShortMem, Reg64, 0} },
-/* Intel Syntax next 4 insns */
+/* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful,
+   since the zero extend 32->64 is implicit, but we can encode them).  */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
-/* These instructions are not particulary usefull, since the zero extend
-   32->64 is implicit, but we can encode them.  */
-{"movzx",  2, 0x0fb6, X, Cpu64, b_Suf|Modrm|Rex64,		{ Reg8|ByteMem, Reg64, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu64, w_Suf|Modrm|Rex64,		{ Reg16|ShortMem, Reg64, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,			{ Reg16|ShortMem, Reg32|Reg64, 0} },
 
 /* Push instructions.  */
 {"push",   1,	0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
@@ -386,7 +386,7 @@ static const template i386_optab[] =
 /* Intel Syntax */
 {"call",   2,	0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
-{"call",   1,	0xff, 3, 0,	 x_Suf|Modrm|DefaultSize,	{WordMem, 0, 0} },
+{"call",   1,	0xff, 3, 0,	 x_Suf|Modrm|DefaultSize,	{WordMem|JumpAbsolute, 0, 0} },
 {"lcall",  2,	0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} },
 {"lcall",  1,	0xff, 3, 0,	 wl_Suf|Modrm|DefaultSize,	{WordMem|JumpAbsolute, 0, 0} },
 
@@ -397,7 +397,7 @@ static const template i386_optab[] =
 /* Intel Syntax.  */
 {"jmp",    2,	0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax.  */
-{"jmp",    1,	0xff, 5, 0,	 x_Suf|Modrm,		{ WordMem, 0, 0} },
+{"jmp",    1,	0xff, 5, 0,	 x_Suf|Modrm,		{ WordMem|JumpAbsolute, 0, 0} },
 {"ljmp",   2,	0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 {"ljmp",   1,	0xff, 5, 0,	 wl_Suf|Modrm,		{ WordMem|JumpAbsolute, 0, 0} },
 
@@ -591,32 +591,30 @@ static const template i386_optab[] =
 
 /* load */
 {"fld",	   1, 0xd9c0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fld",	   1,	0xd9, 0, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fld",	   1, 0xd9c0, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"fld",	   1,	0xd9, 0, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fld",	   1, 0xd9c0, X, 0,	 l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 /* Intel Syntax */
 {"fld",    1,	0xdb, 5, 0,	 x_FP|Modrm,		{ LLongMem, 0, 0} },
-{"fild",   1,	0xdf, 0, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
-/* Intel Syntax */
-{"fildq",  1,	0xdf, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fild",   1,	0xdf, 0, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
+{"fild",   1,	0xdf, 5, 0,	 q_FP|Modrm,		{ LLongMem, 0, 0} },
 {"fildll", 1,	0xdf, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 {"fldt",   1,	0xdb, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 {"fbld",   1,	0xdf, 4, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 
 /* store (no pop) */
 {"fst",	   1, 0xddd0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fst",	   1,	0xd9, 2, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fst",	   1, 0xddd0, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
-{"fist",   1,	0xdf, 2, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fst",	   1,	0xd9, 2, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fst",	   1, 0xddd0, X, 0,	 l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
+{"fist",   1,	0xdf, 2, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 /* store (with pop) */
 {"fstp",   1, 0xddd8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fstp",   1,	0xd9, 3, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fstp",   1, 0xddd8, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"fstp",   1,	0xd9, 3, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fstp",   1, 0xddd8, X, 0,	 l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 /* Intel Syntax */
 {"fstp",   1,	0xdb, 7, 0,	 x_FP|Modrm,		{ LLongMem, 0, 0} },
-{"fistp",  1,	0xdf, 3, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
-/* Intel Syntax */
-{"fistpq", 1,	0xdf, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistp",  1,	0xdf, 3, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
+{"fistp",  1,	0xdf, 7, 0,	 q_FP|Modrm,		{ LLongMem, 0, 0} },
 {"fistpll",1,	0xdf, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 {"fstpt",  1,	0xdb, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 {"fbstp",  1,	0xdf, 6, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
@@ -630,17 +628,17 @@ static const template i386_optab[] =
 {"fcom",   1, 0xd8d0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 /* alias for fcom %st(1) */
 {"fcom",   0, 0xd8d1, X, 0,	 FP,			{ 0, 0, 0} },
-{"fcom",   1,	0xd8, 2, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fcom",   1, 0xd8d0, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
-{"ficom",  1,	0xde, 2, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fcom",   1,	0xd8, 2, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fcom",   1, 0xd8d0, X, 0,	 l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
+{"ficom",  1,	0xde, 2, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 /* comparison (with pop) */
 {"fcomp",  1, 0xd8d8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 /* alias for fcomp %st(1) */
 {"fcomp",  0, 0xd8d9, X, 0,	 FP,			{ 0, 0, 0} },
-{"fcomp",  1,	0xd8, 3, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fcomp",  1, 0xd8d8, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
-{"ficomp", 1,	0xde, 3, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fcomp",  1,	0xd8, 3, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fcomp",  1, 0xd8d8, X, 0,	 l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
+{"ficomp", 1,	0xde, 3, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 {"fcompp", 0, 0xded9, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* unordered comparison (with pop) */
@@ -674,8 +672,8 @@ static const template i386_optab[] =
 /* alias for faddp */
 {"fadd",   0, 0xdec1, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fadd",   1,	0xd8, 0, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fiadd",  1,	0xde, 0, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fadd",   1,	0xd8, 0, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fiadd",  1,	0xde, 0, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 {"faddp",  2, 0xdec0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
 {"faddp",  1, 0xdec0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
@@ -690,8 +688,8 @@ static const template i386_optab[] =
 /* alias for fsubp */
 {"fsub",   0, 0xdee1, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fsub",   1,	0xd8, 4, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fisub",  1,	0xde, 4, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fsub",   1,	0xd8, 4, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fisub",  1,	0xde, 4, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
 {"fsubp",  2, 0xdee0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
@@ -713,8 +711,8 @@ static const template i386_optab[] =
 /* alias for fsubrp */
 {"fsubr",  0, 0xdee9, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fsubr",  1,	0xd8, 5, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fisubr", 1,	0xde, 5, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fsubr",  1,	0xd8, 5, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fisubr", 1,	0xde, 5, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
 {"fsubrp", 2, 0xdee8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
@@ -736,8 +734,8 @@ static const template i386_optab[] =
 /* alias for fmulp */
 {"fmul",   0, 0xdec9, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fmul",   1,	0xd8, 1, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fimul",  1,	0xde, 1, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fmul",   1,	0xd8, 1, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fimul",  1,	0xde, 1, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 {"fmulp",  2, 0xdec8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
 {"fmulp",  1, 0xdec8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
@@ -751,8 +749,8 @@ static const template i386_optab[] =
 /* alias for fdivp */
 {"fdiv",   0, 0xdef1, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fdiv",   1,	0xd8, 6, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fidiv",  1,	0xde, 6, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fdiv",   1,	0xd8, 6, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fidiv",  1,	0xde, 6, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
 {"fdivp",  2, 0xdef0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
@@ -774,8 +772,8 @@ static const template i386_optab[] =
 /* alias for fdivrp */
 {"fdivr",  0, 0xdef9, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fdivr",  1,	0xd8, 7, 0,	 sl_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fidivr", 1,	0xde, 7, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fdivr",  1,	0xd8, 7, 0,	 sl_FP|Modrm,		{ LongMem|LLongMem, 0, 0} },
+{"fidivr", 1,	0xde, 7, 0,	 sl_FP|Modrm,		{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
 {"fdivrp", 2, 0xdef8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
@@ -815,21 +813,23 @@ static const template i386_optab[] =
 {"fldcw",  1,	0xd9, 5, 0,	 FP|Modrm,		{ ShortMem, 0, 0} },
 {"fnstcw", 1,	0xd9, 7, 0,	 FP|Modrm,		{ ShortMem, 0, 0} },
 {"fstcw",  1,	0xd9, 7, 0,	 FP|FWait|Modrm,	{ ShortMem, 0, 0} },
-{"fnstsw", 1, 0xdfe0, X, 0,	 FP,			{ Acc, 0, 0} },
+/* XXX should reject %al, %eax, and %rax */
+{"fnstsw", 1, 0xdfe0, X, 0,	 FP|IgnoreSize,		{ Acc, 0, 0} },
 {"fnstsw", 1,	0xdd, 7, 0,	 FP|Modrm,		{ ShortMem, 0, 0} },
 {"fnstsw", 0, 0xdfe0, X, 0,	 FP,			{ 0, 0, 0} },
-{"fstsw",  1, 0xdfe0, X, 0,	 FP|FWait,		{ Acc, 0, 0} },
+/* XXX should reject %al, %eax, and %rax */
+{"fstsw",  1, 0xdfe0, X, 0,	 FP|FWait|IgnoreSize,	{ Acc, 0, 0} },
 {"fstsw",  1,	0xdd, 7, 0,	 FP|FWait|Modrm,	{ ShortMem, 0, 0} },
 {"fstsw",  0, 0xdfe0, X, 0,	 FP|FWait,		{ 0, 0, 0} },
 {"fnclex", 0, 0xdbe2, X, 0,	 FP,			{ 0, 0, 0} },
 {"fclex",  0, 0xdbe2, X, 0,	 FP|FWait,		{ 0, 0, 0} },
 /* Short forms of fldenv, fstenv use data size prefix.  */
-{"fnstenv",1,	0xd9, 6, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-{"fstenv", 1,	0xd9, 6, 0,	 sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
-{"fldenv", 1,	0xd9, 4, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-{"fnsave", 1,	0xdd, 6, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-{"fsave",  1,	0xdd, 6, 0,	 sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
-{"frstor", 1,	0xdd, 4, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fnstenv",1,	0xd9, 6, 0,	 sl_Suf|Modrm|DefaultSize,		{ LLongMem, 0, 0} },
+{"fstenv", 1,	0xd9, 6, 0,	 sl_Suf|FWait|Modrm|DefaultSize,	{ LLongMem, 0, 0} },
+{"fldenv", 1,	0xd9, 4, 0,	 sl_Suf|Modrm|DefaultSize,		{ LLongMem, 0, 0} },
+{"fnsave", 1,	0xdd, 6, 0,	 sl_Suf|Modrm|DefaultSize,		{ LLongMem, 0, 0} },
+{"fsave",  1,	0xdd, 6, 0,	 sl_Suf|FWait|Modrm|DefaultSize,	{ LLongMem, 0, 0} },
+{"frstor", 1,	0xdd, 4, 0,	 sl_Suf|Modrm|DefaultSize,		{ LLongMem, 0, 0} },
 
 {"ffree",  1, 0xddc0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 /* P6:free st(i), pop st */
@@ -896,7 +896,7 @@ static const template i386_optab[] =
 {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
 {"invd",    0, 0x0f08, X, Cpu486, NoSuf,		{ 0, 0, 0} },
 {"wbinvd",  0, 0x0f09, X, Cpu486, NoSuf,		{ 0, 0, 0} },
-{"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm,		{ AnyMem, 0, 0} },
+{"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} },
 
 /* 586 and late 486 extensions.  */
 {"cpuid",   0, 0x0fa2, X, Cpu486, NoSuf,		{ 0, 0, 0} },
@@ -905,7 +905,7 @@ static const template i386_optab[] =
 {"wrmsr",   0, 0x0f30, X, Cpu586, NoSuf,		{ 0, 0, 0} },
 {"rdtsc",   0, 0x0f31, X, Cpu586, NoSuf,		{ 0, 0, 0} },
 {"rdmsr",   0, 0x0f32, X, Cpu586, NoSuf,		{ 0, 0, 0} },
-{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm,		{ LLongMem, 0, 0} },
+{"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm,		{ LLongMem, 0, 0} },
 
 /* Pentium II/Pentium Pro extensions.  */
 {"sysenter",0, 0x0f34, X, Cpu686, NoSuf,		{ 0, 0, 0} },
@@ -979,30 +979,25 @@ static const template i386_optab[] =
 
 /* Pentium4 extensions.  */
 
-{"movnti",   2, 0x0fc3,    X, CpuP4, FP|Modrm,		{ WordReg, WordMem, 0 } },
-{"clflush",  1, 0x0fae,    7, CpuP4, FP|Modrm, 		{ ByteMem, 0, 0 } },
-{"lfence",   0, 0x0fae, 0xe8, CpuP4, FP|ImmExt,		{ 0, 0, 0 } },
-{"mfence",   0, 0x0fae, 0xf0, CpuP4, FP|ImmExt,		{ 0, 0, 0 } },
-{"pause",    0, 0xf390,    X, CpuP4, FP,		{ 0, 0, 0 } },
+{"movnti",   2, 0x0fc3,    X, CpuP4, wlq_Suf|Modrm,		{ WordReg, WordMem, 0 } },
+{"clflush",  1, 0x0fae,    7, CpuP4, NoSuf|Modrm|IgnoreSize,	{ ByteMem, 0, 0 } },
+{"lfence",   0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt,		{ 0, 0, 0 } },
+{"mfence",   0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt,		{ 0, 0, 0 } },
+{"pause",    0, 0xf390,    X, CpuP4, NoSuf,		{ 0, 0, 0 } },
 
 /* MMX/SSE2 instructions.  */
 
-{"emms",     0, 0x0f77, X, CpuMMX, FP,			{ 0, 0, 0 } },
-{"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,		{ Reg32|LongMem, RegMMX, 0 } },
-{"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,		{ RegMMX, Reg32|LongMem, 0 } },
-{"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,		{ Reg32|LLongMem, RegXMM, 0 } },
-{"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,		{ RegXMM, Reg32|LLongMem, 0 } },
-/* Real MMX instructions.  */
-{"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,		{ Reg64|LLongMem, RegMMX, 0 } },
-{"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,		{ RegMMX, Reg64|LLongMem, 0 } },
-{"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,		{ Reg64|LLongMem, RegXMM, 0 } },
-{"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,		{ RegXMM, Reg64|LLongMem, 0 } },
+{"emms",     0, 0x0f77, X, CpuMMX, NoSuf,			{ 0, 0, 0 } },
+{"movd",     2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } },
+{"movd",     2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } },
+{"movd",     2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } },
+{"movd",     2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } },
 /* In the 64bit mode the short form mov immediate is redefined to have
    64bit displacement value.  */
-{"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,		{ RegMMX, RegMMX|LongMem, 0 } },
-{"movq",     2, 0xf30f7e,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movq",     2, 0x660fd6,X,CpuSSE2,FP|Modrm,		{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movq",     2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"movq",     2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
+{"movq",     2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movq",     2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
 {"movq",   2,	0x88, X, Cpu64,	 NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
 {"movq",   2,	0xc6, 0, Cpu64,	 NoSuf|W|Modrm|Size64,	{ Imm32S, Reg64|WordMem, 0 } },
 {"movq",   2,	0xb0, X, Cpu64,	 NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
@@ -1010,362 +1005,362 @@ static const template i386_optab[] =
    mode they are 64bit.*/
 {"movq",   2, 0x0f20, X, Cpu64,	 NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
 {"movq",   2, 0x0f21, X, Cpu64,	 NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
-{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddb",    2, 0x0ffc, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddb",    2, 0x660ffc,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddw",    2, 0x0ffd, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddw",    2, 0x660ffd,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddd",    2, 0x0ffe, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddd",    2, 0x660ffe,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddq",    2, 0x0fd4, X, CpuMMX, FP|Modrm,		{ RegMMX|LLongMem, RegMMX, 0 } },
-{"paddq",    2, 0x660fd4,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddsb",   2, 0x0fec, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddsb",   2, 0x660fec,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddsw",   2, 0x0fed, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddsw",   2, 0x660fed,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddusb",  2, 0x0fdc, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddusb",  2, 0x660fdc,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"paddusw",  2, 0x0fdd, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddusw",  2, 0x660fdd,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pand",     2, 0x0fdb, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pand",     2, 0x660fdb,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pandn",    2, 0x0fdf, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pandn",    2, 0x660fdf,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpeqb",  2, 0x0f74, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqb",  2, 0x660f74,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpeqw",  2, 0x0f75, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqw",  2, 0x660f75,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpeqd",  2, 0x0f76, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqd",  2, 0x660f76,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpgtb",  2, 0x0f64, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtb",  2, 0x660f64,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpgtw",  2, 0x0f65, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtw",  2, 0x660f65,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpgtd",  2, 0x0f66, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtd",  2, 0x660f66,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pmaddwd",  2, 0x0ff5, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmaddwd",  2, 0x660ff5,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pmulhw",   2, 0x0fe5, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmulhw",   2, 0x660fe5,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pmullw",   2, 0x0fd5, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmullw",   2, 0x660fd5,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"por",	     2, 0x0feb, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"por",	     2, 0x660feb,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psllw",    2, 0x0ff1, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psllw",    2, 0x660ff1,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psllw",    2, 0x0f71, 6, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psllw",    2, 0x660f71,6,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"pslld",    2, 0x0ff2, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pslld",    2, 0x660ff2,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pslld",    2, 0x0f72, 6, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"pslld",    2, 0x660f72,6,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psllq",    2, 0x0ff3, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psllq",    2, 0x660ff3,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psllq",    2, 0x0f73, 6, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psllq",    2, 0x660f73,6,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psraw",    2, 0x0fe1, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psraw",    2, 0x660fe1,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psraw",    2, 0x0f71, 4, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psraw",    2, 0x660f71,4,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psrad",    2, 0x0fe2, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrad",    2, 0x660fe2,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psrad",    2, 0x0f72, 4, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrad",    2, 0x660f72,4,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psrlw",    2, 0x0fd1, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrlw",    2, 0x660fd1,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psrlw",    2, 0x0f71, 2, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrlw",    2, 0x660f71,2,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psrld",    2, 0x0fd2, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrld",    2, 0x660fd2,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psrld",    2, 0x0f72, 2, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrld",    2, 0x660f72,2,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psrlq",    2, 0x0fd3, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrlq",    2, 0x660fd3,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psrlq",    2, 0x0f73, 2, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrlq",    2, 0x660f73,2,CpuSSE2,FP|Modrm,		{ Imm8, RegXMM, 0 } },
-{"psubb",    2, 0x0ff8, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubb",    2, 0x660ff8,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubw",    2, 0x0ff9, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubw",    2, 0x660ff9,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubd",    2, 0x0ffa, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubd",    2, 0x660ffa,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubq",    2, 0x0ffb, X, CpuMMX, FP|Modrm,		{ RegMMX|LLongMem, RegMMX, 0 } },
-{"psubq",    2, 0x660ffb,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubsb",   2, 0x0fe8, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubsb",   2, 0x660fe8,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubsw",   2, 0x0fe9, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubsw",   2, 0x660fe9,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubusb",  2, 0x0fd8, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubusb",  2, 0x660fd8,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"psubusw",  2, 0x0fd9, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubusw",  2, 0x660fd9,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pxor",     2, 0x0fef, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pxor",     2, 0x660fef,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+/* Real MMX instructions.  */
+{"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddb",    2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddb",    2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddw",    2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddw",    2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddd",    2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddd",    2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddq",    2, 0x0fd4, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LLongMem, RegMMX, 0 } },
+{"paddq",    2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddsb",   2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddsb",   2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddsw",   2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddsw",   2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddusb",  2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddusb",  2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"paddusw",  2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddusw",  2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pand",     2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pand",     2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pandn",    2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pandn",    2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpeqb",  2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqb",  2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpeqw",  2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqw",  2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpeqd",  2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqd",  2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpgtb",  2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtb",  2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpgtw",  2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtw",  2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpgtd",  2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtd",  2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaddwd",  2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmaddwd",  2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmulhw",   2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhw",   2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmullw",   2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmullw",   2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"por",	     2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"por",	     2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psllw",    2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllw",    2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psllw",    2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psllw",    2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"pslld",    2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pslld",    2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pslld",    2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"pslld",    2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psllq",    2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllq",    2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psllq",    2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psllq",    2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psraw",    2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psraw",    2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psraw",    2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psraw",    2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psrad",    2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrad",    2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psrad",    2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrad",    2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psrlw",    2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrlw",    2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psrlw",    2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrlw",    2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psrld",    2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrld",    2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psrld",    2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrld",    2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psrlq",    2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrlq",    2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psrlq",    2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrlq",    2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ Imm8, RegXMM, 0 } },
+{"psubb",    2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubb",    2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubw",    2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubw",    2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubd",    2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubd",    2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubq",    2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegMMX|LLongMem, RegMMX, 0 } },
+{"psubq",    2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubsb",   2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubsb",   2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubsw",   2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubsw",   2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubusb",  2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubusb",  2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"psubusw",  2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubusw",  2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pxor",     2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pxor",     2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
 
 /* PIII Katmai New Instructions / SIMD instructions.  */
 
-{"addps",     2, 0x0f58,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"addss",     2, 0xf30f58,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"andnps",    2, 0x0f55,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"andps",     2, 0x0f54,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpeqps",   2, 0x0fc2,    0, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpleps",   2, 0x0fc2,    2, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpless",   2, 0xf30fc2,  2, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpltps",   2, 0x0fc2,    1, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpltss",   2, 0xf30fc2,  1, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpneqps",  2, 0x0fc2,    4, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpnleps",  2, 0x0fc2,    6, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnless",  2, 0xf30fc2,  6, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpnltps",  2, 0x0fc2,    5, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpordps",  2, 0x0fc2,    7, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpordss",  2, 0xf30fc2,  7, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpunordps",2, 0x0fc2,    3, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpunordss",2, 0xf30fc2,  3, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpps",     3, 0x0fc2,    X, CpuSSE, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"cmpss",     3, 0xf30fc2,  X, CpuSSE, FP|Modrm,	{ Imm8, RegXMM|WordMem, RegXMM } },
-{"comiss",    2, 0x0f2f,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
-{"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"addps",     2, 0x0f58,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addss",     2, 0xf30f58,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"andnps",    2, 0x0f55,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"andps",     2, 0x0f54,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqps",   2, 0x0fc2,    0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpleps",   2, 0x0fc2,    2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpless",   2, 0xf30fc2,  2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpltps",   2, 0x0fc2,    1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltss",   2, 0xf30fc2,  1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpneqps",  2, 0x0fc2,    4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnleps",  2, 0x0fc2,    6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnless",  2, 0xf30fc2,  6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnltps",  2, 0x0fc2,    5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpordps",  2, 0x0fc2,    7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordss",  2, 0xf30fc2,  7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpunordps",2, 0x0fc2,    3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordss",2, 0xf30fc2,  3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpps",     3, 0x0fc2,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"cmpss",     3, 0xf30fc2,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|WordMem, RegXMM } },
+{"comiss",    2, 0x0f2f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
+{"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
 {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
 {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
-{"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
 {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ RegXMM|WordMem, Reg32|Reg64, 0 } },
-{"divps",     2, 0x0f5e,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"divss",     2, 0xf30f5e,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"ldmxcsr",   1, 0x0fae,    2, CpuSSE, FP|Modrm, 	{ WordMem, 0, 0 } },
-{"maskmovq",  2, 0x0ff7,    X, CpuSSE, FP|Modrm,	{ RegMMX|InvMem, RegMMX, 0 } },
-{"maxps",     2, 0x0f5f,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"maxss",     2, 0xf30f5f,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"minps",     2, 0x0f5d,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"minss",     2, 0xf30f5d,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"movaps",    2, 0x0f28,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movaps",    2, 0x0f29,    X, CpuSSE, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"movhlps",   2, 0x0f12,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
-{"movhps",    2, 0x0f16,    X, CpuSSE, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"movhps",    2, 0x0f17,    X, CpuSSE, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
-{"movlhps",   2, 0x0f16,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
-{"movlps",    2, 0x0f12,    X, CpuSSE, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"movlps",    2, 0x0f13,    X, CpuSSE, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"divps",     2, 0x0f5e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"divss",     2, 0xf30f5e,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"ldmxcsr",   1, 0x0fae,    2, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ WordMem, 0, 0 } },
+{"maskmovq",  2, 0x0ff7,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|InvMem, RegMMX, 0 } },
+{"maxps",     2, 0x0f5f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"maxss",     2, 0xf30f5f,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"minps",     2, 0x0f5d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"minss",     2, 0xf30f5d,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"movaps",    2, 0x0f28,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movaps",    2, 0x0f29,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movhlps",   2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movhps",    2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movhps",    2, 0x0f17,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"movlhps",   2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movlps",    2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movlps",    2, 0x0f13,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM, LLongMem, 0 } },
 {"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ RegXMM|InvMem, Reg32|Reg64, 0 } },
-{"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
-{"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm, 	{ RegMMX, LLongMem, 0 } },
-{"movntdq",   2, 0x660fe7,  X, CpuSSE2,FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
-{"movss",     2, 0xf30f10,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"movss",     2, 0xf30f11,  X, CpuSSE, FP|Modrm,	{ RegXMM, RegXMM|WordMem, 0 } },
-{"movups",    2, 0x0f10,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movups",    2, 0x0f11,    X, CpuSSE, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"mulps",     2, 0x0f59,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"mulss",     2, 0xf30f59,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"orps",      2, 0x0f56,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pavgb",     2, 0x0fe0,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pavgb",     2, 0x660fe0,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pavgw",     2, 0x660fe3,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movntps",   2, 0x0f2b,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ RegXMM, LLongMem, 0 } },
+{"movntq",    2, 0x0fe7,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ RegMMX, LLongMem, 0 } },
+{"movntdq",   2, 0x660fe7,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, 	{ RegXMM, LLongMem, 0 } },
+{"movss",     2, 0xf30f10,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"movss",     2, 0xf30f11,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|WordMem, 0 } },
+{"movups",    2, 0x0f10,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movups",    2, 0x0f11,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"mulps",     2, 0x0f59,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mulss",     2, 0xf30f59,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"orps",      2, 0x0f56,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pavgb",     2, 0x0fe0,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgb",     2, 0x660fe0,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pavgw",     2, 0x0fe3,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgw",     2, 0x660fe3,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"pextrw",    3, 0x0fc5,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ Imm8, RegMMX|InvMem, Reg32|Reg64 } },
 {"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, RegXMM|InvMem, Reg32|Reg64 } },
 {"pinsrw",    3, 0x0fc4,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ Imm8, Reg32|Reg64|ShortMem, RegMMX } },
-{"pinsrw",    3, 0x660fc4,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
-{"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pmaxsw",    2, 0x660fee,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pmaxub",    2, 0x0fde,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pmaxub",    2, 0x660fde,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pminsw",    2, 0x0fea,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pminsw",    2, 0x660fea,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pminub",    2, 0x660fda,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pinsrw",    3, 0x660fc4,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, Reg32|Reg64|ShortMem, RegXMM } },
+{"pmaxsw",    2, 0x0fee,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxsw",    2, 0x660fee,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaxub",    2, 0x0fde,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxub",    2, 0x660fde,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pminsw",    2, 0x0fea,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pminsw",    2, 0x660fea,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pminub",    2, 0x0fda,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pminub",    2, 0x660fda,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"pmovmskb",  2, 0x0fd7,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ RegMMX|InvMem, Reg32|Reg64, 0 } },
 {"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ RegXMM|InvMem, Reg32|Reg64, 0 } },
-{"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"prefetchnta", 1, 0x0f18,  0, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"prefetcht0",  1, 0x0f18,  1, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"prefetcht1",  1, 0x0f18,  2, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"prefetcht2",  1, 0x0f18,  3, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"psadbw",    2, 0x0ff6,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"psadbw",    2, 0x660ff6,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pshufw",    3, 0x0f70,    X, CpuSSE, FP|Modrm,	{ Imm8, RegMMX|LLongMem, RegMMX } },
-{"rcpps",     2, 0x0f53,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"rcpss",     2, 0xf30f53,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"rsqrtps",   2, 0x0f52,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"rsqrtss",   2, 0xf30f52,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"sfence",    0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt,	{ 0, 0, 0 } },
-{"shufps",    3, 0x0fc6,    X, CpuSSE, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"sqrtps",    2, 0x0f51,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"sqrtss",    2, 0xf30f51,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"stmxcsr",   1, 0x0fae,    3, CpuSSE, FP|Modrm, 	{ WordMem, 0, 0 } },
-{"subps",     2, 0x0f5c,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"subss",     2, 0xf30f5c,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"ucomiss",   2, 0x0f2e,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"unpckhps",  2, 0x0f15,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"unpcklps",  2, 0x0f14,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"xorps",     2, 0x0f57,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmulhuw",   2, 0x0fe4,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"prefetchnta", 1, 0x0f18,  0, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht0",  1, 0x0f18,  1, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht1",  1, 0x0f18,  2, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht2",  1, 0x0f18,  3, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ LLongMem, 0, 0 } },
+{"psadbw",    2, 0x0ff6,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"psadbw",    2, 0x660ff6,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pshufw",    3, 0x0f70,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegMMX|LLongMem, RegMMX } },
+{"rcpps",     2, 0x0f53,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"rcpss",     2, 0xf30f53,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"rsqrtps",   2, 0x0f52,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"rsqrtss",   2, 0xf30f52,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"sfence",    0, 0x0fae, 0xf8, CpuSSE, NoSuf|IgnoreSize|ImmExt,	{ 0, 0, 0 } },
+{"shufps",    3, 0x0fc6,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtps",    2, 0x0f51,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtss",    2, 0xf30f51,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"stmxcsr",   1, 0x0fae,    3, CpuSSE, NoSuf|IgnoreSize|Modrm, 	{ WordMem, 0, 0 } },
+{"subps",     2, 0x0f5c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"subss",     2, 0xf30f5c,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"ucomiss",   2, 0x0f2e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"unpckhps",  2, 0x0f15,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklps",  2, 0x0f14,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"xorps",     2, 0x0f57,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 
 /* SSE-2 instructions.  */
 
-{"addpd",     2, 0x660f58,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"addsd",     2, 0xf20f58,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"andnpd",    2, 0x660f55,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"andpd",     2, 0x660f54,  X, CpuSSE2, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmplepd",   2, 0x660fc2,  2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmppd",     3, 0x660fc2,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"addpd",     2, 0x660f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addsd",     2, 0xf20f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"andnpd",    2, 0x660f55,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"andpd",     2, 0x660f54,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmplepd",   2, 0x660fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmppd",     3, 0x660fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
 /* Intel mode string compare.  */
 {"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
 {"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
-{"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
-{"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
+{"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
+{"comisd",    2, 0x660f2f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
 {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
-{"divpd",     2, 0x660f5e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"divsd",     2, 0xf20f5e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"maxpd",     2, 0x660f5f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"maxsd",     2, 0xf20f5f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"minpd",     2, 0x660f5d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"minsd",     2, 0xf20f5d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"movapd",    2, 0x660f28,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movapd",    2, 0x660f29,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"movhpd",    2, 0x660f16,  X, CpuSSE2, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"movhpd",    2, 0x660f17,  X, CpuSSE2, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
-{"movlpd",    2, 0x660f12,  X, CpuSSE2, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"divpd",     2, 0x660f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"divsd",     2, 0xf20f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"maxpd",     2, 0x660f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"maxsd",     2, 0xf20f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"minpd",     2, 0x660f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"minsd",     2, 0xf20f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"movapd",    2, 0x660f28,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movapd",    2, 0x660f29,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movhpd",    2, 0x660f16,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movhpd",    2, 0x660f17,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"movlpd",    2, 0x660f12,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movlpd",    2, 0x660f13,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, LLongMem, 0 } },
 {"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
-{"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
+{"movntpd",   2, 0x660f2b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, 	{ RegXMM, LLongMem, 0 } },
 /* Intel mode string move.  */
 {"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
 {"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
-{"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LongMem, 0 } },
-{"movupd",    2, 0x660f10,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movupd",    2, 0x660f11,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"mulpd",     2, 0x660f59,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"mulsd",     2, 0xf20f59,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"orpd",      2, 0x660f56,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"shufpd",    3, 0x660fc6,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"sqrtpd",    2, 0x660f51,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"subpd",     2, 0x660f5c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"subsd",     2, 0xf20f5c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"ucomisd",   2, 0x660f2e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"unpckhpd",  2, 0x660f15,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"unpcklpd",  2, 0x660f14,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"xorpd",     2, 0x660f57,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
-{"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movsd",     2, 0xf20f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"movsd",     2, 0xf20f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LongMem, 0 } },
+{"movupd",    2, 0x660f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movupd",    2, 0x660f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"mulpd",     2, 0x660f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mulsd",     2, 0xf20f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"orpd",      2, 0x660f56,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"shufpd",    3, 0x660fc6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtpd",    2, 0x660f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"subpd",     2, 0x660f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"subsd",     2, 0xf20f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"ucomisd",   2, 0x660f2e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"unpckhpd",  2, 0x660f15,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklpd",  2, 0x660f14,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"xorpd",     2, 0x660f57,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
-{"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
 {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
-{"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
-{"movdqa",    2, 0x660f6f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movdqa",    2, 0x660f7f,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"movdqu",    2, 0xf30f6f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movdqu",    2, 0xf30f7f,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, FP|Modrm,	{ RegXMM|InvMem, RegMMX, 0 } },
-{"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, FP|Modrm,	{ RegMMX|InvMem, RegXMM, 0 } },
-{"pmuludq",   2, 0x0ff4,    X, CpuSSE2, FP|Modrm,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmuludq",   2, 0x660ff4,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
-{"pshufd",    3, 0x660f70,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"pshufhw",   3, 0xf30f70,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"pshuflw",   3, 0xf20f70,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"pslldq",    2, 0x660f73,  7, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM, 0 } },
-{"psrldq",    2, 0x660f73,  3, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM, 0 } },
-{"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movdqa",    2, 0x660f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movdqa",    2, 0x660f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movdqu",    2, 0xf30f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movdqu",    2, 0xf30f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|InvMem, RegMMX, 0 } },
+{"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegMMX|InvMem, RegXMM, 0 } },
+{"pmuludq",   2, 0x0ff4,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmuludq",   2, 0x660ff4,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"pshufd",    3, 0x660f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"pshufhw",   3, 0xf30f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"pshuflw",   3, 0xf20f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"pslldq",    2, 0x660f73,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM, 0 } },
+{"psrldq",    2, 0x660f73,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM, 0 } },
+{"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 
 /* Prescott New Instructions.  */
 
-{"addsubpd",  2, 0x660fd0,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"addsubps",  2, 0xf20fd0,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
-/* Intel Syntax */
-{"fisttpq",   1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"addsubpd",  2, 0x660fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps",  2, 0xf20fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fisttp",    1, 0xdd,      1, CpuPNI, q_FP|Modrm,	{ LLongMem, 0, 0} },
 {"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
-{"haddpd",    2, 0x660f7c,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"haddps",    2, 0xf20f7c,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubpd",    2, 0x660f7d,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubps",    2, 0xf20f7d,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"lddqu",     2, 0xf20ff0,  X, CpuPNI, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"monitor",   0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,	{ 0, 0, 0} },
+{"haddpd",    2, 0x660f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps",    2, 0xf20f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd",    2, 0x660f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps",    2, 0xf20f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu",     2, 0xf20ff0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"monitor",   0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt,	{ 0, 0, 0} },
 /* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
-{"monitor",   3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,	{ Reg32, Reg32, Reg32} },
-{"movddup",   2, 0xf20f12,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movshdup",  2, 0xf30f16,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movsldup",  2, 0xf30f12,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"mwait",     0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,	{ 0, 0, 0} },
+{"monitor",   3, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt,	{ Reg32, Reg32, Reg32} },
+{"movddup",   2, 0xf20f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup",  2, 0xf30f16,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup",  2, 0xf30f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait",     0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt,	{ 0, 0, 0} },
 /* Need to ensure only "mwait %eax,%ecx" is accepted.  */
-{"mwait",     2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,	{ Reg32, Reg32, 0} },
+{"mwait",     2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt,	{ Reg32, Reg32, 0} },
 
 /* AMD 3DNow! instructions.  */
 
-{"prefetch", 1, 0x0f0d,	   0, Cpu3dnow, FP|Modrm,		{ ByteMem, 0, 0 } },
-{"prefetchw",1, 0x0f0d,	   1, Cpu3dnow, FP|Modrm,		{ ByteMem, 0, 0 } },
-{"femms",    0, 0x0f0e,	   X, Cpu3dnow, FP,			{ 0, 0, 0 } },
-{"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"prefetch", 1, 0x0f0d,	   0, Cpu3dnow, NoSuf|IgnoreSize|Modrm,	{ ByteMem, 0, 0 } },
+{"prefetchw",1, 0x0f0d,	   1, Cpu3dnow, NoSuf|IgnoreSize|Modrm,	{ ByteMem, 0, 0 } },
+{"femms",    0, 0x0f0e,	   X, Cpu3dnow, NoSuf,			{ 0, 0, 0 } },
+{"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
 
 /* AMD extensions. */
 {"syscall",  0, 0x0f05,    X, CpuK6,	NoSuf,			{ 0, 0, 0} },
@@ -1403,6 +1398,7 @@ static const template i386_optab[] =
 #undef bwlq_Suf
 #undef FP
 #undef l_FP
+#undef q_FP
 #undef x_FP
 #undef sl_FP
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9b0ad7c..e815c6c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,33 @@
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+	* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
+	(indirEb): Remove.
+	(Mp): Use f_mode rather than none at all.
+	(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
+	replaces what previously was x_mode; x_mode now means 128-bit SSE
+	operands.
+	(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
+	mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
+	pinsrw's second operand is Edqw.
+	(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
+	operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
+	fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
+	mode when an operand size override is present or always suffixing.
+	More instructions will need to be added to this group.
+	(putop): Handle new macro chars 'C' (short/long suffix selector),
+	'I' (Intel mode override for following macro char), and 'J' (for
+	adding the 'l' prefix to far branches in AT&T mode). When an
+	alternative was specified in the template, honor macro character when
+	specified for Intel mode.
+	(OP_E): Handle new *_mode values. Correct pointer specifications for
+	memory operands. Consolidate output of index register.
+	(OP_G): Handle new *_mode values.
+	(OP_I): Handle const_1_mode.
+	(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
+	respective opcode prefix bits have been consumed.
+	(OP_EM, OP_EX): Provide some default handling for generating pointer
+	specifications.
+
 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 
 	* crx-opc.c (REV_COP_INST): New macro, reverse operand order of
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 66fd388..b5cc638 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -193,16 +193,19 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define Eb OP_E, b_mode
 #define Ev OP_E, v_mode
 #define Ed OP_E, d_mode
+#define Eq OP_E, q_mode
 #define Edq OP_E, dq_mode
-#define indirEb OP_indirE, b_mode
+#define Edqw OP_E, dqw_mode
 #define indirEv OP_indirE, v_mode
+#define indirEp OP_indirE, f_mode
 #define Ew OP_E, w_mode
 #define Ma OP_E, v_mode
 #define M OP_M, 0		/* lea, lgdt, etc. */
-#define Mp OP_M, 0		/* 32 or 48 bit memory operand for LDS, LES etc */
+#define Mp OP_M, f_mode		/* 32 or 48 bit memory operand for LDS, LES etc */
 #define Gb OP_G, b_mode
 #define Gv OP_G, v_mode
 #define Gd OP_G, d_mode
+#define Gdq OP_G, dq_mode
 #define Gw OP_G, w_mode
 #define Rd OP_Rd, d_mode
 #define Rm OP_Rd, m_mode
@@ -212,6 +215,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define Iq OP_I, q_mode
 #define Iv64 OP_I64, v_mode
 #define Iw OP_I, w_mode
+#define I1 OP_I, const_1_mode
 #define Jb OP_J, b_mode
 #define Jv OP_J, v_mode
 #define Cm OP_C, m_mode
@@ -308,11 +312,15 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define w_mode 3  /* word operand */
 #define d_mode 4  /* double word operand  */
 #define q_mode 5  /* quad word operand */
-#define x_mode 6  /* 80 bit float operand */
-#define m_mode 7  /* d_mode in 32bit, q_mode in 64bit mode.  */
-#define cond_jump_mode 8
-#define loop_jcxz_mode 9
-#define dq_mode 10 /* operand size depends on REX prefixes.  */
+#define t_mode 6  /* ten-byte operand */
+#define x_mode 7  /* 16-byte XMM operand */
+#define m_mode 8  /* d_mode in 32bit, q_mode in 64bit mode.  */
+#define cond_jump_mode 9
+#define loop_jcxz_mode 10
+#define dq_mode 11 /* operand size depends on REX prefixes.  */
+#define dqw_mode 12 /* registers like dq_mode, memory like w_mode.  */
+#define f_mode 13 /* 4- or 6-byte pointer operand */
+#define const_1_mode 14
 
 #define es_reg 100
 #define cs_reg 101
@@ -443,9 +451,14 @@ struct dis386 {
 /* Upper case letters in the instruction names here are macros.
    'A' => print 'b' if no register operands or suffix_always is true
    'B' => print 'b' if suffix_always is true
+   'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
+   .      size prefix
    'E' => print 'e' if 32-bit form of jcxz
    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
    'H' => print ",pt" or ",pn" branch hint
+   'I' => honor following macro letter even in Intel mode (implemented only
+   .      for some of the macro letters)
+   'J' => print 'l'
    'L' => print 'l' if suffix_always is true
    'N' => print 'n' if instruction has no wait "prefix"
    'O' => print 'd', or 'o'
@@ -457,8 +470,8 @@ struct dis386 {
    'S' => print 'w', 'l' or 'q' if suffix_always is true
    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
-   'X' => print 's', 'd' depending on data16 prefix (for XMM)
    'W' => print 'b' or 'w' ("w" or "de" in intel mode)
+   'X' => print 's', 'd' depending on data16 prefix (for XMM)
    'Y' => 'q' if instruction has an REX 64bit overwrite prefix
 
    Many of the above letters print nothing in Intel mode.  See "putop"
@@ -645,7 +658,7 @@ static const struct dis386 dis386[] = {
   /* 98 */
   { "cW{tR||tR|}",	XX, XX, XX },
   { "cR{tO||tO|}",	XX, XX, XX },
-  { "lcall{T|}",	Ap, XX, XX },
+  { "Jcall{T|}",	Ap, XX, XX },
   { "(bad)",		XX, XX, XX },	/* fwait */
   { "pushfT",		XX, XX, XX },
   { "popfT",		XX, XX, XX },
@@ -735,7 +748,7 @@ static const struct dis386 dis386[] = {
   /* e8 */
   { "callT",		Jv, XX, XX },
   { "jmpT",		Jv, XX, XX },
-  { "ljmp{T|}",		Ap, XX, XX },
+  { "Jjmp{T|}",		Ap, XX, XX },
   { "jmp",		Jb, XX, XX },
   { "inB",		AL, indirDX, XX },
   { "inS",		eAX, indirDX, XX },
@@ -853,7 +866,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "cmovle",		Gv, Ev, XX },
   { "cmovg",		Gv, Ev, XX },
   /* 50 */
-  { "movmskpX",		Gd, XS, XX },
+  { "movmskpX",		Gdq, XS, XX },
   { PREGRP13 },
   { PREGRP12 },
   { PREGRP11 },
@@ -983,8 +996,8 @@ static const struct dis386 dis386_twobyte[] = {
   { "xaddS",		Ev, Gv, XX },
   { PREGRP1 },
   { "movntiS",		Ev, Gv, XX },
-  { "pinsrw",		MX, Ed, Ib },
-  { "pextrw",		Gd, MS, Ib },
+  { "pinsrw",		MX, Edqw, Ib },
+  { "pextrw",		Gdq, MS, Ib },
   { "shufpX",		XM, EX, Ib },
   { GRP9 },
   /* c8 */
@@ -1004,7 +1017,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "paddq",		MX, EM, XX },
   { "pmullw",		MX, EM, XX },
   { PREGRP21 },
-  { "pmovmskb",		Gd, MS, XX },
+  { "pmovmskb",		Gdq, MS, XX },
   /* d8 */
   { "psubusb",		MX, EM, XX },
   { "psubusw",		MX, EM, XX },
@@ -1256,25 +1269,25 @@ static const struct dis386 grps[][8] = {
   },
   /* GRP2b_one */
   {
-    { "rolA",	Eb, XX, XX },
-    { "rorA",	Eb, XX, XX },
-    { "rclA",	Eb, XX, XX },
-    { "rcrA",	Eb, XX, XX },
-    { "shlA",	Eb, XX, XX },
-    { "shrA",	Eb, XX, XX },
+    { "rolA",	Eb, I1, XX },
+    { "rorA",	Eb, I1, XX },
+    { "rclA",	Eb, I1, XX },
+    { "rcrA",	Eb, I1, XX },
+    { "shlA",	Eb, I1, XX },
+    { "shrA",	Eb, I1, XX },
     { "(bad)",	XX, XX, XX },
-    { "sarA",	Eb, XX, XX },
+    { "sarA",	Eb, I1, XX },
   },
   /* GRP2S_one */
   {
-    { "rolQ",	Ev, XX, XX },
-    { "rorQ",	Ev, XX, XX },
-    { "rclQ",	Ev, XX, XX },
-    { "rcrQ",	Ev, XX, XX },
-    { "shlQ",	Ev, XX, XX },
-    { "shrQ",	Ev, XX, XX },
+    { "rolQ",	Ev, I1, XX },
+    { "rorQ",	Ev, I1, XX },
+    { "rclQ",	Ev, I1, XX },
+    { "rcrQ",	Ev, I1, XX },
+    { "shlQ",	Ev, I1, XX },
+    { "shrQ",	Ev, I1, XX },
     { "(bad)",	XX, XX, XX},
-    { "sarQ",	Ev, XX, XX },
+    { "sarQ",	Ev, I1, XX },
   },
   /* GRP2b_cl */
   {
@@ -1336,9 +1349,9 @@ static const struct dis386 grps[][8] = {
     { "incQ",	Ev, XX, XX },
     { "decQ",	Ev, XX, XX },
     { "callT",	indirEv, XX, XX },
-    { "lcallT",	indirEv, XX, XX },
+    { "JcallT",	indirEp, XX, XX },
     { "jmpT",	indirEv, XX, XX },
-    { "ljmpT",	indirEv, XX, XX },
+    { "JjmpT",	indirEp, XX, XX },
     { "pushU",	Ev, XX, XX },
     { "(bad)",	XX, XX, XX },
   },
@@ -1355,10 +1368,10 @@ static const struct dis386 grps[][8] = {
   },
   /* GRP7 */
   {
-    { "sgdtQ",	 M, XX, XX },
-    { "sidtQ", PNI_Fixup, 0, XX, XX },
-    { "lgdtQ",	 M, XX, XX },
-    { "lidtQ",	 M, XX, XX },
+    { "sgdtIQ",	 M, XX, XX },
+    { "sidtIQ", PNI_Fixup, 0, XX, XX },
+    { "lgdt{Q|Q||}",	 M, XX, XX },
+    { "lidt{Q|Q||}",	 M, XX, XX },
     { "smswQ",	Ev, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "lmsw",	Ew, XX, XX },
@@ -1378,7 +1391,7 @@ static const struct dis386 grps[][8] = {
   /* GRP9 */
   {
     { "(bad)",	XX, XX, XX },
-    { "cmpxchg8b", Ev, XX, XX },
+    { "cmpxchg8b", Eq, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
@@ -1654,10 +1667,10 @@ static const struct dis386 prefix_user_table[][4] = {
   },
   /* PREGRP25 */
   {
-  { "movntq", Ev, MX, XX },
-  { "(bad)", Ev, XM, XX },
-  { "movntdq", Ev, XM, XX },
-  { "(bad)", Ev, XM, XX },
+    { "movntq", EM, MX, XX },
+    { "(bad)", EM, XM, XX },
+    { "movntdq", EM, XM, XX },
+    { "(bad)", EM, XM, XX },
   },
   /* PREGRP26 */
   {
@@ -2339,9 +2352,9 @@ static const char *float_mem[] = {
   "(bad)",
   "fst{s||s|}",
   "fstp{s||s|}",
-  "fldenv",
+  "fldenvIC",
   "fldcw",
-  "fNstenv",
+  "fNstenvIC",
   "fNstcw",
   /* da */
   "fiadd{l||l|}",
@@ -2375,9 +2388,9 @@ static const char *float_mem[] = {
   "fisttp{ll||ll|}",
   "fst{l||l|}",
   "fstp{l||l|}",
-  "frstor",
+  "frstorIC",
   "(bad)",
-  "fNsave",
+  "fNsaveIC",
   "fNstsw",
   /* de */
   "fiadd",
@@ -2433,9 +2446,9 @@ static const unsigned char float_mem_mode[] = {
   d_mode,
   d_mode,
   0,
-  x_mode,
+  t_mode,
   0,
-  x_mode,
+  t_mode,
   /* dc */
   q_mode,
   q_mode,
@@ -2468,9 +2481,9 @@ static const unsigned char float_mem_mode[] = {
   w_mode,
   w_mode,
   w_mode,
-  x_mode,
+  t_mode,
   q_mode,
-  x_mode,
+  t_mode,
   q_mode
 };
 
@@ -2701,7 +2714,7 @@ static int
 putop (const char *template, int sizeflag)
 {
   const char *p;
-  int alt;
+  int alt = 0;
 
   for (p = template; *p; p++)
     {
@@ -2732,7 +2745,10 @@ putop (const char *template, int sizeflag)
 		}
 	      alt--;
 	    }
-	  break;
+	  /* Fall through.  */
+	case 'I':
+	  alt = 1;
+	  continue;
 	case '|':
 	  while (*++p != '}')
 	    {
@@ -2754,6 +2770,18 @@ putop (const char *template, int sizeflag)
 	  if (sizeflag & SUFFIX_ALWAYS)
 	    *obufp++ = 'b';
 	  break;
+	case 'C':
+	  if (intel_syntax && !alt)
+	    break;
+	  if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
+	    {
+	      if (sizeflag & DFLAG)
+		*obufp++ = intel_syntax ? 'd' : 'l';
+	      else
+		*obufp++ = intel_syntax ? 'w' : 's';
+	      used_prefixes |= (prefixes & PREFIX_DATA);
+	    }
+	  break;
 	case 'E':		/* For jcxz/jecxz */
 	  if (mode_64bit)
 	    {
@@ -2794,6 +2822,11 @@ putop (const char *template, int sizeflag)
 		*obufp++ = 'n';
 	    }
 	  break;
+	case 'J':
+	  if (intel_syntax)
+	    break;
+	  *obufp++ = 'l';
+	  break;
 	case 'L':
 	  if (intel_syntax)
 	    break;
@@ -2852,7 +2885,7 @@ putop (const char *template, int sizeflag)
 	    }
 	  /* Fall through.  */
 	case 'Q':
-	  if (intel_syntax)
+	  if (intel_syntax && !alt)
 	    break;
 	  USED_REX (REX_MODE64);
 	  if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
@@ -2862,7 +2895,7 @@ putop (const char *template, int sizeflag)
 	      else
 		{
 		  if (sizeflag & DFLAG)
-		    *obufp++ = 'l';
+		    *obufp++ = intel_syntax ? 'd' : 'l';
 		  else
 		    *obufp++ = 'w';
 		  used_prefixes |= (prefixes & PREFIX_DATA);
@@ -2965,6 +2998,7 @@ putop (const char *template, int sizeflag)
 	    used_prefixes |= (prefixes & PREFIX_DATA);
 	  break;
 	}
+      alt = 0;
     }
   *obufp = 0;
   return 0;
@@ -3119,10 +3153,11 @@ OP_E (int bytemode, int sizeflag)
 	  break;
 	case v_mode:
 	case dq_mode:
+	case dqw_mode:
 	  USED_REX (REX_MODE64);
 	  if (rex & REX_MODE64)
 	    oappend (names64[rm + add]);
-	  else if ((sizeflag & DFLAG) || bytemode == dq_mode)
+	  else if ((sizeflag & DFLAG) || bytemode != v_mode)
 	    oappend (names32[rm + add]);
 	  else
 	    oappend (names16[rm + add]);
@@ -3212,13 +3247,19 @@ OP_E (int bytemode, int sizeflag)
 		  oappend ("BYTE PTR ");
 		  break;
 		case w_mode:
+		case dqw_mode:
 		  oappend ("WORD PTR ");
 		  break;
 		case v_mode:
-		  if (sizeflag & DFLAG)
+		case dq_mode:
+		  USED_REX (REX_MODE64);
+		  if (rex & REX_MODE64)
+		    oappend ("QWORD PTR ");
+		  else if ((sizeflag & DFLAG) || bytemode == dq_mode)
 		    oappend ("DWORD PTR ");
 		  else
 		    oappend ("WORD PTR ");
+		  used_prefixes |= (prefixes & PREFIX_DATA);
 		  break;
 		case d_mode:
 		  oappend ("DWORD PTR ");
@@ -3228,17 +3269,29 @@ OP_E (int bytemode, int sizeflag)
 		  break;
 		case m_mode:
 		  if (mode_64bit)
+		    oappend ("QWORD PTR ");
+		  else
 		    oappend ("DWORD PTR ");
+		  break;
+		case f_mode:
+		  if (sizeflag & DFLAG)
+		    {
+		      used_prefixes |= (prefixes & PREFIX_DATA);
+		      oappend ("FWORD PTR ");
+		    }
 		  else
-		    oappend ("QWORD PTR ");
+		    oappend ("DWORD PTR ");
+		  break;
+		case t_mode:
+		  oappend ("TBYTE PTR ");
 		  break;
 		case x_mode:
-		  oappend ("XWORD PTR ");
+		  oappend ("XMMWORD PTR ");
 		  break;
 		default:
 		  break;
 		}
-	     }
+	    }
 	  *obufp++ = open_char;
 	  if (intel_syntax && riprel)
 	    oappend ("rip + ");
@@ -3253,22 +3306,13 @@ OP_E (int bytemode, int sizeflag)
 	    {
 	      if (index != 4)
 		{
-		  if (intel_syntax)
+		  if (!intel_syntax || havebase)
 		    {
-		      if (havebase)
-			{
-			  *obufp++ = separator_char;
-			  *obufp = '\0';
-			}
-		      sprintf (scratchbuf, "%s",
-			       mode_64bit && (sizeflag & AFLAG)
-			       ? names64[index] : names32[index]);
+		      *obufp++ = separator_char;
+		      *obufp = '\0';
 		    }
-		  else
-		    sprintf (scratchbuf, ",%s",
-			     mode_64bit && (sizeflag & AFLAG)
-			     ? names64[index] : names32[index]);
-		  oappend (scratchbuf);
+		  oappend (mode_64bit && (sizeflag & AFLAG)
+			   ? names64[index] : names32[index]);
 		}
 	      if (scale != 0 || (!intel_syntax && index != 4))
 		{
@@ -3384,10 +3428,12 @@ OP_G (int bytemode, int sizeflag)
       oappend (names64[reg + add]);
       break;
     case v_mode:
+    case dq_mode:
+    case dqw_mode:
       USED_REX (REX_MODE64);
       if (rex & REX_MODE64)
 	oappend (names64[reg + add]);
-      else if (sizeflag & DFLAG)
+      else if ((sizeflag & DFLAG) || bytemode != v_mode)
 	oappend (names32[reg + add]);
       else
 	oappend (names16[reg + add]);
@@ -3628,6 +3674,10 @@ OP_I (int bytemode, int sizeflag)
       mask = 0xfffff;
       op = get16 ();
       break;
+    case const_1_mode:
+      if (intel_syntax)
+        oappend ("1");
+      return;
     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       return;
@@ -3884,6 +3934,23 @@ ptr_reg (int code, int sizeflag)
 static void
 OP_ESreg (int code, int sizeflag)
 {
+  if (intel_syntax)
+    {
+      if (codep[-1] & 1)
+	{
+	  USED_REX (REX_MODE64);
+	  used_prefixes |= (prefixes & PREFIX_DATA);
+	  if (rex & REX_MODE64)
+	    oappend ("QWORD PTR ");
+	  else if ((sizeflag & DFLAG))
+	    oappend ("DWORD PTR ");
+	  else
+	    oappend ("WORD PTR ");
+	}
+      else
+	oappend ("BYTE PTR ");
+    }
+
   oappend ("%es:" + intel_syntax);
   ptr_reg (code, sizeflag);
 }
@@ -3891,6 +3958,23 @@ OP_ESreg (int code, int sizeflag)
 static void
 OP_DSreg (int code, int sizeflag)
 {
+  if (intel_syntax)
+    {
+      if (codep[-1] != 0xd7 && (codep[-1] & 1))
+	{
+	  USED_REX (REX_MODE64);
+	  used_prefixes |= (prefixes & PREFIX_DATA);
+	  if (rex & REX_MODE64)
+	    oappend ("QWORD PTR ");
+	  else if ((sizeflag & DFLAG))
+	    oappend ("DWORD PTR ");
+	  else
+	    oappend ("WORD PTR ");
+	}
+      else
+	oappend ("BYTE PTR ");
+    }
+
   if ((prefixes
        & (PREFIX_CS
 	  | PREFIX_DS
@@ -3977,6 +4061,11 @@ OP_EM (int bytemode, int sizeflag)
 {
   if (mod != 3)
     {
+      if (intel_syntax && bytemode == v_mode)
+	{
+	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
+	  used_prefixes |= (prefixes & PREFIX_DATA);
+ 	}
       OP_E (bytemode, sizeflag);
       return;
     }
@@ -4005,6 +4094,17 @@ OP_EX (int bytemode, int sizeflag)
   int add = 0;
   if (mod != 3)
     {
+      if (intel_syntax && bytemode == v_mode)
+	{
+	  switch (prefixes & (PREFIX_DATA|PREFIX_REPZ|PREFIX_REPNZ))
+	    {
+	    case 0:            bytemode = x_mode; break;
+	    case PREFIX_REPZ:  bytemode = d_mode; used_prefixes |= PREFIX_REPZ;  break;
+	    case PREFIX_DATA:  bytemode = x_mode; used_prefixes |= PREFIX_DATA;  break;
+	    case PREFIX_REPNZ: bytemode = q_mode; used_prefixes |= PREFIX_REPNZ; break;
+	    default:           bytemode = 0; break;
+	    }
+	}
       OP_E (bytemode, sizeflag);
       return;
     }