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-rw-r--r--cpu/ChangeLog7
-rw-r--r--cpu/bpf.cpu38
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/testsuite/gas/bpf/alu-xbpf.d17
-rw-r--r--gas/testsuite/gas/bpf/alu-xbpf.s11
-rw-r--r--gas/testsuite/gas/bpf/alu32-xbpf.d17
-rw-r--r--gas/testsuite/gas/bpf/alu32-xbpf.s11
-rw-r--r--gas/testsuite/gas/bpf/bpf.exp3
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/bpf-desc.c80
-rw-r--r--opcodes/bpf-desc.h9
-rw-r--r--opcodes/bpf-opc.c96
-rw-r--r--opcodes/bpf-opc.h8
13 files changed, 289 insertions, 23 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 29e2512..4d68e00 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,10 @@
+2020-09-18 David Faust <david.faust@oracle.com>
+
+ * bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
+ (define-alu-insn-bin, daib): Take ISAs as an argument.
+ (define-alu-instructions): Update calls to daib pmacro with
+ ISAs; add sdiv and smod.
+
2020-09-08 David Faust <david.faust@oracle.com>
* bpf.cpu (define-alu-instructions): Correct semantic operators
diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
index eb7bf5c..13dde70 100644
--- a/cpu/bpf.cpu
+++ b/cpu/bpf.cpu
@@ -249,6 +249,8 @@
(ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5)
(LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb)
(ARSH #xc) (END #xd)
+ ;; xBPF-only: signed div, signed mod
+ (SDIV #xe) (SMOD #xf)
;; Codes for OP_CLASS_JMP
(JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4)
(JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9)
@@ -420,12 +422,12 @@
()))
(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
- x-endian x-mode x-semop)
+ x-endian x-mode x-semop x-isas)
(begin
;; dst = dst OP immediate
(dni (.sym x-basename x-suffix "i" x-endian)
(.str x-basename x-suffix " immediate")
- (endian-isas x-endian)
+ (.splice (.unsplice x-isas))
(.str x-basename x-suffix " $dst" x-endian ",$imm32")
(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
x-op-class OP_SRC_K x-op-code)
@@ -434,7 +436,7 @@
;; dst = dst OP src
(dni (.sym x-basename x-suffix "r" x-endian)
(.str x-basename x-suffix " register")
- (endian-isas x-endian)
+ (.splice (.unsplice x-isas))
(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
x-op-class OP_SRC_X x-op-code)
@@ -471,10 +473,10 @@
;; Binary ALU instructions (all the others)
;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
-(define-pmacro (daib x-basename x-op-code x-endian x-semop)
+(define-pmacro (daib x-basename x-op-code x-endian x-semop x-isas)
(begin
- (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
- (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
+ (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop x-isas)
+ (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop x-isas)))
;; Move ALU instructions (mov)
(define-pmacro (daim x-basename x-op-code x-endian)
@@ -484,17 +486,19 @@
(define-pmacro (define-alu-instructions x-endian)
(begin
- (daib add OP_CODE_ADD x-endian add)
- (daib sub OP_CODE_SUB x-endian sub)
- (daib mul OP_CODE_MUL x-endian mul)
- (daib div OP_CODE_DIV x-endian udiv)
- (daib or OP_CODE_OR x-endian or)
- (daib and OP_CODE_AND x-endian and)
- (daib lsh OP_CODE_LSH x-endian sll)
- (daib rsh OP_CODE_RSH x-endian srl)
- (daib mod OP_CODE_MOD x-endian umod)
- (daib xor OP_CODE_XOR x-endian xor)
- (daib arsh OP_CODE_ARSH x-endian sra)
+ (daib add OP_CODE_ADD x-endian add (endian-isas x-endian))
+ (daib sub OP_CODE_SUB x-endian sub (endian-isas x-endian))
+ (daib mul OP_CODE_MUL x-endian mul (endian-isas x-endian))
+ (daib div OP_CODE_DIV x-endian udiv (endian-isas x-endian))
+ (daib or OP_CODE_OR x-endian or (endian-isas x-endian))
+ (daib and OP_CODE_AND x-endian and (endian-isas x-endian))
+ (daib lsh OP_CODE_LSH x-endian sll (endian-isas x-endian))
+ (daib rsh OP_CODE_RSH x-endian srl (endian-isas x-endian))
+ (daib mod OP_CODE_MOD x-endian umod (endian-isas x-endian))
+ (daib xor OP_CODE_XOR x-endian xor (endian-isas x-endian))
+ (daib arsh OP_CODE_ARSH x-endian sra (endian-isas x-endian))
+ (daib sdiv OP_CODE_SDIV x-endian div ((ISA (.sym xbpf x-endian))))
+ (daib smod OP_CODE_SMOD x-endian mod ((ISA (.sym xbpf x-endian))))
(daiu neg OP_CODE_NEG x-endian neg)
(daim mov OP_CODE_MOV x-endian)))
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 057feeb..cad6b5c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2020-09-018 David Faust <david.faust@oracle.com>
+
+ * testsuite/gas/bpf/alu-xbpf.d: New file.
+ * testsuite/gas/bpf/alu-xbpf.s: Likewise.
+ * testsuite/gas/bpf/alu32-xbpf.d: Likewise.
+ * testsuite/gas/bpf/alu32-xbpf.d: Likewise.
+ * testuiste/gas/bpf/bpf.exp: Run new tests.
+
2020-09-18 Tucker <tuckkern+sourceware@gmail.com>
PR 26556
diff --git a/gas/testsuite/gas/bpf/alu-xbpf.d b/gas/testsuite/gas/bpf/alu-xbpf.d
new file mode 100644
index 0000000..7f97d49
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu-xbpf.d
@@ -0,0 +1,17 @@
+#as: --EL -mxbpf
+#objdump: -dr -mxbpf
+#name: xBPF ALU64 insns
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ 0: e7 02 00 00 02 00 00 00 sdiv %r2,2
+ 8: e7 03 00 00 fd ff ff ff sdiv %r3,-3
+ 10: e7 04 00 00 ef be ad 7e sdiv %r4,0x7eadbeef
+ 18: ef 25 00 00 00 00 00 00 sdiv %r5,%r2
+ 20: f7 02 00 00 03 00 00 00 smod %r2,3
+ 28: f7 03 00 00 fc ff ff ff smod %r3,-4
+ 30: f7 04 00 00 ef be ad 7e smod %r4,0x7eadbeef
+ 38: ff 25 00 00 00 00 00 00 smod %r5,%r2
diff --git a/gas/testsuite/gas/bpf/alu-xbpf.s b/gas/testsuite/gas/bpf/alu-xbpf.s
new file mode 100644
index 0000000..ebcebd7
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu-xbpf.s
@@ -0,0 +1,11 @@
+ # Tests for xBPF-specific alu instructions
+ .text
+ sdiv %r2, 2
+ sdiv %r3, -3
+ sdiv %r4, 0x7eadbeef
+ sdiv %r5, %r2
+
+ smod %r2, 3
+ smod %r3, -4
+ smod %r4, 0x7eadbeef
+ smod %r5, %r2
diff --git a/gas/testsuite/gas/bpf/alu32-xbpf.d b/gas/testsuite/gas/bpf/alu32-xbpf.d
new file mode 100644
index 0000000..03411d6
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu32-xbpf.d
@@ -0,0 +1,17 @@
+#as: --EL -mxbpf
+#objdump: -dr -mxbpf
+#name: xBPF ALU32 insns
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ 0: e4 02 00 00 02 00 00 00 sdiv32 %r2,2
+ 8: e4 03 00 00 fd ff ff ff sdiv32 %r3,-3
+ 10: e4 04 00 00 ef be ad 7e sdiv32 %r4,0x7eadbeef
+ 18: ec 25 00 00 00 00 00 00 sdiv32 %r5,%r2
+ 20: f4 02 00 00 03 00 00 00 smod32 %r2,3
+ 28: f4 03 00 00 fc ff ff ff smod32 %r3,-4
+ 30: f4 04 00 00 ef be ad 7e smod32 %r4,0x7eadbeef
+ 38: fc 25 00 00 00 00 00 00 smod32 %r5,%r2
diff --git a/gas/testsuite/gas/bpf/alu32-xbpf.s b/gas/testsuite/gas/bpf/alu32-xbpf.s
new file mode 100644
index 0000000..9ce5a26
--- /dev/null
+++ b/gas/testsuite/gas/bpf/alu32-xbpf.s
@@ -0,0 +1,11 @@
+ # Tests for xBPF-specific alu instructions
+ .text
+ sdiv32 %r2, 2
+ sdiv32 %r3, -3
+ sdiv32 %r4, 0x7eadbeef
+ sdiv32 %r5, %r2
+
+ smod32 %r2, 3
+ smod32 %r3, -4
+ smod32 %r4, 0x7eadbeef
+ smod32 %r5, %r2
diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp
index 242b190..f7c04f4 100644
--- a/gas/testsuite/gas/bpf/bpf.exp
+++ b/gas/testsuite/gas/bpf/bpf.exp
@@ -41,4 +41,7 @@ if {[istarget bpf*-*-*]} {
run_dump_test indcall-1
run_list_test indcall-bad-1
+
+ run_dump_test alu-xbpf
+ run_dump_test alu32-xbpf
}
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6243511..0f3c270 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-09-18 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
* csky-dis.c (csky_get_disassembler): Don't return NULL when there
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
index 6914ce9..adcff34 100644
--- a/opcodes/bpf-desc.c
+++ b/opcodes/bpf-desc.c
@@ -520,6 +520,46 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
},
+/* sdiv $dstle,$imm32 */
+ {
+ BPF_INSN_SDIVILE, "sdivile", "sdiv", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* sdiv $dstle,$srcle */
+ {
+ BPF_INSN_SDIVRLE, "sdivrle", "sdiv", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* sdiv32 $dstle,$imm32 */
+ {
+ BPF_INSN_SDIV32ILE, "sdiv32ile", "sdiv32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* sdiv32 $dstle,$srcle */
+ {
+ BPF_INSN_SDIV32RLE, "sdiv32rle", "sdiv32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* smod $dstle,$imm32 */
+ {
+ BPF_INSN_SMODILE, "smodile", "smod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* smod $dstle,$srcle */
+ {
+ BPF_INSN_SMODRLE, "smodrle", "smod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* smod32 $dstle,$imm32 */
+ {
+ BPF_INSN_SMOD32ILE, "smod32ile", "smod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
+/* smod32 $dstle,$srcle */
+ {
+ BPF_INSN_SMOD32RLE, "smod32rle", "smod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+ },
/* neg $dstle */
{
BPF_INSN_NEGLE, "negle", "neg", 64,
@@ -770,6 +810,46 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
},
+/* sdiv $dstbe,$imm32 */
+ {
+ BPF_INSN_SDIVIBE, "sdivibe", "sdiv", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* sdiv $dstbe,$srcbe */
+ {
+ BPF_INSN_SDIVRBE, "sdivrbe", "sdiv", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* sdiv32 $dstbe,$imm32 */
+ {
+ BPF_INSN_SDIV32IBE, "sdiv32ibe", "sdiv32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* sdiv32 $dstbe,$srcbe */
+ {
+ BPF_INSN_SDIV32RBE, "sdiv32rbe", "sdiv32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* smod $dstbe,$imm32 */
+ {
+ BPF_INSN_SMODIBE, "smodibe", "smod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* smod $dstbe,$srcbe */
+ {
+ BPF_INSN_SMODRBE, "smodrbe", "smod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* smod32 $dstbe,$imm32 */
+ {
+ BPF_INSN_SMOD32IBE, "smod32ibe", "smod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
+/* smod32 $dstbe,$srcbe */
+ {
+ BPF_INSN_SMOD32RBE, "smod32rbe", "smod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+ },
/* neg $dstbe */
{
BPF_INSN_NEGBE, "negbe", "neg", 64,
diff --git a/opcodes/bpf-desc.h b/opcodes/bpf-desc.h
index dd24996..04e2af1 100644
--- a/opcodes/bpf-desc.h
+++ b/opcodes/bpf-desc.h
@@ -67,10 +67,11 @@ typedef enum insn_op_code_alu {
OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
, OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
, OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
- , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_JA = 0, OP_CODE_JEQ = 1
- , OP_CODE_JGT = 2, OP_CODE_JGE = 3, OP_CODE_JSET = 4, OP_CODE_JNE = 5
- , OP_CODE_JSGT = 6, OP_CODE_JSGE = 7, OP_CODE_CALL = 8, OP_CODE_EXIT = 9
- , OP_CODE_JLT = 10, OP_CODE_JLE = 11, OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
+ , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_SDIV = 14, OP_CODE_SMOD = 15
+ , OP_CODE_JA = 0, OP_CODE_JEQ = 1, OP_CODE_JGT = 2, OP_CODE_JGE = 3
+ , OP_CODE_JSET = 4, OP_CODE_JNE = 5, OP_CODE_JSGT = 6, OP_CODE_JSGE = 7
+ , OP_CODE_CALL = 8, OP_CODE_EXIT = 9, OP_CODE_JLT = 10, OP_CODE_JLE = 11
+ , OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
} INSN_OP_CODE_ALU;
/* Enum declaration for eBPF instruction source. */
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 72d5cd2..5a157ee 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -424,6 +424,54 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
& ifmt_addrle, { 0xcc }
},
+/* sdiv $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xe7 }
+ },
+/* sdiv $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xef }
+ },
+/* sdiv32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xe4 }
+ },
+/* sdiv32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xec }
+ },
+/* smod $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xf7 }
+ },
+/* smod $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xff }
+ },
+/* smod32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xf4 }
+ },
+/* smod32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xfc }
+ },
/* neg $dstle */
{
{ 0, 0, 0, 0 },
@@ -724,6 +772,54 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
& ifmt_addrbe, { 0xcc }
},
+/* sdiv $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xe7 }
+ },
+/* sdiv $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xef }
+ },
+/* sdiv32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xe4 }
+ },
+/* sdiv32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xec }
+ },
+/* smod $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xf7 }
+ },
+/* smod $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xff }
+ },
+/* smod32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xf4 }
+ },
+/* smod32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xfc }
+ },
/* neg $dstbe */
{
{ 0, 0, 0, 0 },
diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h
index 5d5150c..c3f9362 100644
--- a/opcodes/bpf-opc.h
+++ b/opcodes/bpf-opc.h
@@ -59,7 +59,9 @@ typedef enum cgen_insn_type {
, BPF_INSN_RSH32RLE, BPF_INSN_MODILE, BPF_INSN_MODRLE, BPF_INSN_MOD32ILE
, BPF_INSN_MOD32RLE, BPF_INSN_XORILE, BPF_INSN_XORRLE, BPF_INSN_XOR32ILE
, BPF_INSN_XOR32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
- , BPF_INSN_ARSH32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
+ , BPF_INSN_ARSH32RLE, BPF_INSN_SDIVILE, BPF_INSN_SDIVRLE, BPF_INSN_SDIV32ILE
+ , BPF_INSN_SDIV32RLE, BPF_INSN_SMODILE, BPF_INSN_SMODRLE, BPF_INSN_SMOD32ILE
+ , BPF_INSN_SMOD32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
, BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE, BPF_INSN_MOV32RLE, BPF_INSN_ADDIBE
, BPF_INSN_ADDRBE, BPF_INSN_ADD32IBE, BPF_INSN_ADD32RBE, BPF_INSN_SUBIBE
, BPF_INSN_SUBRBE, BPF_INSN_SUB32IBE, BPF_INSN_SUB32RBE, BPF_INSN_MULIBE
@@ -71,7 +73,9 @@ typedef enum cgen_insn_type {
, BPF_INSN_RSHRBE, BPF_INSN_RSH32IBE, BPF_INSN_RSH32RBE, BPF_INSN_MODIBE
, BPF_INSN_MODRBE, BPF_INSN_MOD32IBE, BPF_INSN_MOD32RBE, BPF_INSN_XORIBE
, BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_ARSHIBE
- , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_NEGBE
+ , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_SDIVIBE
+ , BPF_INSN_SDIVRBE, BPF_INSN_SDIV32IBE, BPF_INSN_SDIV32RBE, BPF_INSN_SMODIBE
+ , BPF_INSN_SMODRBE, BPF_INSN_SMOD32IBE, BPF_INSN_SMOD32RBE, BPF_INSN_NEGBE
, BPF_INSN_NEG32BE, BPF_INSN_MOVIBE, BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE
, BPF_INSN_MOV32RBE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
, BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSW
generated by cgit v1.1 at 2024-11-16 04:22:46 +0000