diff options
| -rw-r--r-- | sim/testsuite/sim/bfin/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/testsuite/sim/bfin/se_allopcodes.h | 5 |
2 files changed, 8 insertions, 2 deletions
diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog index ddcce86..11a3072 100644 --- a/sim/testsuite/sim/bfin/ChangeLog +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -1,5 +1,10 @@ 2013-06-23 Mike Frysinger <vapier@gentoo.org> + * se_allopcodes.h (_match): Simplify register test to one less insn. + Omit the SSYNC insn when compiling for the sim. + +2013-06-23 Mike Frysinger <vapier@gentoo.org> + * testutils.inc: Trim trailing whitespace. 2013-06-17 Mike Frysinger <vapier@gentoo.org> diff --git a/sim/testsuite/sim/bfin/se_allopcodes.h b/sim/testsuite/sim/bfin/se_allopcodes.h index 8f96125..796d5c4 100644 --- a/sim/testsuite/sim/bfin/se_allopcodes.h +++ b/sim/testsuite/sim/bfin/se_allopcodes.h @@ -102,8 +102,7 @@ _match: se_all_load_table /* is this the end of the table? */ - R4 = 0; - CC = R4 == R7; + CC = R7 == 0; IF CC jump _new_instruction; /* is the opcode (R0) greater than the 2nd entry in the table (R6) */ @@ -168,8 +167,10 @@ _legal_instruction: _next_instruction: se_all_next_insn +.ifdef BFIN_JTAG /* Make sure the opcode isn't in a write buffer */ SSYNC; +.endif R1 = P5; RETX = R1; |